Added signals to SampleSinkFifo including samples timings. Implements #1143 and part of #1139

2026-06-02 14:04:46 -04:00 · 2022-03-15 22:21:06 +01:00
parent a1babc9706
commit 09599e145e
5 changed files with 60 additions and 2 deletions
@@ -100,6 +100,8 @@ bool RTLSDRInput::openDevice()
        return false;
    }

+    m_sampleFifo.setWrittenSignalRateDivider(32);
+
    int device;

    if ((device = rtlsdr_get_index_by_serial(qPrintable(m_deviceAPI->getSamplingDeviceSerial()))) < 0)