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https://github.com/f4exb/sdrangel.git
synced 2024-12-23 01:55:48 -05:00
Fixed the rest of the warnings and main cmake file. Implements #663
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f4exb
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7c1e546f5f
commit
164b83a3ce
@ -305,8 +305,11 @@ if (SANITIZE_ADDRESS)
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endif()
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endif()
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# set compiler
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include(FindCompiler)
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if (C_CLANG OR C_GCC)
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra -Wvla -Woverloaded-virtual -ffast-math -ftree-vectorize ${EXTRA_FLAGS}")
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra -Wvla -ffast-math -ftree-vectorize ${EXTRA_FLAGS}")
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elseif (C_MSVC)
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -w -MP ${EXTRA_FLAGS}")
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endif()
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@ -317,9 +320,6 @@ elseif (C_GCC)
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fmax-errors=1")
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endif()
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# set compiler
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include(FindCompiler)
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# find cpu flags (and set compiler)
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include(FindCPUflags)
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@ -95,5 +95,7 @@ void ChirpChatDemodDecoder::decodeSymbols(const std::vector<unsigned short>& sym
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);
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}
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break;
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default:
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break;
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}
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}
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@ -183,8 +183,8 @@ bool DATVideoRender::InitializeFFMPEG()
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return false;
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}
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avcodec_register_all();
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av_register_all();
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//avcodec_register_all();
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//av_register_all();
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av_log_set_level(AV_LOG_FATAL);
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//av_log_set_level(AV_LOG_ERROR);
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@ -17,6 +17,8 @@
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#ifndef LEANSDR_DISCRMATH_H
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#define LEANSDR_DISCRMATH_H
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#pragma GCC diagnostic ignored "-Wshift-negative-value"
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#include <cstddef>
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namespace leansdr
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@ -235,51 +235,44 @@ const struct modcod_info
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// EN 302 307, section 5.4.4, Table 10
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float g1, g2, g3;
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} modcod_infos[32] = {
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{
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0,
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},
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{0, 0, cstln_base::BPSK, FEC12, 0.0, 0.0, 0.0, 0.0},
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// 1 - 11
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{360, 4, cstln_base::QPSK, FEC14, -2.35},
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{360, 4, cstln_base::QPSK, FEC13, -1.24},
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{360, 4, cstln_base::QPSK, FEC25, -0.30},
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{360, 4, cstln_base::QPSK, FEC12, 1.00},
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{360, 4, cstln_base::QPSK, FEC35, 2.23},
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{360, 4, cstln_base::QPSK, FEC23, 3.10},
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{360, 4, cstln_base::QPSK, FEC34, 4.03},
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{360, 4, cstln_base::QPSK, FEC45, 4.68},
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{360, 4, cstln_base::QPSK, FEC56, 5.18},
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{360, 4, cstln_base::QPSK, FEC89, 6.20},
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{360, 4, cstln_base::QPSK, FEC910, 6.42},
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{360, 4, cstln_base::QPSK, FEC14, -2.35, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC13, -1.24, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC25, -0.30, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC12, 1.00, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC35, 2.23, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC23, 3.10, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC34, 4.03, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC45, 4.68, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC56, 5.18, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC89, 6.20, 0.0, 0.0, 0.0},
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{360, 4, cstln_base::QPSK, FEC910, 6.42, 0.0, 0.0, 0.0},
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// 12 - 17
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{240, 8, cstln_base::PSK8, FEC35, 5.50},
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{240, 8, cstln_base::PSK8, FEC23, 6.62},
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{240, 8, cstln_base::PSK8, FEC34, 7.91},
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{240, 8, cstln_base::PSK8, FEC56, 9.35},
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{240, 8, cstln_base::PSK8, FEC89, 10.69},
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{240, 8, cstln_base::PSK8, FEC910, 10.98},
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{240, 8, cstln_base::PSK8, FEC35, 5.50, 0.0, 0.0, 0.0},
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{240, 8, cstln_base::PSK8, FEC23, 6.62, 0.0, 0.0, 0.0},
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{240, 8, cstln_base::PSK8, FEC34, 7.91, 0.0, 0.0, 0.0},
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{240, 8, cstln_base::PSK8, FEC56, 9.35, 0.0, 0.0, 0.0},
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{240, 8, cstln_base::PSK8, FEC89, 10.69, 0.0, 0.0, 0.0},
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{240, 8, cstln_base::PSK8, FEC910, 10.98, 0.0, 0.0, 0.0},
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// 18 - 23
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{180, 16, cstln_base::APSK16, FEC23, 8.97, 3.15},
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{180, 16, cstln_base::APSK16, FEC34, 10.21, 2.85},
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{180, 16, cstln_base::APSK16, FEC45, 11.03, 2.75},
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{180, 16, cstln_base::APSK16, FEC56, 11.61, 2.70},
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{180, 16, cstln_base::APSK16, FEC89, 12.89, 2.60},
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{180, 16, cstln_base::APSK16, FEC910, 13.13, 2.57},
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{180, 16, cstln_base::APSK16, FEC23, 8.97, 3.15, 0.0, 0.0},
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{180, 16, cstln_base::APSK16, FEC34, 10.21, 2.85, 0.0, 0.0},
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{180, 16, cstln_base::APSK16, FEC45, 11.03, 2.75, 0.0, 0.0},
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{180, 16, cstln_base::APSK16, FEC56, 11.61, 2.70, 0.0, 0.0},
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{180, 16, cstln_base::APSK16, FEC89, 12.89, 2.60, 0.0, 0.0},
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{180, 16, cstln_base::APSK16, FEC910, 13.13, 2.57, 0.0, 0.0},
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// 24 - 28
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{144, 32, cstln_base::APSK32, FEC34, 12.73, 2.84, 5.27},
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{144, 32, cstln_base::APSK32, FEC45, 13.64, 2.72, 4.87},
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{144, 32, cstln_base::APSK32, FEC56, 14.28, 2.64, 4.64},
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{144, 32, cstln_base::APSK32, FEC89, 15.69, 2.54, 4.33},
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{144, 32, cstln_base::APSK32, FEC910, 16.05, 2.53, 4.30},
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{144, 32, cstln_base::APSK32, FEC34, 12.73, 2.84, 5.27, 0.0},
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{144, 32, cstln_base::APSK32, FEC45, 13.64, 2.72, 4.87, 0.0},
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{144, 32, cstln_base::APSK32, FEC56, 14.28, 2.64, 4.64, 0.0},
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{144, 32, cstln_base::APSK32, FEC89, 15.69, 2.54, 4.33, 0.0},
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{144, 32, cstln_base::APSK32, FEC910, 16.05, 2.53, 4.30, 0.0},
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// 29 - 31
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{
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0,
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},
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{
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0,
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},
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{
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0,
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}};
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{0, 0, cstln_base::BPSK, FEC12, 0.0, 0.0, 0.0, 0.0},
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{0, 0, cstln_base::BPSK, FEC12, 0.0, 0.0, 0.0, 0.0},
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{0, 0, cstln_base::BPSK, FEC12, 0.0, 0.0, 0.0, 0.0}
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};
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// Assert that a MODCOD number is valid
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const modcod_info *check_modcod(int m)
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@ -621,7 +614,7 @@ struct s2_frame_receiver : runnable
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int nsymbols = MAX_SYMBOLS_PER_FRAME; // TBD Adjust after PLS decoding
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sampler_state ss = {in.rd(), mu, phase16, freqw16};
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sampler_state ss = {in.rd(), mu, phase16, freqw16, nullptr};
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sampler->update_freq(ss.fw16 / omega0);
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if (!in_power)
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@ -1889,10 +1882,10 @@ static const struct fec_info
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// Normal frames - must respect enum code_rate order
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{32208, 32400, 12, &ldpc_nf_fec12}, // FEC12 (was [FEC12] = {...} and so on. Does not compile with MSVC)
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{43040, 43200, 10, &ldpc_nf_fec23}, // FEC23
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{0}, // FEC46
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{0, 0, 0, nullptr}, // FEC46
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{48408, 48600, 12, &ldpc_nf_fec34}, // FEC34
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{53840, 54000, 10, &ldpc_nf_fec56}, // FEC56
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{0}, // FEC78
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{0, 0, 0, nullptr}, // FEC78
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{51648, 51840, 12, &ldpc_nf_fec45}, // FEC45
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{57472, 57600, 8, &ldpc_nf_fec89}, // FEC89
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{58192, 58320, 8, &ldpc_nf_fec910}, // FEC910
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@ -1905,13 +1898,13 @@ static const struct fec_info
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// Short frames - must respect enum code_rate order
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{7032, 7200, 12, &ldpc_sf_fec12}, // FEC12 (was [FEC12] = {...} and so on. Does not compile with MSVC)
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{10632, 10800, 12, &ldpc_sf_fec23}, // FEC23
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{}, // FEC46
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{0, 0, 0, nullptr}, // FEC46
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{11712, 11880, 12, &ldpc_sf_fec34}, // FEC34
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{13152, 13320, 12, &ldpc_sf_fec56}, // FEC56
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{}, // FEC78
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{0, 0, 0, nullptr}, // FEC78
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{12432, 12600, 12, &ldpc_sf_fec45}, // FEC45
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{14232, 14400, 12, &ldpc_sf_fec89}, // FEC89
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{}, // FEC910
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{0, 0, 0, nullptr}, // FEC910
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{3072, 3240, 12, &ldpc_sf_fec14}, // FEC14
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{5232, 5400, 12, &ldpc_sf_fec13}, // FEC13
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{6312, 6480, 12, &ldpc_sf_fec25}, // FEC25
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@ -52,6 +52,7 @@ struct MetisMISOSettings {
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void resetToDefaults();
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QByteArray serialize() const;
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bool deserialize(const QByteArray& data);
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MetisMISOSettings& operator=(const MetisMISOSettings&) = default;
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static int getSampleRateFromIndex(unsigned int index);
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};
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@ -468,7 +468,7 @@ quint64 MetisMISOUDPHandler::getRxCenterFrequency(int index)
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quint64 MetisMISOUDPHandler::getTxCenterFrequency()
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{
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qint64 requiredTxFrequency = m_settings.m_txCenterFrequency;
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qint64 requiredTxFrequency = m_settings.m_txCenterFrequency
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- (m_settings.m_txTransverterMode ? m_settings.m_txTransverterDeltaFrequency : 0);
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requiredTxFrequency = requiredTxFrequency < 0 ? 0 : requiredTxFrequency;
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return requiredTxFrequency;
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@ -77,6 +77,7 @@ struct TestMISettings {
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void resetToDefaults();
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QByteArray serialize() const;
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bool deserialize(const QByteArray& data);
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TestMISettings& operator=(const TestMISettings&) = default;
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};
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