VE7UWU/sdrangel
1
0
Fork 0
mirror of https://github.com/f4exb/sdrangel.git synced 2024-09-27 15:26:33 -04:00
Code Issues Projects Releases Wiki Activity

New scope: interim state (5)

Browse Source
This commit is contained in:
f4exb 2017-02-02 18:18:37 +01:00
parent a7bb81c70a
commit 1db62fd347
2 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
sdrbase/dsp/scopevisng.cpp
View File

@ -192,7 +192,7 @@ void ScopeVisNG::feed(const SampleVector::const_iterator& cbegin, const SampleVe
if (triggerCondition.m_triggerData.m_triggerDelay > 0) // there is a delay => initialize the delay
{
triggerCondition.m_triggerDelayCount = triggerCondition.m_triggerData.m_triggerDelay;
m_triggerState == TriggerDelay;
m_triggerState = TriggerDelay;
}
else
{
@ -297,7 +297,6 @@ bool ScopeVisNG::nextTrigger()
return false; // final
}
// TODO: should handle previous and live traces the same way from a stored buffer
int ScopeVisNG::processTraces(int beginPointDelta, int endPointDelta, TraceBackBuffer& traceBuffer, bool traceStart)
{
SampleVector::iterator begin = traceBuffer.current() - beginPointDelta;

13
sdrbase/dsp/scopevisng.h
View File

@ -555,7 +555,18 @@ private:
int m_sampleRate;
TraceBackDiscreteMemory m_traceDiscreteMemory; //!< Complex trace memory for triggered states TODO: vectorize when more than on input is allowed
bool nextTrigger();
/**
* Moves on to the next trigger if any or increments trigger count if in repeat mode
* - If not final it returns true
* - If final i.e. signal is actually triggerd it returns false
*/
bool nextTrigger(); //!< Returns true if not final
/**
* Process traces from complex trace memory buffer.
* - if finished it returns the number of unprocessed samples left in the buffer
* - if not finished it returns -1
*/
int processTraces(int beginPointDelta, int endPointDelta, TraceBackBuffer& traceBuffer, bool traceStart = false);
};