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mirror of https://github.com/f4exb/sdrangel.git synced 2024-11-26 01:39:05 -05:00

Send number of samples to write in the writeData signal. Ask for half the buffer size when more than half of it is consumed

This commit is contained in:
f4exb 2016-12-21 02:24:49 +01:00
parent b3a470efff
commit 441c2c1817
4 changed files with 17 additions and 17 deletions

View File

@ -168,10 +168,10 @@ QString DSPDeviceSinkEngine::sinkDeviceDescription()
return cmd.getDeviceDescription();
}
void DSPDeviceSinkEngine::work()
void DSPDeviceSinkEngine::work(int nbWriteSamples)
{
SampleSourceFifo* sampleFifo = m_deviceSampleSink->getSampleFifo();
unsigned int nbWriteSamples = sampleFifo->getChunkSize();
//unsigned int nbWriteSamples = sampleFifo->getChunkSize();
SampleVector::iterator writeBegin;
sampleFifo->getWriteIterator(writeBegin);
SampleVector::iterator writeAt = writeBegin;
@ -407,7 +407,7 @@ void DSPDeviceSinkEngine::handleSetSink(DeviceSampleSink* sink)
if(m_deviceSampleSink != 0)
{
qDebug("DSPDeviceSinkEngine::handleSetSink: set %s", qPrintable(sink->getDeviceDescription()));
connect(m_deviceSampleSink->getSampleFifo(), SIGNAL(dataWrite()), this, SLOT(handleData()), Qt::QueuedConnection);
connect(m_deviceSampleSink->getSampleFifo(), SIGNAL(dataWrite(int)), this, SLOT(handleData(int)), Qt::QueuedConnection);
}
else
{
@ -415,11 +415,11 @@ void DSPDeviceSinkEngine::handleSetSink(DeviceSampleSink* sink)
}
}
void DSPDeviceSinkEngine::handleData()
void DSPDeviceSinkEngine::handleData(int nbSamples)
{
if(m_state == StRunning)
{
work();
work(nbSamples);
}
}

View File

@ -105,7 +105,7 @@ private:
quint64 m_centerFrequency;
void run();
void work(); //!< transfer samples from beseband sources to sink if in running state
void work(int nbWriteSamples); //!< transfer samples from beseband sources to sink if in running state
State gotoIdle(); //!< Go to the idle state
State gotoInit(); //!< Go to the acquisition init state from idle
@ -115,7 +115,7 @@ private:
void handleSetSink(DeviceSampleSink* sink); //!< Manage sink setting
private slots:
void handleData(); //!< Handle data when samples from source FIFO are ready to be processed
void handleData(int nbSamples); //!< Handle data when samples have to be written to the sample FIFO
void handleInputMessages(); //!< Handle input message queue
void handleSynchronousMessages(); //!< Handle synchronous messages with the thread
void handleForwardToSpectrumSink(int nbSamples);

View File

@ -52,7 +52,7 @@ void SampleSourceFifo::init()
void SampleSourceFifo::readAdvance(SampleVector::iterator& readUntil, unsigned int nbSamples)
{
QMutexLocker mutexLocker(&m_mutex);
// QMutexLocker mutexLocker(&m_mutex);
assert(nbSamples < m_samplesChunkSize/2);
m_ir = (m_ir + nbSamples) % m_size;
@ -63,21 +63,21 @@ void SampleSourceFifo::readAdvance(SampleVector::iterator& readUntil, unsigned i
if (m_init)
{
emit dataWrite();
emit dataWrite(m_size);
m_init = false;
}
else if (i_delta > 0)
{
if (i_delta <= m_samplesChunkSize)
if (i_delta <= m_size/2) // m_samplesChunkSize)
{
emit dataWrite();
emit dataWrite(m_size/2);
}
}
else
{
if (i_delta + m_size <= m_samplesChunkSize)
if (i_delta + m_size <= m_size/2) //m_samplesChunkSize)
{
emit dataWrite();
emit dataWrite(m_size/2);
}
}
}
@ -88,7 +88,7 @@ void SampleSourceFifo::write(const Sample& sample)
m_data[m_iw+m_size] = sample;
{
QMutexLocker mutexLocker(&m_mutex);
// QMutexLocker mutexLocker(&m_mutex);
m_iw = (m_iw+1) % m_size;
}
}
@ -108,7 +108,7 @@ void SampleSourceFifo::bumpIndex(SampleVector::iterator& writeAt)
m_data[m_iw+m_size] = m_data[m_iw];
{
QMutexLocker mutexLocker(&m_mutex);
// QMutexLocker mutexLocker(&m_mutex);
m_iw = (m_iw+1) % m_size;
}

View File

@ -54,8 +54,8 @@ private:
QMutex m_mutex;
signals:
void dataWrite(); // signal data is read past a read chunk of samples and write is needed
void dataRead(int nbSamples); // signal a read has been done for a number of samples
void dataWrite(int nbSamples); // signal data is read past a threshold and writing new samples to fill in is needed
void dataRead(int nbSamples); // signal a read has been done for a number of samples
};
#endif /* SDRBASE_DSP_SAMPLESOURCEFIFO_H_ */