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USRP: Check if device supports automatic clock rate
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@ -50,10 +50,13 @@ bool DeviceUSRPParams::open(const QString &deviceStr, bool channelNumOnly)
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m_loRangeTx = m_dev->get_fe_tx_freq_range();
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m_loRangeTx = m_dev->get_fe_tx_freq_range();
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// For some devices (B210), rx/tx_rates vary with master_clock_rate
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// For some devices (B210), rx/tx_rates vary with master_clock_rate
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// which can be set automatically by UHD. For other devices,
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// master_clock_rate must be set manually (currently as a device arg)
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// Note master_clock_rate is rate between FPGA and RFIC
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// Note master_clock_rate is rate between FPGA and RFIC
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// tx/rx_rate is rate between PC and FPGA
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// tx/rx_rate is rate between PC and FPGA
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uhd::meta_range_t clockRange = m_dev->get_master_clock_rate_range();
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uhd::meta_range_t clockRange = m_dev->get_master_clock_rate_range();
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if (clockRange.start() == clockRange.stop())
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uhd::property_tree::sptr properties = m_dev->get_device()->get_tree();
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if ((clockRange.start() == clockRange.stop()) || !properties->exists("/mboards/0/auto_tick_rate"))
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{
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{
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m_srRangeRx = m_dev->get_rx_rates();
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m_srRangeRx = m_dev->get_rx_rates();
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m_srRangeTx = m_dev->get_tx_rates();
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m_srRangeTx = m_dev->get_tx_rates();
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@ -73,9 +76,7 @@ bool DeviceUSRPParams::open(const QString &deviceStr, bool channelNumOnly)
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m_srRangeTx = uhd::meta_range_t(std::min(txLow.start(), txHigh.start()), std::max(txLow.stop(), txHigh.stop()));
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m_srRangeTx = uhd::meta_range_t(std::min(txLow.start(), txHigh.start()), std::max(txLow.stop(), txHigh.stop()));
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// Need to restore automatic clock rate
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// Need to restore automatic clock rate
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uhd::property_tree::sptr properties = m_dev->get_device()->get_tree();
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if (properties->exists("/mboards/0/auto_tick_rate")) {
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if (properties->exists("/mboards/0/auto_tick_rate"))
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{
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properties->access<bool>("/mboards/0/auto_tick_rate").set(true);
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properties->access<bool>("/mboards/0/auto_tick_rate").set(true);
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}
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}
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}
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}
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