mirror of https://github.com/f4exb/sdrangel.git
BFM demod: RDS demod debug #1
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f4exb
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14f72bae8a
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dcea42d309
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@ -28,10 +28,11 @@ RDSDemod::RDSDemod()
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{
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m_srate = 250000;
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m_fsc = 57000.0;
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m_subcarrPhi = 0;
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m_subcarrPhi_1 = 0;
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m_dPhiSc = 0;
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m_subcarrBB_1 = 0.0;
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m_rdsClockPhase = 0.0;
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m_rdsClockPhase_1 = 0.0;
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m_rdsClockOffset = 0.0;
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m_rdsClockLO = 0.0;
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m_rdsClockLO_1 = 0.0;
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@ -57,63 +58,28 @@ void RDSDemod::setSampleRate(int srate)
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void RDSDemod::process(Real demod, Real pilotPhaseSample)
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{
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/*
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// Subcarrier downmix & phase recovery
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m_subcarrPhi += 2 * M_PI * m_fsc * (1.0 / m_srate);
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m_subcarrBB[0] = filter_lp_2400_iq(demod * cos(m_subcarrPhi), 0);
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m_subcarrBB[1] = filter_lp_2400_iq(demod * sin(m_subcarrPhi), 1);
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pilotPhaseSample = fmod(pilotPhaseSample, M_PI);
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m_dPhiSc = 2 * filter_lp_pll(m_subcarrBB[1] * m_subcarrBB[0]);
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m_subcarrPhi -= m_pllBeta * m_dPhiSc; //prev_loop;
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m_fsc -= .5 * m_pllBeta * m_dPhiSc; //prev_loop;
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m_dPhiSc = pilotPhaseSample - m_subcarrPhi_1;
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// 1187.5 Hz clock
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m_rdsClockPhase = m_subcarrPhi / 48.0 + m_rdsClockOffset;
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m_rdsClockLO = (fmod(m_rdsClockPhase, 2 * M_PI) < M_PI ? 1 : -1);
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// Clock phase recovery
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if (sign(m_subcarrBB_1) != sign(m_subcarrBB[0]))
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if (m_dPhiSc < 0)
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{
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Real d_cphi = fmod(m_rdsClockPhase, M_PI);
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if (d_cphi >= M_PI_2)
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{
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d_cphi -= M_PI;
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}
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m_rdsClockOffset -= 0.005 * d_cphi;
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m_dPhiSc += M_PI;
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}
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// Decimate band-limited signal
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if (m_numSamples % 8 == 0)
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{
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// biphase symbol integrate & dump
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m_acc += m_subcarrBB[0] * m_rdsClockLO;
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if (sign(m_rdsClockLO) != sign(m_rdsClockLO_1))
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{
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biphase(m_acc, m_fsc);
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m_acc = 0;
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}
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m_rdsClockLO_1 = m_rdsClockLO;
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}
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m_subcarrBB_1 = m_subcarrBB[0];
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*/
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m_subcarrBB[0] = filter_lp_2400_iq(demod, 0); // working on real part only
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// 1187.5 Hz clock from 19 kHz pilot
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m_rdsClockPhase = (pilotPhaseSample / 16.0) + m_rdsClockOffset;
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m_rdsClockLO = (m_rdsClockPhase > 0.0 ? 1.0 : -1.0);
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m_rdsClockPhase += (m_dPhiSc / 16.0) + m_rdsClockOffset;
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m_rdsClockPhase = fmod(m_rdsClockPhase, M_PI);
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m_rdsClockLO = (m_rdsClockPhase < 0.0 ? -1.0 : 1.0);
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// Clock phase recovery
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if (sign(m_subcarrBB_1) != sign(m_subcarrBB[0]))
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{
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Real d_cphi = fmod(m_rdsClockPhase, M_PI);
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Real d_cphi = m_rdsClockPhase;
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if (d_cphi >= M_PI_2)
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{
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@ -123,22 +89,11 @@ void RDSDemod::process(Real demod, Real pilotPhaseSample)
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m_rdsClockOffset -= 0.005 * d_cphi;
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}
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// Decimate band-limited signal
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if (m_numSamples % 8 == 0)
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{
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// biphase symbol integrate & dump
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m_acc += m_subcarrBB[0] * m_rdsClockLO;
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if (sign(m_rdsClockLO) != sign(m_rdsClockLO_1))
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{
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biphase(m_acc, 57000.0);
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m_acc = 0;
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}
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m_rdsClockLO_1 = m_rdsClockLO;
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}
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biphase(m_acc, m_rdsClockPhase - m_rdsClockPhase_1);
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m_numSamples++;
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m_subcarrPhi_1 = pilotPhaseSample;
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m_rdsClockPhase_1 = m_rdsClockPhase;
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}
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Real RDSDemod::filter_lp_2400_iq(Real input, int iqIndex)
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@ -171,39 +126,25 @@ int RDSDemod::sign(Real a)
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return (a >= 0 ? 1 : 0);
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}
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void RDSDemod::biphase(Real acc, Real fsc)
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void RDSDemod::biphase(Real acc, Real clockDPhi)
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{
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if (sign(acc) != sign(m_acc_1)) // two successive of different sign: error detected
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if (clockDPhi < 0)
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{
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m_totErrors[m_counter % 2]++;
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clockDPhi += M_PI;
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}
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if (m_counter % 2 == m_readingFrame) // two successive of the same sign: OK
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{
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print_delta(sign(acc + m_acc_1));
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}
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double fsc = (m_dPhiSc / (2.0 * M_PI)) * m_srate;
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double fclk = (clockDPhi / (2.0 * M_PI)) * m_srate;
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if (m_counter == 0)
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{
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if (m_totErrors[1 - m_readingFrame] < m_totErrors[m_readingFrame])
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{
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m_readingFrame = 1 - m_readingFrame;
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double qua = (1.0 * abs(m_totErrors[0] - m_totErrors[1]) / (m_totErrors[0] + m_totErrors[1])) * 100;
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qDebug("RDSDemod::biphase: frame: %d errs: %3d %3d qual: %3.0f%% pll: %.1f (%.1f ppm)",
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m_readingFrame,
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m_totErrors[0],
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m_totErrors[1],
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qua,
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fsc,
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(57000.0-fsc)/57000.0*1000000);
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}
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m_totErrors[0] = 0;
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m_totErrors[1] = 0;
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qDebug("RDSDemod::biphase: frame: %d pll: %.3f (ppm: %+8.3f) clk: %8.1f",
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m_readingFrame,
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fsc,
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((fsc - 19000.0) / 19000.0) * 1000000,
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fclk);
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}
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m_acc_1 = acc; // memorize (z^-1)
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m_counter = (m_counter + 1) % 800;
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}
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@ -34,7 +34,7 @@ protected:
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Real filter_lp_2400_iq(Real in, int iqIndex);
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Real filter_lp_pll(Real input);
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int sign(Real a);
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void biphase(Real acc, Real fsc);
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void biphase(Real acc, Real dPhiClock);
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void print_delta(char b);
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void output_bit(char b);
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@ -45,11 +45,12 @@ private:
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Real m_yv[2][2+1];
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Real m_xw[2];
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Real m_yw[2];
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Real m_subcarrPhi;
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Real m_subcarrPhi_1;
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Real m_subcarrBB[2];
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Real m_dPhiSc;
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Real m_subcarrBB_1;
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Real m_rdsClockPhase;
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Real m_rdsClockPhase_1;
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Real m_rdsClockOffset;
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Real m_rdsClockLO;
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Real m_rdsClockLO_1;
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