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BFM demod: RDS demod debug #1

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This commit is contained in:
f4exb 2015-12-11 19:33:10 +01:00
parent 14f72bae8a
commit dcea42d309
2 changed files with 28 additions and 86 deletions
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109
plugins/channel/bfm/rdsdemod.cpp
View File

@ -28,10 +28,11 @@ RDSDemod::RDSDemod()
{
m_srate = 250000;
m_fsc = 57000.0;
m_subcarrPhi = 0;
m_subcarrPhi_1 = 0;
m_dPhiSc = 0;
m_subcarrBB_1 = 0.0;
m_rdsClockPhase = 0.0;
m_rdsClockPhase_1 = 0.0;
m_rdsClockOffset = 0.0;
m_rdsClockLO = 0.0;
m_rdsClockLO_1 = 0.0;
@ -57,63 +58,28 @@ void RDSDemod::setSampleRate(int srate)
void RDSDemod::process(Real demod, Real pilotPhaseSample)
{
/*
// Subcarrier downmix & phase recovery
m_subcarrPhi += 2 * M_PI * m_fsc * (1.0 / m_srate);
m_subcarrBB[0] = filter_lp_2400_iq(demod * cos(m_subcarrPhi), 0);
m_subcarrBB[1] = filter_lp_2400_iq(demod * sin(m_subcarrPhi), 1);
pilotPhaseSample = fmod(pilotPhaseSample, M_PI);
m_dPhiSc = 2 * filter_lp_pll(m_subcarrBB[1] * m_subcarrBB[0]);
m_subcarrPhi -= m_pllBeta * m_dPhiSc; //prev_loop;
m_fsc -= .5 * m_pllBeta * m_dPhiSc; //prev_loop;
m_dPhiSc = pilotPhaseSample - m_subcarrPhi_1;
// 1187.5 Hz clock
m_rdsClockPhase = m_subcarrPhi / 48.0 + m_rdsClockOffset;
m_rdsClockLO = (fmod(m_rdsClockPhase, 2 * M_PI) < M_PI ? 1 : -1);
// Clock phase recovery
if (sign(m_subcarrBB_1) != sign(m_subcarrBB[0]))
if (m_dPhiSc < 0)
{
Real d_cphi = fmod(m_rdsClockPhase, M_PI);
if (d_cphi >= M_PI_2)
{
d_cphi -= M_PI;
}
m_rdsClockOffset -= 0.005 * d_cphi;
m_dPhiSc += M_PI;
}
// Decimate band-limited signal
if (m_numSamples % 8 == 0)
{
// biphase symbol integrate & dump
m_acc += m_subcarrBB[0] * m_rdsClockLO;
if (sign(m_rdsClockLO) != sign(m_rdsClockLO_1))
{
biphase(m_acc, m_fsc);
m_acc = 0;
}
m_rdsClockLO_1 = m_rdsClockLO;
}
m_subcarrBB_1 = m_subcarrBB[0];
*/
m_subcarrBB[0] = filter_lp_2400_iq(demod, 0); // working on real part only
// 1187.5 Hz clock from 19 kHz pilot
m_rdsClockPhase = (pilotPhaseSample / 16.0) + m_rdsClockOffset;
m_rdsClockLO = (m_rdsClockPhase > 0.0 ? 1.0 : -1.0);
m_rdsClockPhase += (m_dPhiSc / 16.0) + m_rdsClockOffset;
m_rdsClockPhase = fmod(m_rdsClockPhase, M_PI);
m_rdsClockLO = (m_rdsClockPhase < 0.0 ? -1.0 : 1.0);
// Clock phase recovery
if (sign(m_subcarrBB_1) != sign(m_subcarrBB[0]))
{
Real d_cphi = fmod(m_rdsClockPhase, M_PI);
Real d_cphi = m_rdsClockPhase;
if (d_cphi >= M_PI_2)
{
@ -123,22 +89,11 @@ void RDSDemod::process(Real demod, Real pilotPhaseSample)
m_rdsClockOffset -= 0.005 * d_cphi;
}
// Decimate band-limited signal
if (m_numSamples % 8 == 0)
{
// biphase symbol integrate & dump
m_acc += m_subcarrBB[0] * m_rdsClockLO;
if (sign(m_rdsClockLO) != sign(m_rdsClockLO_1))
{
biphase(m_acc, 57000.0);
m_acc = 0;
}
m_rdsClockLO_1 = m_rdsClockLO;
}
biphase(m_acc, m_rdsClockPhase - m_rdsClockPhase_1);
m_numSamples++;
m_subcarrPhi_1 = pilotPhaseSample;
m_rdsClockPhase_1 = m_rdsClockPhase;
}
Real RDSDemod::filter_lp_2400_iq(Real input, int iqIndex)
@ -171,39 +126,25 @@ int RDSDemod::sign(Real a)
return (a >= 0 ? 1 : 0);
}
void RDSDemod::biphase(Real acc, Real fsc)
void RDSDemod::biphase(Real acc, Real clockDPhi)
{
if (sign(acc) != sign(m_acc_1)) // two successive of different sign: error detected
if (clockDPhi < 0)
{
m_totErrors[m_counter % 2]++;
clockDPhi += M_PI;
}
if (m_counter % 2 == m_readingFrame) // two successive of the same sign: OK
{
print_delta(sign(acc + m_acc_1));
}
double fsc = (m_dPhiSc / (2.0 * M_PI)) * m_srate;
double fclk = (clockDPhi / (2.0 * M_PI)) * m_srate;
if (m_counter == 0)
{
if (m_totErrors[1 - m_readingFrame] < m_totErrors[m_readingFrame])
{
m_readingFrame = 1 - m_readingFrame;
double qua = (1.0 * abs(m_totErrors[0] - m_totErrors[1]) / (m_totErrors[0] + m_totErrors[1])) * 100;
qDebug("RDSDemod::biphase: frame: %d errs: %3d %3d qual: %3.0f%% pll: %.1f (%.1f ppm)",
m_readingFrame,
m_totErrors[0],
m_totErrors[1],
qua,
fsc,
(57000.0-fsc)/57000.0*1000000);
}
m_totErrors[0] = 0;
m_totErrors[1] = 0;
qDebug("RDSDemod::biphase: frame: %d pll: %.3f (ppm: %+8.3f) clk: %8.1f",
m_readingFrame,
fsc,
((fsc - 19000.0) / 19000.0) * 1000000,
fclk);
}
m_acc_1 = acc; // memorize (z^-1)
m_counter = (m_counter + 1) % 800;
}

5
plugins/channel/bfm/rdsdemod.h
View File

@ -34,7 +34,7 @@ protected:
Real filter_lp_2400_iq(Real in, int iqIndex);
Real filter_lp_pll(Real input);
int sign(Real a);
void biphase(Real acc, Real fsc);
void biphase(Real acc, Real dPhiClock);
void print_delta(char b);
void output_bit(char b);
@ -45,11 +45,12 @@ private:
Real m_yv[2][2+1];
Real m_xw[2];
Real m_yw[2];
Real m_subcarrPhi;
Real m_subcarrPhi_1;
Real m_subcarrBB[2];
Real m_dPhiSc;
Real m_subcarrBB_1;
Real m_rdsClockPhase;
Real m_rdsClockPhase_1;
Real m_rdsClockOffset;
Real m_rdsClockLO;
Real m_rdsClockLO_1;