VE7UWU/sdrangel
1
0
Fork 0
mirror of https://github.com/f4exb/sdrangel.git synced 2026-06-07 16:34:45 -04:00
Code Issues Projects Releases Wiki Activity
10,020 Commits 3 Branches 383 Tags
0bd4bbe0d4d704fcfa43316d9f92387debf442f6
Commit Graph

4 Commits

Author SHA1 Message Date
srcejon 41716632d4 Remove use of deprecated QRegExp. 2024-06-10 14:01:57 +01:00
Daniele Forsi 8c3f7e3775 Remove unused includes and use more direct includes 2024-04-11 23:31:34 +02:00
srcejon 2a29a69a3e AIS, DSC, End-of-Train, Packet, Radiosonde: All packet date/time to come from File Input device or system clock. 2024-03-03 21:24:54 +00:00
srcejon 5919f234c0 Add End-of-Train demodulator for #1866 2024-03-03 13:40:42 +00:00