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mirror of https://github.com/f4exb/sdrangel.git synced 2024-11-14 12:22:00 -05:00
Commit Graph

14 Commits

Author SHA1 Message Date
f4exb
3a3d8e3dcb activated compiler warnings 2017-05-25 20:13:34 +02:00
f4exb
cf267b1254 Code warnings in Eclipse cleanup 2017-05-05 10:40:45 +02:00
f4exb
9b72a3c064 FileSink plugin: fixed possible segfault 2017-01-03 23:22:06 +01:00
f4exb
fa0afb6c92 Tx support: implemented final interpolation stage in FileSink plugin 2017-01-02 03:14:46 +01:00
f4exb
e05822ba02 Implement own FIFO in BasebandSampleSource. SampleSourceFIFO: remove useless chunk size completely and set initial fill to only half the FIFO size 2016-12-23 14:29:42 +01:00
f4exb
1afd8df5f9 Modulators: changed single Tx channel samples feed handling 2016-12-22 23:39:06 +01:00
f4exb
d7918f0ff4 Restore tx implementation roadmap 2016-12-21 21:47:56 +01:00
f4exb
1769a145de FileSink plugin: return to a 1s sample buffer 2016-12-21 02:25:20 +01:00
f4exb
cd3191a9dc FileSink plugin: use larger buffer in thread 2016-12-20 00:26:43 +01:00
f4exb
0fc6d95357 Tx ph.1: fixed read pointer management when getting new samples 2016-10-25 03:31:36 +02:00
f4exb
ee55747c0b Tx ph.1: FileSink: set sample source FIFO size depending on sample rate 2016-10-25 02:34:29 +02:00
f4exb
289c1a203f Tx ph.1: Sample source FIFO read with signal. Use a specific spectrum sink (vis) reference in Device sink engine for main spectrum rendering 2016-10-24 18:06:44 +02:00
f4exb
fbb816ebdf Tx ph.1: Added FileSink (2) compiles. Added plugin/samplesink in all builds 2016-10-19 22:32:14 +02:00
f4exb
6c82c36958 Tx ph.1: Added FileSink (1) 2016-10-19 18:42:57 +02:00