mirror of
https://github.com/f4exb/sdrangel.git
synced 2024-11-08 09:36:02 -05:00
383 lines
9.3 KiB
C
383 lines
9.3 KiB
C
/*
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* Copyright (C) 2010 DSD Author
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* GPG Key ID: 0x3F1D7FD0 (74EF 430D F7F2 0A48 FCE6 F630 FAA2 635D 3F1D 7FD0)
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
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* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "dsd.h"
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#include "dmr_const.h"
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void
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processDMRvoice (dsd_opts * opts, dsd_state * state)
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{
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// extracts AMBE frames from DMR frame
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int i, j, dibit;
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int *dibit_p;
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char ambe_fr[4][24];
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char ambe_fr2[4][24];
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char ambe_fr3[4][24];
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const int *w, *x, *y, *z;
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char sync[25];
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char syncdata[25];
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char cachdata[13];
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int mutecurrentslot;
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int msMode;
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#ifdef DMR_DUMP
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int k;
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char syncbits[49];
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char cachbits[25];
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#endif
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mutecurrentslot = 0;
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msMode = 0;
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dibit_p = state->dibit_buf_p - 144;
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for (j = 0; j < 6; j++)
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{
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// 2nd half of previous slot
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for (i = 0; i < 54; i++)
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{
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if (j > 0)
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{
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dibit = getDibit (opts, state);
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}
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else
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{
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dibit = *dibit_p;
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dibit_p++;
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if (opts->inverted_dmr == 1)
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{
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dibit = (dibit ^ 2);
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}
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}
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}
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// CACH
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for (i = 0; i < 12; i++)
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{
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if (j > 0)
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{
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dibit = getDibit (opts, state);
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}
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else
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{
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dibit = *dibit_p;
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dibit_p++;
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if (opts->inverted_dmr == 1)
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{
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dibit = (dibit ^ 2);
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}
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}
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cachdata[i] = dibit;
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if (i == 2)
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{
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state->currentslot = (1 & (dibit >> 1)); // bit 1
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if (state->currentslot == 0)
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{
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state->slot0light[0] = '[';
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state->slot0light[6] = ']';
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state->slot1light[0] = ' ';
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state->slot1light[6] = ' ';
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}
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else
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{
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state->slot1light[0] = '[';
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state->slot1light[6] = ']';
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state->slot0light[0] = ' ';
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state->slot0light[6] = ' ';
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}
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}
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}
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cachdata[12] = 0;
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#ifdef DMR_DUMP
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k = 0;
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for (i = 0; i < 12; i++)
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{
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dibit = cachdata[i];
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cachbits[k] = (1 & (dibit >> 1)) + 48; // bit 1
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k++;
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cachbits[k] = (1 & dibit) + 48; // bit 0
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k++;
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}
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cachbits[24] = 0;
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printf ("%s ", cachbits);
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#endif
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// current slot frame 1
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w = rW;
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x = rX;
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y = rY;
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z = rZ;
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for (i = 0; i < 36; i++)
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{
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if (j > 0)
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{
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dibit = getDibit (opts, state);
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}
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else
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{
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dibit = *dibit_p;
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dibit_p++;
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if (opts->inverted_dmr == 1)
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{
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dibit = (dibit ^ 2);
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}
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}
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ambe_fr[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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// current slot frame 2 first half
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w = rW;
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x = rX;
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y = rY;
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z = rZ;
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for (i = 0; i < 18; i++)
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{
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if (j > 0)
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{
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dibit = getDibit (opts, state);
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}
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else
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{
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dibit = *dibit_p;
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dibit_p++;
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if (opts->inverted_dmr == 1)
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{
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dibit = (dibit ^ 2);
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}
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}
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ambe_fr2[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr2[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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// signaling data or sync
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for (i = 0; i < 24; i++)
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{
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if (j > 0)
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{
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dibit = getDibit (opts, state);
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}
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else
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{
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dibit = *dibit_p;
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dibit_p++;
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if (opts->inverted_dmr == 1)
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{
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dibit = (dibit ^ 2);
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}
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}
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syncdata[i] = dibit;
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sync[i] = (dibit | 1) + 48;
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}
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sync[24] = 0;
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syncdata[24] = 0;
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if ((strcmp (sync, DMR_BS_DATA_SYNC) == 0) || (strcmp (sync, DMR_MS_DATA_SYNC) == 0))
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{
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mutecurrentslot = 1;
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if (state->currentslot == 0)
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{
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sprintf (state->slot0light, "[slot0]");
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}
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else
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{
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sprintf (state->slot1light, "[slot1]");
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}
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}
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else if ((strcmp (sync, DMR_BS_VOICE_SYNC) == 0) || (strcmp (sync, DMR_MS_VOICE_SYNC) == 0))
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{
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mutecurrentslot = 0;
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if (state->currentslot == 0)
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{
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sprintf (state->slot0light, "[SLOT0]");
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}
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else
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{
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sprintf (state->slot1light, "[SLOT1]");
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}
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}
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if ((strcmp (sync, DMR_MS_VOICE_SYNC) == 0) || (strcmp (sync, DMR_MS_DATA_SYNC) == 0))
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{
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msMode = 1;
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}
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if ((j == 0) && (opts->errorbars == 1))
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{
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printf ("%s %s VOICE e:", state->slot0light, state->slot1light);
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}
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#ifdef DMR_DUMP
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k = 0;
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for (i = 0; i < 24; i++)
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{
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dibit = syncdata[i];
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syncbits[k] = (1 & (dibit >> 1)) + 48; // bit 1
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k++;
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syncbits[k] = (1 & dibit) + 48; // bit 0
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k++;
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}
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syncbits[48] = 0;
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printf ("%s ", syncbits);
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#endif
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// current slot frame 2 second half
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for (i = 0; i < 18; i++)
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{
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dibit = getDibit (opts, state);
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ambe_fr2[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr2[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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if (mutecurrentslot == 0)
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{
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if (state->firstframe == 1)
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{ // we don't know if anything received before the first sync after no carrier is valid
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state->firstframe = 0;
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}
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else
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{
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processMbeFrame (opts, state, NULL, ambe_fr, NULL);
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processMbeFrame (opts, state, NULL, ambe_fr2, NULL);
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}
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}
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// current slot frame 3
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w = rW;
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x = rX;
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y = rY;
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z = rZ;
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for (i = 0; i < 36; i++)
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{
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dibit = getDibit (opts, state);
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ambe_fr3[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr3[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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if (mutecurrentslot == 0)
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{
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processMbeFrame (opts, state, NULL, ambe_fr3, NULL);
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}
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// CACH
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for (i = 0; i < 12; i++)
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{
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dibit = getDibit (opts, state);
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cachdata[i] = dibit;
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}
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cachdata[12] = 0;
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#ifdef DMR_DUMP
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k = 0;
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for (i = 0; i < 12; i++)
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{
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dibit = cachdata[i];
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cachbits[k] = (1 & (dibit >> 1)) + 48; // bit 1
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k++;
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cachbits[k] = (1 & dibit) + 48; // bit 0
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k++;
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}
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cachbits[24] = 0;
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printf ("%s ", cachbits);
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#endif
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// next slot
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skipDibit (opts, state, 54);
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// signaling data or sync
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for (i = 0; i < 24; i++)
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{
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dibit = getDibit (opts, state);
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syncdata[i] = dibit;
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sync[i] = (dibit | 1) + 48;
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}
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sync[24] = 0;
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syncdata[24] = 0;
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if ((strcmp (sync, DMR_BS_DATA_SYNC) == 0) || (msMode == 1))
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{
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if (state->currentslot == 0)
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{
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sprintf (state->slot1light, " slot1 ");
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}
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else
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{
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sprintf (state->slot0light, " slot0 ");
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}
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}
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else if (strcmp (sync, DMR_BS_VOICE_SYNC) == 0)
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{
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if (state->currentslot == 0)
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{
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sprintf (state->slot1light, " SLOT1 ");
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}
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else
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{
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sprintf (state->slot0light, " SLOT0 ");
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}
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}
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#ifdef DMR_DUMP
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k = 0;
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for (i = 0; i < 24; i++)
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{
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dibit = syncdata[i];
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syncbits[k] = (1 & (dibit >> 1)) + 48; // bit 1
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k++;
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syncbits[k] = (1 & dibit) + 48; // bit 0
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k++;
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}
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syncbits[48] = 0;
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printf ("%s ", syncbits);
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#endif
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if (j == 5)
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{
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// 2nd half next slot
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skipDibit (opts, state, 54);
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// CACH
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skipDibit (opts, state, 12);
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// first half current slot
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skipDibit (opts, state, 54);
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}
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}
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if (opts->errorbars == 1)
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{
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printf ("\n");
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}
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}
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