mirror of https://github.com/f4exb/sdrangel.git
595 lines
22 KiB
C++
595 lines
22 KiB
C++
/**
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@file Connection_uLimeSDRing.cpp
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@author Lime Microsystems
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@brief Implementation of uLimeSDR board connection (streaming API)
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*/
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#include "Connection_uLimeSDR.h"
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#include "fifo.h"
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#include <LMS7002M.h>
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#include <iostream>
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#include <thread>
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#include <chrono>
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#include <algorithm>
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#include <complex>
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#include <ciso646>
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#include <vector>
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#include <FPGA_common.h>
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#include "ErrorReporting.h"
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using namespace lime;
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using namespace std;
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#define __unix__
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/** @brief Configures FPGA PLLs to LimeLight interface frequency
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*/
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int Connection_uLimeSDR::UpdateExternalDataRate(const size_t channel, const double txRate, const double rxRate, const double txPhase, const double rxPhase)
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{
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const float txInterfaceClk = 2 * txRate;
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const float rxInterfaceClk = 2 * rxRate;
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int status = 0;
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mExpectedSampleRate = rxRate;
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lime::fpga::FPGA_PLL_clock clocks[4];
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clocks[0].bypass = false;
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clocks[0].index = 0;
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clocks[0].outFrequency = txInterfaceClk;
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clocks[0].phaseShift_deg = 0;
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clocks[0].findPhase = false;
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clocks[1].bypass = false;
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clocks[1].index = 1;
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clocks[1].outFrequency = txInterfaceClk;
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clocks[1].findPhase = false;
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clocks[1].phaseShift_deg = txPhase;
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clocks[2].bypass = false;
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clocks[2].index = 2;
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clocks[2].outFrequency = rxInterfaceClk;
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clocks[2].phaseShift_deg = 0;
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clocks[2].findPhase = false;
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clocks[3].bypass = false;
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clocks[3].index = 3;
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clocks[3].outFrequency = rxInterfaceClk;
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clocks[3].findPhase = false;
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clocks[3].phaseShift_deg = rxPhase;
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status = lime::fpga::SetPllFrequency(this, 0, rxInterfaceClk, clocks, 4);
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return status;
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}
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/** @brief Configures FPGA PLLs to LimeLight interface frequency
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*/
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int Connection_uLimeSDR::UpdateExternalDataRate(const size_t channel, const double txRate_Hz, const double rxRate_Hz)
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{
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const float txInterfaceClk = 2 * txRate_Hz;
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const float rxInterfaceClk = 2 * rxRate_Hz;
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int status = 0;
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uint32_t reg20;
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const double rxPhC1[] = { 91.08, 89.46 };
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const double rxPhC2[] = { -1 / 6e6, 1.24e-6 };
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const double txPhC1[] = { 89.75, 89.61 };
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const double txPhC2[] = { -3.0e-7, 2.71e-7 };
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const std::vector<uint32_t> spiAddr = { 0x0021, 0x0022, 0x0023, 0x0024,
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0x0027, 0x002A, 0x0400, 0x040C,
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0x040B, 0x0400, 0x040B, 0x0400 };
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const int bakRegCnt = spiAddr.size() - 4;
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auto info = GetDeviceInfo();
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const int addrLMS7002M = info.addrsLMS7002M.at(0);
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bool phaseSearch = false;
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//if (this->chipVersion == 0x3841) //0x3840 LMS7002Mr2, 0x3841 LMS7002Mr3
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/*if (rxInterfaceClk >= 5e6 || txInterfaceClk >= 5e6)
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phaseSearch = true;*/
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mExpectedSampleRate = rxRate_Hz;
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std::vector<uint32_t> dataWr;
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std::vector<uint32_t> dataRd;
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if (phaseSearch)
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{
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dataWr.resize(spiAddr.size());
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dataRd.resize(spiAddr.size());
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//backup registers
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dataWr[0] = (uint32_t(0x0020) << 16);
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TransactSPI(addrLMS7002M, dataWr.data(), ®20, 1);
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dataWr[0] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFD; //msbit 1=SPI write
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TransactSPI(addrLMS7002M, dataWr.data(), nullptr, 1);
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for (int i = 0; i < bakRegCnt; ++i)
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dataWr[i] = (spiAddr[i] << 16);
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TransactSPI(addrLMS7002M, dataWr.data(), dataRd.data(), bakRegCnt);
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//UpdateThreads(true);
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}
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if ((txInterfaceClk >= 5e6) && (rxInterfaceClk >= 5e6))
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{
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lime::fpga::FPGA_PLL_clock clocks[4];
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clocks[0].bypass = false;
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clocks[0].index = 0;
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clocks[0].outFrequency = txInterfaceClk;
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clocks[0].phaseShift_deg = 0;
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clocks[0].findPhase = false;
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clocks[1].bypass = false;
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clocks[1].index = 1;
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clocks[1].outFrequency = txInterfaceClk;
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clocks[1].findPhase = false;
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if (this->chipVersion == 0x3841)
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clocks[1].phaseShift_deg = txPhC1[1] + txPhC2[1] * txInterfaceClk;
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else
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clocks[1].phaseShift_deg = txPhC1[0] + txPhC2[0] * txInterfaceClk;
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clocks[2].bypass = false;
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clocks[2].index = 2;
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clocks[2].outFrequency = rxInterfaceClk;
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clocks[2].phaseShift_deg = 0;
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clocks[2].findPhase = false;
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clocks[3].bypass = false;
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clocks[3].index = 3;
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clocks[3].outFrequency = rxInterfaceClk;
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clocks[3].findPhase = false;
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if (this->chipVersion == 0x3841)
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clocks[3].phaseShift_deg = rxPhC1[1] + rxPhC2[1] * rxInterfaceClk;
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else
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clocks[3].phaseShift_deg = rxPhC1[0] + rxPhC2[0] * rxInterfaceClk;
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if (phaseSearch)
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{
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{
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#ifndef NDEBUG
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printf("RX phase config:\n");
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#endif
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clocks[3].findPhase = true;
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const std::vector<uint32_t> spiData = { 0x0E9F, 0x07FF, 0x5550, 0xE4E4,
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0xE4E4, 0x0086, 0x028D, 0x00FF, 0x5555, 0x02CD, 0xAAAA, 0x02ED };
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//Load test config
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const int setRegCnt = spiData.size();
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for (int i = 0; i < setRegCnt; ++i)
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dataWr[i] = (1 << 31) | (uint32_t(spiAddr[i]) << 16) | spiData[i]; //msbit 1=SPI write
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TransactSPI(addrLMS7002M, dataWr.data(), nullptr, setRegCnt);
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status = lime::fpga::SetPllFrequency(this, 0, rxInterfaceClk, clocks, 4);
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}
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{
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#ifndef NDEBUG
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printf("TX phase config:\n");
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#endif
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clocks[3].findPhase = false;
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const std::vector<uint32_t> spiData = { 0x0E9F, 0x07FF, 0x5550, 0xE4E4, 0xE4E4, 0x0484 };
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WriteRegister(0x000A, 0x0000);
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//Load test config
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const int setRegCnt = spiData.size();
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for (int i = 0; i < setRegCnt; ++i)
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dataWr[i] = (1 << 31) | (uint32_t(spiAddr[i]) << 16) | spiData[i]; //msbit 1=SPI write
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TransactSPI(addrLMS7002M, dataWr.data(), nullptr, setRegCnt);
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clocks[1].findPhase = true;
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WriteRegister(0x000A, 0x0200);
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}
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}
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status = lime::fpga::SetPllFrequency(this, 0, rxInterfaceClk, clocks, 4);
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}
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else
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{
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status = lime::fpga::SetDirectClocking(this, 0, rxInterfaceClk, 90);
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if (status == 0)
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status = lime::fpga::SetDirectClocking(this, 1, rxInterfaceClk, 90);
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}
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if (phaseSearch)
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{
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//Restore registers
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for (int i = 0; i < bakRegCnt; ++i)
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dataWr[i] = (1 << 31) | (uint32_t(spiAddr[i]) << 16) | dataRd[i]; //msbit 1=SPI write
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TransactSPI(addrLMS7002M, dataWr.data(), nullptr, bakRegCnt);
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dataWr[0] = (1 << 31) | (uint32_t(0x0020) << 16) | reg20; //msbit 1=SPI write
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TransactSPI(addrLMS7002M, dataWr.data(), nullptr, 1);
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WriteRegister(0x000A, 0);
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UpdateThreads();
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}
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return status;
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}
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int Connection_uLimeSDR::ReadRawStreamData(char* buffer, unsigned length, int timeout_ms)
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{
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int totalBytesReceived = 0;
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fpga::StopStreaming(this);
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//ResetStreamBuffers();
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WriteRegister(0x0008, 0x0100 | 0x2);
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WriteRegister(0x0007, 1);
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fpga::StartStreaming(this);
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int handle = BeginDataReading(buffer, length);
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if (WaitForReading(handle, timeout_ms))
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totalBytesReceived = FinishDataReading(buffer, length, handle);
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AbortReading();
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fpga::StopStreaming(this);
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return totalBytesReceived;
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}
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int Connection_uLimeSDR::ResetStreamBuffers()
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{
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rxSize = 0;
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txSize = 0;
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#ifndef __unix__
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if (FT_AbortPipe(mFTHandle, mStreamRdEndPtAddr)!=FT_OK)
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return -1;
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if (FT_AbortPipe(mFTHandle, mStreamWrEndPtAddr)!=FT_OK)
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return -1;
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if (FT_FlushPipe(mFTHandle, mStreamRdEndPtAddr)!=FT_OK)
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return -1;
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#else
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return FT_FlushPipe(mStreamRdEndPtAddr);
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#endif
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return 0;
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}
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/** @brief Function dedicated for receiving data samples from board
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@param rxFIFO FIFO to store received data
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@param terminate periodically pooled flag to terminate thread
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@param dataRate_Bps (optional) if not NULL periodically returns data rate in bytes per second
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*/
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void Connection_uLimeSDR::ReceivePacketsLoop(const Connection_uLimeSDR::ThreadData args)
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{
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//auto dataPort = args.dataPort;
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auto terminate = args.terminate;
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auto dataRate_Bps = args.dataRate_Bps;
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auto generateData = args.generateData;
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auto safeToConfigInterface = args.safeToConfigInterface;
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//at this point FPGA has to be already configured to output samples
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const uint8_t chCount = args.channels.size();
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const auto link = args.channels[0]->config.linkFormat;
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const uint32_t samplesInPacket = (link == StreamConfig::STREAM_12_BIT_COMPRESSED ? 1360 : 1020)/chCount;
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double latency=0;
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for (int i = 0; i < chCount; i++)
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{
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latency += args.channels[i]->config.performanceLatency/chCount;
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}
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const unsigned tmp_cnt = (latency * 4)+0.5;
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const uint8_t packetsToBatch = (1<<tmp_cnt);
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const uint32_t bufferSize = packetsToBatch*sizeof(FPGA_DataPacket);
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const uint8_t buffersCount = 16; // must be power of 2
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vector<int> handles(buffersCount, 0);
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vector<char>buffers(buffersCount*bufferSize, 0);
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vector<StreamChannel::Frame> chFrames;
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try
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{
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chFrames.resize(chCount);
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}
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catch (const std::bad_alloc &ex)
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{
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ReportError("Error allocating Rx buffers, not enough memory");
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return;
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}
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uint8_t activeTransfers = 0;
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for (int i = 0; i<buffersCount; ++i)
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{
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handles[i] = this->BeginDataReading(&buffers[i*bufferSize], bufferSize);
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++activeTransfers;
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}
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int bi = 0;
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unsigned long totalBytesReceived = 0; //for data rate calculation
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int m_bufferFailures = 0;
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int32_t droppedSamples = 0;
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int32_t packetLoss = 0;
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vector<uint32_t> samplesCollected(chCount, 0);
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vector<uint32_t> samplesReceived(chCount, 0);
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auto t1 = chrono::high_resolution_clock::now();
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auto t2 = chrono::high_resolution_clock::now();
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std::mutex txFlagsLock;
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condition_variable resetTxFlags;
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//worker thread for reseting late Tx packet flags
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std::thread txReset([](ILimeSDRStreaming* port,
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atomic<bool> *terminate,
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mutex *spiLock,
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condition_variable *doWork)
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{
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uint32_t reg9;
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port->ReadRegister(0x0009, reg9);
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const uint32_t addr[] = {0x0009, 0x0009};
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const uint32_t data[] = {reg9 | (1 << 1), reg9 & ~(1 << 1)};
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while (not terminate->load())
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{
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std::unique_lock<std::mutex> lck(*spiLock);
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doWork->wait(lck);
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port->WriteRegisters(addr, data, 2);
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}
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}, this, terminate, &txFlagsLock, &resetTxFlags);
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int resetFlagsDelay = 128;
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uint64_t prevTs = 0;
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while (terminate->load() == false)
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{
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if(generateData->load())
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{
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if(activeTransfers == 0) //stop FPGA when last transfer completes
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fpga::StopStreaming(this);
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safeToConfigInterface->notify_all(); //notify that it's safe to change chip config
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const int batchSize = (this->mExpectedSampleRate/chFrames[0].samplesCount)/10;
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IStreamChannel::Metadata meta;
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for(int i=0; i<batchSize; ++i)
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{
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for(int ch=0; ch<chCount; ++ch)
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{
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meta.timestamp = chFrames[ch].timestamp;
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for(int j=0; j<chFrames[ch].samplesCount; ++j)
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{
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chFrames[ch].samples[j].i = 0;
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chFrames[ch].samples[j].q = 0;
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}
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uint32_t samplesPushed = args.channels[ch]->Write((const void*)chFrames[ch].samples, chFrames[ch].samplesCount, &meta);
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samplesReceived[ch] += chFrames[ch].samplesCount;
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if(samplesPushed != chFrames[ch].samplesCount)
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printf("Rx samples pushed %i/%i\n", samplesPushed, chFrames[ch].samplesCount);
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}
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}
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this_thread::sleep_for(chrono::milliseconds(100));
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}
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int32_t bytesReceived = 0;
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if(handles[bi] >= 0)
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{
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if (this->WaitForReading(handles[bi], 1000) == false)
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++m_bufferFailures;
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bytesReceived = this->FinishDataReading(&buffers[bi*bufferSize], bufferSize, handles[bi]);
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--activeTransfers;
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totalBytesReceived += bytesReceived;
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if (bytesReceived != int32_t(bufferSize)) //data should come in full sized packets
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++m_bufferFailures;
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}
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bool txLate=false;
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for (uint8_t pktIndex = 0; pktIndex < bytesReceived / sizeof(FPGA_DataPacket); ++pktIndex)
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{
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const FPGA_DataPacket* pkt = (FPGA_DataPacket*)&buffers[bi*bufferSize];
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const uint8_t byte0 = pkt[pktIndex].reserved[0];
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if ((byte0 & (1 << 3)) != 0 && !txLate) //report only once per batch
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{
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txLate = true;
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if(resetFlagsDelay > 0)
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--resetFlagsDelay;
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else
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{
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printf("L");
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resetTxFlags.notify_one();
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resetFlagsDelay = packetsToBatch*buffersCount;
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if (args.reportLateTx) args.reportLateTx(pkt[pktIndex].counter);
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}
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}
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uint8_t* pktStart = (uint8_t*)pkt[pktIndex].data;
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if(pkt[pktIndex].counter - prevTs != samplesInPacket && pkt[pktIndex].counter != prevTs)
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{
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#ifndef NDEBUG
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printf("\tRx pktLoss ts diff %lli\n", (long long)pkt[pktIndex].counter - prevTs);
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#endif
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packetLoss += (pkt[pktIndex].counter - prevTs)/samplesInPacket;
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}
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prevTs = pkt[pktIndex].counter;
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if(args.lastTimestamp)
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args.lastTimestamp->store(pkt[pktIndex].counter);
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//parse samples
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vector<complex16_t*> dest(chCount);
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for(uint8_t c=0; c<chCount; ++c)
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dest[c] = (chFrames[c].samples);
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size_t samplesCount = 0;
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fpga::FPGAPacketPayload2Samples(pktStart, 4080, chCount, link, dest.data(), &samplesCount);
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for(int ch=0; ch<chCount; ++ch)
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{
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IStreamChannel::Metadata meta;
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meta.timestamp = pkt[pktIndex].counter;
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meta.flags = RingFIFO::OVERWRITE_OLD;
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uint32_t samplesPushed = args.channels[ch]->Write((const void*)chFrames[ch].samples, samplesCount, &meta, 100);
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if(samplesPushed != samplesCount)
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droppedSamples += samplesCount-samplesPushed;
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}
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}
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// Re-submit this request to keep the queue full
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if(not generateData->load())
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{
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if(activeTransfers == 0) //reactivate FPGA and USB transfers
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fpga::StartStreaming(this);
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for(int i=0; i<buffersCount-activeTransfers; ++i)
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{
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handles[bi] = this->BeginDataReading(&buffers[bi*bufferSize], bufferSize);
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bi = (bi + 1) & (buffersCount-1);
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++activeTransfers;
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}
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}
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else
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{
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handles[bi] = -1;
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bi = (bi + 1) & (buffersCount-1);
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}
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t2 = chrono::high_resolution_clock::now();
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auto timePeriod = std::chrono::duration_cast<std::chrono::milliseconds>(t2 - t1).count();
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if (timePeriod >= 1000)
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{
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t1 = t2;
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//total number of bytes sent per second
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double dataRate = 1000.0*totalBytesReceived / timePeriod;
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#ifndef NDEBUG
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//each channel sample rate
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float samplingRate = 1000.0*samplesReceived[0] / timePeriod;
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printf("Rx: %.3f MB/s, Fs: %.3f MHz, overrun: %i, loss: %i \n", dataRate / 1000000.0, samplingRate / 1000000.0, droppedSamples, packetLoss);
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#endif
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samplesReceived[0] = 0;
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totalBytesReceived = 0;
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m_bufferFailures = 0;
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droppedSamples = 0;
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packetLoss = 0;
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if (dataRate_Bps)
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dataRate_Bps->store((uint32_t)dataRate);
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}
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}
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this->AbortReading();
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for (int j = 0; j<buffersCount; j++)
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{
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if(handles[bi] >= 0)
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{
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this->WaitForReading(handles[bi], 1000);
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this->FinishDataReading(&buffers[bi*bufferSize], bufferSize, handles[bi]);
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}
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bi = (bi + 1) & (buffersCount-1);
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}
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resetTxFlags.notify_one();
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txReset.join();
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if (dataRate_Bps)
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dataRate_Bps->store(0);
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}
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/** @brief Functions dedicated for transmitting packets to board
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@param txFIFO data source FIFO
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@param terminate periodically pooled flag to terminate thread
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@param dataRate_Bps (optional) if not NULL periodically returns data rate in bytes per second
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*/
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void Connection_uLimeSDR::TransmitPacketsLoop(const Connection_uLimeSDR::ThreadData args)
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{
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//auto dataPort = args.dataPort;
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auto terminate = args.terminate;
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auto dataRate_Bps = args.dataRate_Bps;
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//at this point FPGA has to be already configured to output samples
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const uint8_t maxChannelCount = 2;
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const uint8_t chCount = args.channels.size();
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const auto link = args.channels[0]->config.linkFormat;
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double latency=0;
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for (int i = 0; i < chCount; i++)
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{
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latency += args.channels[i]->config.performanceLatency/chCount;
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}
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const unsigned tmp_cnt = (latency * 4)+0.5;
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const uint8_t buffersCount = 16; // must be power of 2
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assert(buffersCount % 2 == 0);
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const uint8_t packetsToBatch = (1<<tmp_cnt); //packets in single USB transfer
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const uint32_t bufferSize = packetsToBatch*4096;
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const uint32_t popTimeout_ms = 100;
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const int maxSamplesBatch = (link==StreamConfig::STREAM_12_BIT_COMPRESSED?1360:1020)/chCount;
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vector<int> handles(buffersCount, 0);
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vector<bool> bufferUsed(buffersCount, 0);
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vector<uint32_t> bytesToSend(buffersCount, 0);
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vector<complex16_t> samples[maxChannelCount];
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vector<char> buffers;
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try
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{
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for(int i=0; i<chCount; ++i)
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samples[i].resize(maxSamplesBatch);
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buffers.resize(buffersCount*bufferSize, 0);
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}
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catch (const std::bad_alloc& ex) //not enough memory for buffers
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{
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printf("Error allocating Tx buffers, not enough memory\n");
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return;
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}
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int m_bufferFailures = 0;
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long totalBytesSent = 0;
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uint32_t samplesSent = 0;
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auto t1 = chrono::high_resolution_clock::now();
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auto t2 = chrono::high_resolution_clock::now();
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uint8_t bi = 0; //buffer index
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while (terminate->load() != true)
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{
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if (bufferUsed[bi])
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{
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if (this->WaitForSending(handles[bi], 1000) == false)
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++m_bufferFailures;
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uint32_t bytesSent = this->FinishDataSending(&buffers[bi*bufferSize], bytesToSend[bi], handles[bi]);
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totalBytesSent += bytesSent;
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if (bytesSent != bytesToSend[bi])
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++m_bufferFailures;
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bufferUsed[bi] = false;
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}
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int i=0;
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while(i<packetsToBatch && terminate->load() != true)
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{
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IStreamChannel::Metadata meta;
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FPGA_DataPacket* pkt = reinterpret_cast<FPGA_DataPacket*>(&buffers[bi*bufferSize]);
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for(int ch=0; ch<chCount; ++ch)
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{
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int samplesPopped = args.channels[ch]->Read(samples[ch].data(), maxSamplesBatch, &meta, popTimeout_ms);
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if (samplesPopped != maxSamplesBatch)
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{
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#ifndef NDEBUG
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printf("Warning popping from TX, samples popped %i/%i\n", samplesPopped, maxSamplesBatch);
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#endif
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}
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}
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if(terminate->load() == true) //early termination
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break;
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pkt[i].counter = meta.timestamp;
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pkt[i].reserved[0] = 0;
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//by default ignore timestamps
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const int ignoreTimestamp = !(meta.flags & IStreamChannel::Metadata::SYNC_TIMESTAMP);
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pkt[i].reserved[0] |= ((int)ignoreTimestamp << 4); //ignore timestamp
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vector<complex16_t*> src(chCount);
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for(uint8_t c=0; c<chCount; ++c)
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src[c] = (samples[c].data());
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uint8_t* const dataStart = (uint8_t*)pkt[i].data;
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fpga::Samples2FPGAPacketPayload(src.data(), maxSamplesBatch, chCount, link, dataStart, nullptr);
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samplesSent += maxSamplesBatch;
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++i;
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}
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bytesToSend[bi] = bufferSize;
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handles[bi] = this->BeginDataSending(&buffers[bi*bufferSize], bytesToSend[bi]);
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bufferUsed[bi] = true;
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t2 = chrono::high_resolution_clock::now();
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auto timePeriod = std::chrono::duration_cast<std::chrono::milliseconds>(t2 - t1).count();
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if (timePeriod >= 1000)
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{
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//total number of bytes sent per second
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float dataRate = 1000.0*totalBytesSent / timePeriod;
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if(dataRate_Bps)
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dataRate_Bps->store(dataRate);
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m_bufferFailures = 0;
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samplesSent = 0;
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totalBytesSent = 0;
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t1 = t2;
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#ifndef NDEBUG
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//total number of samples from all channels per second
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float sampleRate = 1000.0*samplesSent / timePeriod;
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printf("Tx: %.3f MB/s, Fs: %.3f MHz, failures: %i\n", dataRate / 1000000.0, sampleRate / 1000000.0, m_bufferFailures);
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#endif
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}
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bi = (bi + 1) & (buffersCount-1);
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}
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// Wait for all the queued requests to be cancelled
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this->AbortSending();
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for (int j = 0; j<buffersCount; j++)
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{
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if (bufferUsed[bi])
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{
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this->WaitForSending(handles[bi], 1000);
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this->FinishDataSending(&buffers[bi*bufferSize], bufferSize, handles[bi]);
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}
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bi = (bi + 1) & (buffersCount-1);
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}
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if (dataRate_Bps)
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dataRate_Bps->store(0);
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}
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