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VE7UWU
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sdrangel
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7ae5c2a6d6
sdrangel
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plugins
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f4exb
7ae5c2a6d6
UDP source: save channel marker center frequency in only one slot
2017-08-26 15:13:03 +02:00
..
channelrx
UDP source: save channel marker center frequency in only one slot
2017-08-26 15:13:03 +02:00
channeltx
UDP sink: fixed input power display placement
2017-08-26 06:10:16 +02:00
samplesink
SDRDaemonSink: fixed compile warning in debug mode
2017-08-19 00:12:28 +02:00
samplesource
LimeSDR: fixed issue
#50
by moving channel acquisition and release at start and stop times. Corrections to buddies thread suspend/resume. Corrected void channel handling
2017-08-14 03:32:51 +02:00
CMakeLists.txt
Tx ph.1: new AM modulator plugin (2). Compiles but pull method is still empty
2016-10-20 18:04:15 +02:00