mirror of https://github.com/f4exb/sdrangel.git
542 lines
20 KiB
C++
542 lines
20 KiB
C++
/**
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@file ConnectionSTREAMing.cpp
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@author Lime Microsystems
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@brief Implementation of STREAM board connection (streaming API)
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*/
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#include "ConnectionSTREAM.h"
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#include "fifo.h"
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#include <LMS7002M.h>
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#include <iostream>
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#include <thread>
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#include <chrono>
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#include <algorithm>
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#include <complex>
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#include <ciso646>
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#include <FPGA_common.h>
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#include "ErrorReporting.h"
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#include "Logger.h"
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using namespace lime;
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using namespace std;
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/** @brief Configures FPGA PLLs to LimeLight interface frequency
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*/
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int ConnectionSTREAM::UpdateExternalDataRate(const size_t channel, const double txRate_Hz, const double rxRate_Hz, const double txPhase, const double rxPhase)
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{
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lime::fpga::FPGA_PLL_clock clocks[2];
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if (channel == 2)
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{
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clocks[0].index = 0;
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clocks[0].outFrequency = rxRate_Hz;
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clocks[1].index = 1;
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clocks[1].outFrequency = txRate_Hz;
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return lime::fpga::SetPllFrequency(this, 4, 30.72e6, clocks, 2);
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}
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const float txInterfaceClk = 2 * txRate_Hz;
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const float rxInterfaceClk = 2 * rxRate_Hz;
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mExpectedSampleRate = rxRate_Hz;
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const int pll_ind = (channel == 1) ? 2 : 0;
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clocks[0].index = 0;
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clocks[0].outFrequency = rxInterfaceClk;
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clocks[1].index = 1;
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clocks[1].outFrequency = rxInterfaceClk;
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clocks[1].phaseShift_deg = rxPhase;
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if (lime::fpga::SetPllFrequency(this, pll_ind+1, rxInterfaceClk, clocks, 2)!=0)
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return -1;
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clocks[0].index = 0;
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clocks[0].outFrequency = txInterfaceClk;
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clocks[1].index = 1;
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clocks[1].outFrequency = txInterfaceClk;
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clocks[1].phaseShift_deg = txPhase;
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if (lime::fpga::SetPllFrequency(this, pll_ind, txInterfaceClk, clocks, 2)!=0)
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return -1;
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return 0;
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}
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/** @brief Configures FPGA PLLs to LimeLight interface frequency
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*/
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int ConnectionSTREAM::UpdateExternalDataRate(const size_t channel, const double txRate_Hz, const double rxRate_Hz)
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{
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const float txInterfaceClk = 2 * txRate_Hz;
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const float rxInterfaceClk = 2 * rxRate_Hz;
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const int pll_ind = (channel == 1) ? 2 : 0;
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int status = 0;
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uint32_t reg20;
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const double rxPhC1[] = { 91.08, 89.46 };
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const double rxPhC2[] = { -1 / 6e6, 1.24e-6 };
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const double txPhC1[] = { 89.75, 89.61 };
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const double txPhC2[] = { -3.0e-7, 2.71e-7 };
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const std::vector<uint32_t> spiAddr = { 0x021, 0x022, 0x023, 0x024, 0x027, 0x02A,
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0x400, 0x40C, 0x40B, 0x400, 0x40B, 0x400};
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const int bakRegCnt = spiAddr.size() - 4;
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auto info = GetDeviceInfo();
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bool phaseSearch = false;
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if (!(mStreamers.size() > channel && (mStreamers[channel]->rxRunning || mStreamers[channel]->txRunning)))
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if (this->chipVersion == 0x3841 && stoi(info.gatewareRevision) >= 7 && stoi(info.gatewareVersion) >= 2) //0x3840 LMS7002Mr2, 0x3841 LMS7002Mr3
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if(rxInterfaceClk >= 5e6 || txInterfaceClk >= 5e6)
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phaseSearch = true;
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mExpectedSampleRate = rxRate_Hz;
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std::vector<uint32_t> dataWr;
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std::vector<uint32_t> dataRd;
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if (phaseSearch)
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{
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dataWr.resize(spiAddr.size());
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dataRd.resize(spiAddr.size());
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//backup registers
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dataWr[0] = (uint32_t(0x0020) << 16);
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ReadLMS7002MSPI(dataWr.data(), ®20, 1, channel);
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dataWr[0] = (1 << 31) | (uint32_t(0x0020) << 16) | 0xFFFD; //msbit 1=SPI write
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WriteLMS7002MSPI(dataWr.data(), 1, channel);
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for (int i = 0; i < bakRegCnt; ++i)
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dataWr[i] = (spiAddr[i] << 16);
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ReadLMS7002MSPI(dataWr.data(),dataRd.data(), bakRegCnt, channel);
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}
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if(rxInterfaceClk >= 5e6)
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{
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if (phaseSearch)
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{
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const std::vector<uint32_t> spiData = { 0x0E9F, 0x07FF, 0x5550, 0xE4E4, 0xE4E4, 0x0086,
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0x028D, 0x00FF, 0x5555, 0x02CD, 0xAAAA, 0x02ED};
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//Load test config
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const int setRegCnt = spiData.size();
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for (int i = 0; i < setRegCnt; ++i)
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dataWr[i] = (1 << 31) | (uint32_t(spiAddr[i]) << 16) | spiData[i]; //msbit 1=SPI write
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WriteLMS7002MSPI(dataWr.data(), setRegCnt, channel);
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}
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lime::fpga::FPGA_PLL_clock clocks[2];
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clocks[0].index = 0;
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clocks[0].outFrequency = rxInterfaceClk;
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clocks[1].index = 1;
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clocks[1].outFrequency = rxInterfaceClk;
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if (this->chipVersion == 0x3841)
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clocks[1].phaseShift_deg = rxPhC1[1] + rxPhC2[1] * rxInterfaceClk;
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else
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clocks[1].phaseShift_deg = rxPhC1[0] + rxPhC2[0] * rxInterfaceClk;
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if (phaseSearch)
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clocks[1].findPhase = true;
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status = lime::fpga::SetPllFrequency(this, pll_ind+1, rxInterfaceClk, clocks, 2);
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}
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else
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status = lime::fpga::SetDirectClocking(this, pll_ind+1, rxInterfaceClk, 90);
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if(txInterfaceClk >= 5e6)
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{
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if (phaseSearch)
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{
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const std::vector<uint32_t> spiData = {0x0E9F, 0x07FF, 0x5550, 0xE4E4, 0xE4E4, 0x0484};
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WriteRegister(0x000A, 0x0000);
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//Load test config
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const int setRegCnt = spiData.size();
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for (int i = 0; i < setRegCnt; ++i)
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dataWr[i] = (1 << 31) | (uint32_t(spiAddr[i]) << 16) | spiData[i]; //msbit 1=SPI write
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WriteLMS7002MSPI(dataWr.data(), setRegCnt, channel);
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}
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lime::fpga::FPGA_PLL_clock clocks[2];
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clocks[0].index = 0;
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clocks[0].outFrequency = txInterfaceClk;
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clocks[0].phaseShift_deg = 0;
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clocks[1].index = 1;
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clocks[1].outFrequency = txInterfaceClk;
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if (this->chipVersion == 0x3841)
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clocks[1].phaseShift_deg = txPhC1[1] + txPhC2[1] * txInterfaceClk;
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else
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clocks[1].phaseShift_deg = txPhC1[0] + txPhC2[0] * txInterfaceClk;
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if (phaseSearch)
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{
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clocks[1].findPhase = true;
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WriteRegister(0x000A, 0x0200);
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}
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status = lime::fpga::SetPllFrequency(this, pll_ind, txInterfaceClk, clocks, 2);
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}
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else
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status = lime::fpga::SetDirectClocking(this, pll_ind, txInterfaceClk, 90);
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if (phaseSearch)
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{
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//Restore registers
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for (int i = 0; i < bakRegCnt; ++i)
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dataWr[i] = (1 << 31) | (uint32_t(spiAddr[i]) << 16) | dataRd[i]; //msbit 1=SPI write
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WriteLMS7002MSPI(dataWr.data(), bakRegCnt, channel);
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dataWr[0] = (1 << 31) | (uint32_t(0x0020) << 16) | reg20; //msbit 1=SPI write
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WriteLMS7002MSPI(dataWr.data(), 1, channel);
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WriteRegister(0x000A, 0);
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}
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return status;
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}
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int ConnectionSTREAM::ResetStreamBuffers()
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{
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//USB FIFO reset
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LMS64CProtocol::GenericPacket ctrPkt;
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ctrPkt.cmd = CMD_USB_FIFO_RST;
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ctrPkt.outBuffer.push_back(0x00);
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return TransferPacket(ctrPkt);
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}
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int ConnectionSTREAM::ReadRawStreamData(char* buffer, unsigned length, int epIndex, int timeout_ms)
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{
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const unsigned char ep = 0x81;
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fpga::StopStreaming(this, epIndex);
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ResetStreamBuffers();
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WriteRegister(0x0008, 0x0100 | 0x2);
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WriteRegister(0x0007, 1);
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fpga::StartStreaming(this, epIndex);
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int totalBytesReceived = ReceiveData(buffer,length, epIndex, timeout_ms);
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fpga::StopStreaming(this, epIndex);
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AbortReading(ep);
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return totalBytesReceived;
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}
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/** @brief Function dedicated for receiving data samples from board
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@param stream a pointer to an active receiver stream
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*/
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void ConnectionSTREAM::ReceivePacketsLoop(Streamer* stream)
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{
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//at this point FPGA has to be already configured to output samples
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const uint8_t chCount = stream->mRxStreams.size();
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const auto link = stream->mRxStreams[0]->config.linkFormat;
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const uint32_t samplesInPacket = (link == StreamConfig::STREAM_12_BIT_COMPRESSED ? 1360 : 1020)/chCount;
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const unsigned char ep = 0x81;
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const int chipID = stream->mChipID;
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float latency=0;
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for (int i = 0; i < chCount; i++)
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latency += stream->mRxStreams[i]->config.performanceLatency/chCount;
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const unsigned tmp_cnt = (latency * 6)+0.5;
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const uint8_t packetsToBatch = (1<<tmp_cnt);
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const uint32_t bufferSize = packetsToBatch*sizeof(FPGA_DataPacket);
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const uint8_t buffersCount = 16;
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vector<int> handles(buffersCount, 0);
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vector<char>buffers(buffersCount*bufferSize, 0);
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vector<StreamChannel::Frame> chFrames;
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try
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{
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chFrames.resize(chCount);
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}
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catch (const std::bad_alloc &ex)
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{
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ReportError("Error allocating Rx buffers, not enough memory");
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return;
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}
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int activeTransfers = 0;
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for (int i = 0; i<buffersCount; ++i)
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{
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handles[i] = this->BeginDataReading(&buffers[i*bufferSize], bufferSize, ep);
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++activeTransfers;
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}
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int bi = 0;
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unsigned long totalBytesReceived = 0; //for data rate calculation
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auto t1 = chrono::high_resolution_clock::now();
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auto t2 = t1;
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std::mutex txFlagsLock;
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condition_variable resetTxFlags;
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//worker thread for reseting late Tx packet flags
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std::thread txReset([](ILimeSDRStreaming* port,
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atomic<bool> *terminate,
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mutex *spiLock,
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condition_variable *doWork)
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{
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uint32_t reg9;
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port->ReadRegister(0x0009, reg9);
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const uint32_t addr[] = {0x0009, 0x0009};
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const uint32_t data[] = {reg9 | (5 << 1), reg9 & ~(5 << 1)};
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while (not terminate->load())
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{
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std::unique_lock<std::mutex> lck(*spiLock);
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doWork->wait(lck);
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port->WriteRegisters(addr, data, 2);
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}
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}, this, &stream->terminateRx, &txFlagsLock, &resetTxFlags);
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int resetFlagsDelay = 128;
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uint64_t prevTs = 0;
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while (stream->terminateRx.load() == false)
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{
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if(stream->generateData.load())
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{
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if(activeTransfers == 0) //stop FPGA when last transfer completes
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fpga::StopStreaming(this, chipID);
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stream->safeToConfigInterface.notify_all(); //notify that it's safe to change chip config
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const int batchSize = (this->mExpectedSampleRate/chFrames[0].samplesCount)/10;
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IStreamChannel::Metadata meta;
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for(int i=0; i<batchSize; ++i)
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{
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for(int ch=0; ch<chCount; ++ch)
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{
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meta.timestamp = chFrames[ch].timestamp;
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for(int j=0; j<chFrames[ch].samplesCount; ++j)
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{
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chFrames[ch].samples[j].i = 0;
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chFrames[ch].samples[j].q = 0;
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}
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uint32_t samplesPushed = stream->mRxStreams[ch]->Write((const void*)chFrames[ch].samples, chFrames[ch].samplesCount, &meta);
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if(samplesPushed != chFrames[ch].samplesCount)
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lime::warning("Rx samples pushed %i/%i", samplesPushed, chFrames[ch].samplesCount);
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}
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}
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this_thread::sleep_for(chrono::milliseconds(100));
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}
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int32_t bytesReceived = 0;
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if(handles[bi] >= 0)
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{
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if (this->WaitForReading(handles[bi], 1000) == true)
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bytesReceived = this->FinishDataReading(&buffers[bi*bufferSize], bufferSize, handles[bi]);
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--activeTransfers;
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totalBytesReceived += bytesReceived;
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if (bytesReceived != int32_t(bufferSize)) //data should come in full sized packets
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for(auto value: stream->mRxStreams)
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value->underflow++;
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}
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bool txLate=false;
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for (uint8_t pktIndex = 0; pktIndex < bytesReceived / sizeof(FPGA_DataPacket); ++pktIndex)
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{
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const FPGA_DataPacket* pkt = (FPGA_DataPacket*)&buffers[bi*bufferSize];
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const uint8_t byte0 = pkt[pktIndex].reserved[0];
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if ((byte0 & (1 << 3)) != 0 && !txLate) //report only once per batch
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{
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txLate = true;
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if(resetFlagsDelay > 0)
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--resetFlagsDelay;
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else
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{
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lime::info("L %llu", (unsigned long long)pkt[pktIndex].counter);
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resetTxFlags.notify_one();
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resetFlagsDelay = packetsToBatch*buffersCount;
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stream->txLastLateTime.store(pkt[pktIndex].counter);
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for(auto value: stream->mTxStreams)
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value->pktLost++;
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}
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}
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uint8_t* pktStart = (uint8_t*)pkt[pktIndex].data;
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if(pkt[pktIndex].counter - prevTs != samplesInPacket && pkt[pktIndex].counter != prevTs)
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{
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int packetLoss = ((pkt[pktIndex].counter - prevTs)/samplesInPacket)-1;
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#ifndef NDEBUG
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printf("\tRx pktLoss: ts diff: %li pktLoss: %i\n", pkt[pktIndex].counter - prevTs, packetLoss);
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#endif
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for(auto value: stream->mRxStreams)
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value->pktLost += packetLoss;
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}
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prevTs = pkt[pktIndex].counter;
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stream->rxLastTimestamp.store(prevTs);
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//parse samples
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vector<complex16_t*> dest(chCount);
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for(uint8_t c=0; c<chCount; ++c)
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dest[c] = (chFrames[c].samples);
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size_t samplesCount = 0;
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fpga::FPGAPacketPayload2Samples(pktStart, 4080, chCount, link, dest.data(), &samplesCount);
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for(int ch=0; ch<chCount; ++ch)
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{
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IStreamChannel::Metadata meta;
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meta.timestamp = pkt[pktIndex].counter;
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meta.flags = RingFIFO::OVERWRITE_OLD;
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uint32_t samplesPushed = stream->mRxStreams[ch]->Write((const void*)chFrames[ch].samples, samplesCount, &meta, 100);
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if(samplesPushed != samplesCount)
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stream->mRxStreams[ch]->overflow++;
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}
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}
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// Re-submit this request to keep the queue full
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if(not stream->generateData.load())
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{
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if(activeTransfers == 0) //reactivate FPGA and USB transfers
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fpga::StartStreaming(this, chipID);
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for(int i=0; i<buffersCount-activeTransfers; ++i)
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{
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handles[bi] = this->BeginDataReading(&buffers[bi*bufferSize], bufferSize, ep);
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bi = (bi + 1) & (buffersCount-1);
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++activeTransfers;
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}
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}
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else
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{
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handles[bi] = -1;
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bi = (bi + 1) & (buffersCount-1);
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}
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t2 = chrono::high_resolution_clock::now();
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auto timePeriod = std::chrono::duration_cast<std::chrono::milliseconds>(t2 - t1).count();
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if (timePeriod >= 1000)
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{
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t1 = t2;
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//total number of bytes sent per second
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double dataRate = 1000.0*totalBytesReceived / timePeriod;
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#ifndef NDEBUG
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printf("Rx: %.3f MB/s\n", dataRate / 1000000.0);
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#endif
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totalBytesReceived = 0;
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stream->rxDataRate_Bps.store((uint32_t)dataRate);
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}
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}
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AbortReading(ep);
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for (int j = 0; j<buffersCount; j++)
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{
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if(handles[bi] >= 0)
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{
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this->WaitForReading(handles[bi], 1000);
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this->FinishDataReading(&buffers[bi*bufferSize], bufferSize, handles[bi]);
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}
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bi = (bi + 1) & (buffersCount-1);
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}
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resetTxFlags.notify_one();
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txReset.join();
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stream->rxDataRate_Bps.store(0);
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}
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/** @brief Functions dedicated for transmitting packets to board
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@param stream an active transmit stream
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*/
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void ConnectionSTREAM::TransmitPacketsLoop(Streamer* stream)
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{
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//at this point FPGA has to be already configured to output samples
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const uint8_t maxChannelCount = 2;
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const uint8_t chCount = stream->mTxStreams.size();
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const auto link = stream->mTxStreams[0]->config.linkFormat;
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const unsigned char ep = 0x01;
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double latency=0;
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for (int i = 0; i < chCount; i++)
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latency += stream->mTxStreams[i]->config.performanceLatency/chCount;
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const unsigned tmp_cnt = (latency * 6)+0.5;
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const uint8_t buffersCount = 16; // must be power of 2
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const uint8_t packetsToBatch = (1<<tmp_cnt); //packets in single USB transfer
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const uint32_t bufferSize = packetsToBatch*4096;
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const uint32_t popTimeout_ms = 100;
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const int maxSamplesBatch = (link==StreamConfig::STREAM_12_BIT_COMPRESSED?1360:1020)/chCount;
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vector<int> handles(buffersCount, 0);
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vector<bool> bufferUsed(buffersCount, 0);
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vector<complex16_t> samples[maxChannelCount];
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vector<char> buffers;
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try
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{
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for(int i=0; i<chCount; ++i)
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samples[i].resize(maxSamplesBatch);
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buffers.resize(buffersCount*bufferSize, 0);
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}
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catch (const std::bad_alloc& ex) //not enough memory for buffers
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{
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return lime::error("Error allocating Tx buffers, not enough memory");
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}
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|
|
|
long totalBytesSent = 0;
|
|
auto t1 = chrono::high_resolution_clock::now();
|
|
auto t2 = t1;
|
|
|
|
uint8_t bi = 0; //buffer index
|
|
while (stream->terminateTx.load() != true)
|
|
{
|
|
if (bufferUsed[bi])
|
|
{
|
|
unsigned bytesSent = 0;
|
|
if (this->WaitForSending(handles[bi], 1000) == true) {
|
|
bytesSent = this->FinishDataSending(&buffers[bi*bufferSize], bufferSize, handles[bi]);
|
|
}
|
|
|
|
if (bytesSent != bufferSize) {
|
|
for (auto value : stream->mTxStreams) {
|
|
value->overflow++;
|
|
}
|
|
}
|
|
else {
|
|
totalBytesSent += bytesSent;
|
|
}
|
|
bufferUsed[bi] = false;
|
|
}
|
|
int i=0;
|
|
|
|
while(i<packetsToBatch && stream->terminateTx.load() != true)
|
|
{
|
|
IStreamChannel::Metadata meta;
|
|
FPGA_DataPacket* pkt = reinterpret_cast<FPGA_DataPacket*>(&buffers[bi*bufferSize]);
|
|
bool badSamples = false;
|
|
for(int ch=0; ch<chCount; ++ch)
|
|
{
|
|
int samplesPopped = stream->mTxStreams[ch]->Read(samples[ch].data(), maxSamplesBatch, &meta, popTimeout_ms);
|
|
if (samplesPopped != maxSamplesBatch)
|
|
{
|
|
badSamples = true;
|
|
stream->mTxStreams[ch]->underflow++;
|
|
stream->txDataRate_Bps.store(0);
|
|
#ifndef NDEBUG
|
|
printf("popping from TX, samples popped %i/%i\n", samplesPopped, maxSamplesBatch);
|
|
#endif
|
|
break;
|
|
}
|
|
}
|
|
if (badSamples)
|
|
continue;
|
|
if(stream->terminateTx.load() == true) //early termination
|
|
break;
|
|
pkt[i].counter = meta.timestamp;
|
|
pkt[i].reserved[0] = 0;
|
|
//by default ignore timestamps
|
|
const int ignoreTimestamp = !(meta.flags & IStreamChannel::Metadata::SYNC_TIMESTAMP);
|
|
pkt[i].reserved[0] |= ((int)ignoreTimestamp << 4); //ignore timestamp
|
|
|
|
vector<complex16_t*> src(chCount);
|
|
for(uint8_t c=0; c<chCount; ++c)
|
|
src[c] = (samples[c].data());
|
|
uint8_t* const dataStart = (uint8_t*)pkt[i].data;
|
|
fpga::Samples2FPGAPacketPayload(src.data(), maxSamplesBatch, chCount, link, dataStart, nullptr);
|
|
++i;
|
|
}
|
|
|
|
handles[bi] = this->BeginDataSending(&buffers[bi*bufferSize], bufferSize, ep);
|
|
bufferUsed[bi] = true;
|
|
|
|
t2 = chrono::high_resolution_clock::now();
|
|
auto timePeriod = std::chrono::duration_cast<std::chrono::milliseconds>(t2 - t1).count();
|
|
if (timePeriod >= 1000)
|
|
{
|
|
//total number of bytes sent per second
|
|
float dataRate = 1000.0*totalBytesSent / timePeriod;
|
|
stream->txDataRate_Bps.store(dataRate);
|
|
totalBytesSent = 0;
|
|
t1 = t2;
|
|
#ifndef NDEBUG
|
|
printf("Tx: %.3f MB/s\n", dataRate / 1000000.0);
|
|
#endif
|
|
}
|
|
bi = (bi + 1) & (buffersCount-1);
|
|
}
|
|
|
|
// Wait for all the queued requests to be cancelled
|
|
AbortSending(ep);
|
|
for (int j = 0; j<buffersCount; j++)
|
|
{
|
|
if (bufferUsed[bi])
|
|
{
|
|
this->WaitForSending(handles[bi], 1000);
|
|
this->FinishDataSending(&buffers[bi*bufferSize], bufferSize, handles[bi]);
|
|
}
|
|
bi = (bi + 1) & (buffersCount-1);
|
|
}
|
|
stream->txDataRate_Bps.store(0);
|
|
}
|
|
|