android_kernel_xiaomi_sm8350/arch/csky/abiv1/inc/abi/pgtable-bits.h

/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.

#ifndef __ASM_CSKY_PGTABLE_BITS_H
#define __ASM_CSKY_PGTABLE_BITS_H

/* implemented in software */
#define _PAGE_ACCESSED		(1<<3)
#define PAGE_ACCESSED_BIT	(3)

#define _PAGE_READ		(1<<1)
#define _PAGE_WRITE		(1<<2)
#define _PAGE_PRESENT		(1<<0)

#define _PAGE_MODIFIED		(1<<4)
#define PAGE_MODIFIED_BIT	(4)

/* implemented in hardware */
#define _PAGE_GLOBAL		(1<<6)

#define _PAGE_VALID		(1<<7)
#define PAGE_VALID_BIT		(7)

#define _PAGE_DIRTY		(1<<8)
#define PAGE_DIRTY_BIT		(8)

#define _PAGE_CACHE		(3<<9)
#define _PAGE_UNCACHE		(2<<9)
#define _PAGE_SO		_PAGE_UNCACHE

#define _CACHE_MASK		(7<<9)

#define _CACHE_CACHED		(_PAGE_VALID | _PAGE_CACHE)
#define _CACHE_UNCACHED		(_PAGE_VALID | _PAGE_UNCACHE)

#define HAVE_ARCH_UNMAPPED_AREA

#endif /* __ASM_CSKY_PGTABLE_BITS_H */
csky: MMU and page table management This patch adds files related to memory management and here is our memory-layout: Fixmap : 0xffc02000 – 0xfffff000 (4 MB - 12KB) Pkmap : 0xff800000 – 0xffc00000 (4 MB) Vmalloc : 0xf0200000 – 0xff000000 (238 MB) Lowmem : 0x80000000 – 0xc0000000 (1GB) abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem. abiv2 CPUs are all PIPT cache and they could support highmem. Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup memory page table for it. Link:https://lore.kernel.org/lkml/20180518215548.GH17671@n2100.armlinux.org.uk/ Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> 2018-09-05 02:25:12 -04:00			`/* SPDX-License-Identifier: GPL-2.0 */`
			`// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.`

			`#ifndef __ASM_CSKY_PGTABLE_BITS_H`
			`#define __ASM_CSKY_PGTABLE_BITS_H`

			`/* implemented in software */`
			`#define _PAGE_ACCESSED (1<<3)`
			`#define PAGE_ACCESSED_BIT (3)`

			`#define _PAGE_READ (1<<1)`
			`#define _PAGE_WRITE (1<<2)`
			`#define _PAGE_PRESENT (1<<0)`

			`#define _PAGE_MODIFIED (1<<4)`
			`#define PAGE_MODIFIED_BIT (4)`

			`/* implemented in hardware */`
			`#define _PAGE_GLOBAL (1<<6)`

			`#define _PAGE_VALID (1<<7)`
			`#define PAGE_VALID_BIT (7)`

			`#define _PAGE_DIRTY (1<<8)`
			`#define PAGE_DIRTY_BIT (8)`

			`#define _PAGE_CACHE (3<<9)`
			`#define _PAGE_UNCACHE (2<<9)`
csky: fixup abiv2 mmap(... O_SYNC) failed. Glibc function mmap(... O_SYNC) will make page to _PAGE_UNCACHE + _PAGE_SO and strong-order page couldn't support unalignment access. So remove _PAGE_SO from _PAGE_UNCACHE, also sync abiv1 with the macro of _PAGE_SO. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reported-by: Liu Renwei <Renwei.Liu@verisilicon.com> Tested-by: Yuan Qiyun <qiyun_yuan@c-sky.com> 2018-12-30 08:47:28 -05:00			`#define _PAGE_SO _PAGE_UNCACHE`
csky: MMU and page table management This patch adds files related to memory management and here is our memory-layout: Fixmap : 0xffc02000 – 0xfffff000 (4 MB - 12KB) Pkmap : 0xff800000 – 0xffc00000 (4 MB) Vmalloc : 0xf0200000 – 0xff000000 (238 MB) Lowmem : 0x80000000 – 0xc0000000 (1GB) abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem. abiv2 CPUs are all PIPT cache and they could support highmem. Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup memory page table for it. Link:https://lore.kernel.org/lkml/20180518215548.GH17671@n2100.armlinux.org.uk/ Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> 2018-09-05 02:25:12 -04:00
			`#define _CACHE_MASK (7<<9)`

			`#define _CACHE_CACHED (_PAGE_VALID \| _PAGE_CACHE)`
			`#define _CACHE_UNCACHED (_PAGE_VALID \| _PAGE_UNCACHE)`

			`#define HAVE_ARCH_UNMAPPED_AREA`

			`#endif /* __ASM_CSKY_PGTABLE_BITS_H */`