334 lines
8.9 KiB
C
334 lines
8.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, Linux Foundation. All rights reserved.
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*/
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#include "phy-qcom-ufs-qmp-v4.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_v4"
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#define check_v1(major, minor, step) \
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((major == 0x4) && (minor == 0x000) && (step == 0x0000))
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#define check_v2(major, minor, step) \
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((major == 0x4) && (minor == 0x001) && (step == 0x0000))
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static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy);
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static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common);
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static
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int ufs_qcom_phy_qmp_v4_phy_calibrate(struct phy *generic_phy)
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{
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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struct device *dev = ufs_qcom_phy->dev;
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bool is_g4, is_rate_B;
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int err;
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u8 major = ufs_qcom_phy->host_ctrl_rev_major;
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u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
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u16 step = ufs_qcom_phy->host_ctrl_rev_step;
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err = reset_control_assert(ufs_qcom_phy->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to assert UFS PHY reset %d\n", err);
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goto out;
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}
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/* For UFS PHY's submode, 1 = G4, 0 = non-G4 */
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is_g4 = !!ufs_qcom_phy->submode;
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is_rate_B = (ufs_qcom_phy->mode == PHY_MODE_UFS_HS_B) ? true : false;
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writel_relaxed(0x01, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET);
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/* Ensure PHY is in reset before writing PHY calibration data */
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wmb();
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/*
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* Writing PHY calibration in this order:
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* 1. Write Rate-A calibration first (1-lane mode).
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* Apply G3 or G4 specific settings (v2 may have additional
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* settings).
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* 2. Write 2nd lane configuration if needed.
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* Apply G3 or G4 specific settings (v2 may have additional
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* settings).
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* 3. Write Rate-B calibration overrides
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*/
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A,
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ARRAY_SIZE(phy_cal_table_rate_A));
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if (!is_g4)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_g3,
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ARRAY_SIZE(phy_cal_table_rate_A_g3));
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else
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_A_g4,
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ARRAY_SIZE(phy_cal_table_rate_A_g4));
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if (check_v2(major, minor, step)) {
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if (!is_g4)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_rate_A_v2_g3,
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ARRAY_SIZE(phy_cal_table_rate_A_v2_g3));
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else
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_rate_A_v2_g4,
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ARRAY_SIZE(phy_cal_table_rate_A_v2_g4));
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}
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if (ufs_qcom_phy->lanes_per_direction == 2) {
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_2nd_lane,
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ARRAY_SIZE(phy_cal_table_2nd_lane));
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if (check_v2(major, minor, step)) {
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if (!is_g4)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_2nd_lane_v2_g3,
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ARRAY_SIZE(phy_cal_table_2nd_lane_v2_g3));
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else
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ufs_qcom_phy_write_tbl(ufs_qcom_phy,
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phy_cal_table_2nd_lane_v2_g4,
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ARRAY_SIZE(phy_cal_table_2nd_lane_v2_g4));
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}
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}
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if (is_rate_B)
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ufs_qcom_phy_write_tbl(ufs_qcom_phy, phy_cal_table_rate_B,
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ARRAY_SIZE(phy_cal_table_rate_B));
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if (check_v1(major, minor, step)) {
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writel_relaxed(0x01, ufs_qcom_phy->mmio +
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QSERDES_RX0_AC_JTAG_ENABLE);
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writel_relaxed(0x01, ufs_qcom_phy->mmio +
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QSERDES_RX0_AC_JTAG_MODE);
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writel_relaxed(0x01, ufs_qcom_phy->mmio +
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QSERDES_RX1_AC_JTAG_ENABLE);
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writel_relaxed(0x01, ufs_qcom_phy->mmio +
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QSERDES_RX1_AC_JTAG_MODE);
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}
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writel_relaxed(0x00, ufs_qcom_phy->mmio + UFS_PHY_SW_RESET);
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/* flush buffered writes */
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wmb();
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err = reset_control_deassert(ufs_qcom_phy->ufs_reset);
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if (err) {
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dev_err(dev, "Failed to deassert UFS PHY reset %d\n", err);
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goto out;
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}
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ufs_qcom_phy_qmp_v4_start_serdes(ufs_qcom_phy);
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err = ufs_qcom_phy_qmp_v4_is_pcs_ready(ufs_qcom_phy);
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_v4_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy_qmp_v4 *phy = phy_get_drvdata(generic_phy);
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struct ufs_qcom_phy *phy_common = &phy->common_cfg;
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int err;
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err = ufs_qcom_phy_init_clks(phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
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__func__, err);
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goto out;
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}
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err = ufs_qcom_phy_init_vregulators(phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
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__func__, err);
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goto out;
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}
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/* Optional */
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ufs_qcom_phy_get_reset(phy_common);
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_v4_exit(struct phy *generic_phy)
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{
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return 0;
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}
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static
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int ufs_qcom_phy_qmp_v4_set_mode(struct phy *generic_phy,
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enum phy_mode mode, int submode)
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{
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struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
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phy_common->mode = PHY_MODE_INVALID;
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if (mode > 0)
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phy_common->mode = mode;
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phy_common->submode = submode;
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return 0;
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}
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static
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void ufs_qcom_phy_qmp_v4_power_control(struct ufs_qcom_phy *phy,
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bool power_ctrl)
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{
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if (!power_ctrl) {
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/* apply analog power collapse */
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writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Make sure that PHY knows its analog rail is going to be
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* powered OFF.
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*/
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mb();
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} else {
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/* bring PHY out of analog power collapse */
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writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON.
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*/
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mb();
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}
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}
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static inline
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void ufs_qcom_phy_qmp_v4_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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/*
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* v4 PHY does not have TX_LANE_ENABLE register.
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* Implement this function so as not to propagate error to caller.
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*/
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}
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static
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void ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)
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{
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u32 temp;
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temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);
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if (ctrl) /* enable RX LineCfg */
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temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;
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else /* disable RX LineCfg */
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temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;
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writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);
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/* make sure that RX LineCfg config applied before we return */
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mb();
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}
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static inline void ufs_qcom_phy_qmp_v4_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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static int ufs_qcom_phy_qmp_v4_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err) {
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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goto out;
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}
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out:
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return err;
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}
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static void ufs_qcom_phy_qmp_v4_dbg_register_dump(struct ufs_qcom_phy *phy)
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{
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ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
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"PHY QSERDES COM Registers ");
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ufs_qcom_phy_dump_regs(phy, PCS2_BASE, PCS2_SIZE,
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"PHY PCS2 Registers ");
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ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE,
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"PHY Registers ");
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ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE,
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"PHY RX0 Registers ");
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ufs_qcom_phy_dump_regs(phy, TX_BASE(0), TX_SIZE,
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"PHY TX0 Registers ");
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ufs_qcom_phy_dump_regs(phy, RX_BASE(1), RX_SIZE,
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"PHY RX1 Registers ");
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ufs_qcom_phy_dump_regs(phy, TX_BASE(1), TX_SIZE,
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"PHY TX1 Registers ");
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}
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static const struct phy_ops ufs_qcom_phy_qmp_v4_phy_ops = {
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.init = ufs_qcom_phy_qmp_v4_init,
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.exit = ufs_qcom_phy_qmp_v4_exit,
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.set_mode = ufs_qcom_phy_qmp_v4_set_mode,
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.calibrate = ufs_qcom_phy_qmp_v4_phy_calibrate,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_v4_ops = {
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.start_serdes = ufs_qcom_phy_qmp_v4_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v4_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_v4_set_tx_lane_enable,
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.ctrl_rx_linecfg = ufs_qcom_phy_qmp_v4_ctrl_rx_linecfg,
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.power_control = ufs_qcom_phy_qmp_v4_power_control,
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.dbg_register_dump = ufs_qcom_phy_qmp_v4_dbg_register_dump,
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};
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static int ufs_qcom_phy_qmp_v4_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_v4 *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qmp_v4_phy_ops, &phy_v4_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_v4_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-v4"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v4_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_v4_driver = {
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.probe = ufs_qcom_phy_qmp_v4_probe,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_v4_of_match,
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.name = "ufs_qcom_phy_qmp_v4",
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_v4_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v4");
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MODULE_LICENSE("GPL v2");
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