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android_kernel_xiaomi_sm8350/drivers/iommu/msm_iommu_hw-8xxx.h

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Merge remote-tracking branch 'remotes/origin/tmp-f686d9f' into msm-lahaina * remotes/origin/tmp-f686d9f: ANDROID: update abi_gki_aarch64.xml for 5.2-rc6 Linux 5.2-rc6 Revert "iommu/vt-d: Fix lock inversion between iommu->lock and device_domain_lock" Bluetooth: Fix regression with minimum encryption key size alignment tcp: refine memory limit test in tcp_fragment() x86/vdso: Prevent segfaults due to hoisted vclock reads SUNRPC: Fix a credential refcount leak Revert "SUNRPC: Declare RPC timers as TIMER_DEFERRABLE" net :sunrpc :clnt :Fix xps refcount imbalance on the error path NFS4: Only set creation opendata if O_CREAT ANDROID: gki_defconfig: workaround to enable configs ANDROID: gki_defconfig: more configs for partners ARM: 8867/1: vdso: pass --be8 to linker if necessary KVM: nVMX: reorganize initial steps of vmx_set_nested_state KVM: PPC: Book3S HV: Invalidate ERAT when flushing guest TLB entries habanalabs: use u64_to_user_ptr() for reading user pointers nfsd: replace Jeff by Chuck as nfsd co-maintainer inet: clear num_timeout reqsk_alloc() PCI/P2PDMA: Ignore root complex whitelist when an IOMMU is present net: mvpp2: debugfs: Add pmap to fs dump ipv6: Default fib6_type to RTN_UNICAST when not set net: hns3: Fix inconsistent indenting net/af_iucv: always register net_device notifier net/af_iucv: build proper skbs for HiperTransport net/af_iucv: remove GFP_DMA restriction for HiperTransport doc: fix documentation about UIO_MEM_LOGICAL using MAINTAINERS / Documentation: Thorsten Scherer is the successor of Gavin Schenk docs: fb: Add TER16x32 to the available font names MAINTAINERS: fpga: hand off maintainership to Moritz treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 507 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 506 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 505 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 504 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 503 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 502 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 501 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 499 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 498 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 497 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 496 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 495 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 491 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 490 treewide: Replace GPLv2 boilerplate/reference with SPDX - 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rule 454 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 452 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 451 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 250 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 248 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 247 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 246 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 245 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 244 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 243 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 239 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 238 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 237 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 235 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 233 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 232 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 231 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 230 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 226 KVM: arm/arm64: Fix emulated ptimer irq injection net: dsa: mv88e6xxx: fix shift of FID bits in mv88e6185_g1_vtu_loadpurge() tests: kvm: Check for a kernel warning kvm: tests: Sort tests in the Makefile alphabetically KVM: x86/mmu: Allocate PAE root array when using SVM's 32-bit NPT KVM: x86: Modify struct kvm_nested_state to have explicit fields for data fanotify: update connector fsid cache on add mark quota: fix a problem about transfer quota drm/i915: Don't clobber M/N values during fastset check powerpc: enable a 30-bit ZONE_DMA for 32-bit pmac ovl: make i_ino consistent with st_ino in more cases scsi: qla2xxx: Fix hardlockup in abort command during driver remove scsi: ufs: Avoid runtime suspend possibly being blocked forever scsi: qedi: update driver version to 8.37.0.20 scsi: qedi: Check targetname while finding boot target information hvsock: fix epollout hang from race condition net/udp_gso: Allow TX timestamp with UDP GSO net: netem: fix use after free and double free with packet corruption net: netem: fix backlog accounting for corrupted GSO frames net: lio_core: fix potential sign-extension overflow on large shift tipc: pass tunnel dev as NULL to udp_tunnel(6)_xmit_skb ip6_tunnel: allow not to count pkts on tstats by passing dev as NULL ip_tunnel: allow not to count pkts on tstats by setting skb's dev to NULL apparmor: reset pos on failure to unpack for various functions apparmor: enforce nullbyte at end of tag string apparmor: fix PROFILE_MEDIATES for untrusted input RDMA/efa: Handle mmap insertions overflow tun: wake up waitqueues after IFF_UP is set drm: return -EFAULT if copy_to_user() fails net: remove duplicate fetch in sock_getsockopt tipc: fix issues with early FAILOVER_MSG from peer bnx2x: Check if transceiver implements DDM before access xhci: detect USB 3.2 capable host controllers correctly usb: xhci: Don't try to recover an endpoint if port is in error state. KVM: fix typo in documentation drm/panfrost: Make sure a BO is only unmapped when appropriate md: fix for divide error in status_resync soc: ixp4xx: npe: Fix an IS_ERR() vs NULL check in probe arm64/mm: don't initialize pgd_cache twice MAINTAINERS: Update my email address arm64/sve: <uapi/asm/ptrace.h> should not depend on <uapi/linux/prctl.h> ovl: fix typo in MODULE_PARM_DESC ovl: fix bogus -Wmaybe-unitialized warning ovl: don't fail with disconnected lower NFS mmc: core: Prevent processing SDIO IRQs when the card is suspended mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning brcmfmac: sdio: Don't tune while the card is off mmc: core: Add sdio_retune_hold_now() and sdio_retune_release() brcmfmac: sdio: Disable auto-tuning around commands expected to fail mmc: core: API to temporarily disable retuning for SDIO CRC errors Revert "brcmfmac: disable command decode in sdio_aos" ARM: ixp4xx: include irqs.h where needed ARM: ixp4xx: mark ixp4xx_irq_setup as __init ARM: ixp4xx: don't select SERIAL_OF_PLATFORM firmware: trusted_foundations: add ARMv7 dependency usb: dwc2: Use generic PHY width in params setup RDMA/efa: Fix success return value in case of error IB/hfi1: Handle port down properly in pio IB/hfi1: Handle wakeup of orphaned QPs for pio IB/hfi1: Wakeup QPs orphaned on wait list after flush IB/hfi1: Use aborts to trigger RC throttling IB/hfi1: Create inline to get extended headers IB/hfi1: Silence txreq allocation warnings IB/hfi1: Avoid hardlockup with flushlist_lock KVM: PPC: Book3S HV: Only write DAWR[X] when handling h_set_dawr in real mode KVM: PPC: Book3S HV: Fix r3 corruption in h_set_dabr() fs/namespace: fix unprivileged mount propagation vfs: fsmount: add missing mntget() cifs: fix GlobalMid_Lock bug in cifs_reconnect SMB3: retry on STATUS_INSUFFICIENT_RESOURCES instead of failing write staging: erofs: add requirements field in superblock arm64: ssbd: explicitly depend on <linux/prctl.h> block: fix page leak when merging to same page block: return from __bio_try_merge_page if merging occured in the same page Btrfs: fix failure to persist compression property xattr deletion on fsync riscv: remove unused barrier defines usb: chipidea: udc: workaround for endpoint conflict issue MAINTAINERS: Change QCOM repo location mmc: mediatek: fix SDIO IRQ detection issue mmc: mediatek: fix SDIO IRQ interrupt handle flow mmc: core: complete HS400 before checking status riscv: mm: synchronize MMU after pte change MAINTAINERS: Update my email address to use @kernel.org ANDROID: update abi_gki_aarch64.xml for 5.2-rc5 riscv: dts: add initial board data for the SiFive HiFive Unleashed riscv: dts: add initial support for the SiFive FU540-C000 SoC dt-bindings: riscv: convert cpu binding to json-schema dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 arch: riscv: add support for building DTB files from DT source data drm/i915/gvt: ignore unexpected pvinfo write lapb: fixed leak of control-blocks. tipc: purge deferredq list for each grp member in tipc_group_delete ax25: fix inconsistent lock state in ax25_destroy_timer neigh: fix use-after-free read in pneigh_get_next tcp: fix compile error if !CONFIG_SYSCTL hv_sock: Suppress bogus "may be used uninitialized" warnings be2net: Fix number of Rx queues used for flow hashing net: handle 802.1P vlan 0 packets properly Linux 5.2-rc5 tcp: enforce tcp_min_snd_mss in tcp_mtu_probing() tcp: add tcp_min_snd_mss sysctl tcp: tcp_fragment() should apply sane memory limits tcp: limit payload size of sacked skbs Revert "net: phylink: set the autoneg state in phylink_phy_change" bpf: fix nested bpf tracepoints with per-cpu data bpf: Fix out of bounds memory access in bpf_sk_storage vsock/virtio: set SOCK_DONE on peer shutdown net: dsa: rtl8366: Fix up VLAN filtering net: phylink: set the autoneg state in phylink_phy_change powerpc/32: fix build failure on book3e with KVM powerpc/booke: fix fast syscall entry on SMP powerpc/32s: fix initial setup of segment registers on secondary CPU x86/microcode, cpuhotplug: Add a microcode loader CPU hotplug callback net: add high_order_alloc_disable sysctl/static key tcp: add tcp_tx_skb_cache sysctl tcp: add tcp_rx_skb_cache sysctl sysctl: define proc_do_static_key() hv_netvsc: Set probe mode to sync net: sched: flower: don't call synchronize_rcu() on mask creation net: dsa: fix warning same module names sctp: Free cookie before we memdup a new one net: dsa: microchip: Don't try to read stats for unused ports qmi_wwan: extend permitted QMAP mux_id value range qmi_wwan: avoid RCU stalls on device disconnect when in QMAP mode qmi_wwan: add network device usage statistics for qmimux devices qmi_wwan: add support for QMAP padding in the RX path bpf, x64: fix stack layout of JITed bpf code Smack: Restore the smackfsdef mount option and add missing prefixes bpf, devmap: Add missing RCU read lock on flush bpf, devmap: Add missing bulk queue free bpf, devmap: Fix premature entry free on destroying map ftrace: Fix NULL pointer dereference in free_ftrace_func_mapper() module: Fix livepatch/ftrace module text permissions race tracing/uprobe: Fix obsolete comment on trace_uprobe_create() tracing/uprobe: Fix NULL pointer dereference in trace_uprobe_create() tracing: Make two symbols static tracing: avoid build warning with HAVE_NOP_MCOUNT tracing: Fix out-of-range read in trace_stack_print() gfs2: Fix rounding error in gfs2_iomap_page_prepare net: phylink: further mac_config documentation improvements nfc: Ensure presence of required attributes in the deactivate_target handler btrfs: start readahead also in seed devices x86/kasan: Fix boot with 5-level paging and KASAN cfg80211: report measurement start TSF correctly cfg80211: fix memory leak of wiphy device name cfg80211: util: fix bit count off by one mac80211: do not start any work during reconfigure flow cfg80211: use BIT_ULL in cfg80211_parse_mbssid_data() mac80211: only warn once on chanctx_conf being NULL mac80211: drop robust management frames from unknown TA gpu: ipu-v3: image-convert: Fix image downsize coefficients gpu: ipu-v3: image-convert: Fix input bytesperline for packed formats gpu: ipu-v3: image-convert: Fix input bytesperline width/height align thunderbolt: Implement CIO reset correctly for Titan Ridge ARM: davinci: da8xx: specify dma_coherent_mask for lcdc ARM: davinci: da850-evm: call regulator_has_full_constraints() timekeeping: Repair ktime_get_coarse*() granularity Revert "ALSA: hda/realtek - Improve the headset mic for Acer Aspire laptops" ANDROID: update abi_gki_aarch64.xml mm/devm_memremap_pages: fix final page put race PCI/P2PDMA: track pgmap references per resource, not globally lib/genalloc: introduce chunk owners PCI/P2PDMA: fix the gen_pool_add_virt() failure path mm/devm_memremap_pages: introduce devm_memunmap_pages drivers/base/devres: introduce devm_release_action() mm/vmscan.c: fix trying to reclaim unevictable LRU page coredump: fix race condition between collapse_huge_page() and core dumping mm/mlock.c: change count_mm_mlocked_page_nr return type mm: mmu_gather: remove __tlb_reset_range() for force flush fs/ocfs2: fix race in ocfs2_dentry_attach_lock() mm/vmscan.c: fix recent_rotated history mm/mlock.c: mlockall error for flag MCL_ONFAULT scripts/decode_stacktrace.sh: prefix addr2line with $CROSS_COMPILE mm/list_lru.c: fix memory leak in __memcg_init_list_lru_node mm: memcontrol: don't batch updates of local VM stats and events PCI: PM: Skip devices in D0 for suspend-to-idle ANDROID: Removed extraneous configs from gki powerpc/bpf: use unsigned division instruction for 64-bit operations bpf: fix div64 overflow tests to properly detect errors bpf: sync BPF_FIB_LOOKUP flag changes with BPF uapi bpf: simplify definition of BPF_FIB_LOOKUP related flags cifs: add spinlock for the openFileList to cifsInodeInfo cifs: fix panic in smb2_reconnect x86/fpu: Don't use current->mm to check for a kthread KVM: nVMX: use correct clean fields when copying from eVMCS vfio-ccw: Destroy kmem cache region on module exit block/ps3vram: Use %llu to format sector_t after LBDAF removal libata: Extend quirks for the ST1000LM024 drives with NOLPM quirk bcache: only set BCACHE_DEV_WB_RUNNING when cached device attached bcache: fix stack corruption by PRECEDING_KEY() arm64/sve: Fix missing SVE/FPSIMD endianness conversions blk-mq: remove WARN_ON(!q->elevator) from blk_mq_sched_free_requests blkio-controller.txt: Remove references to CFQ block/switching-sched.txt: Update to blk-mq schedulers null_blk: remove duplicate check for report zone blk-mq: no need to check return value of debugfs_create functions io_uring: fix memory leak of UNIX domain socket inode block: force select mq-deadline for zoned block devices binder: fix possible UAF when freeing buffer drm/amdgpu: return 0 by default in amdgpu_pm_load_smu_firmware drm/amdgpu: Fix bounds checking in amdgpu_ras_is_supported() ANDROID: x86 gki_defconfig: enable DMA_CMA ANDROID: Fixed x86 regression ANDROID: gki_defconfig: enable DMA_CMA Input: synaptics - enable SMBus on ThinkPad E480 and E580 net: mvpp2: prs: Use the correct helpers when removing all VID filters net: mvpp2: prs: Fix parser range for VID filtering mlxsw: spectrum: Disallow prio-tagged packets when PVID is removed mlxsw: spectrum_buffers: Reduce pool size on Spectrum-2 selftests: tc_flower: Add TOS matching test mlxsw: spectrum_flower: Fix TOS matching selftests: mlxsw: Test nexthop offload indication mlxsw: spectrum_router: Refresh nexthop neighbour when it becomes dead mlxsw: spectrum: Use different seeds for ECMP and LAG hash net: tls, correctly account for copied bytes with multiple sk_msgs vrf: Increment Icmp6InMsgs on the original netdev cpuset: restore sanity to cpuset_cpus_allowed_fallback() net: ethtool: Allow matching on vlan DEI bit linux-next: DOC: RDS: Fix a typo in rds.txt x86/kgdb: Return 0 from kgdb_arch_set_breakpoint() mpls: fix af_mpls dependencies for real selinux: fix a missing-check bug in selinux_sb_eat_lsm_opts() selinux: fix a missing-check bug in selinux_add_mnt_opt( ) arm64: tlbflush: Ensure start/end of address range are aligned to stride usb: typec: Make sure an alt mode exist before getting its partner KVM: arm/arm64: vgic: Fix kvm_device leak in vgic_its_destroy KVM: arm64: Filter out invalid core register IDs in KVM_GET_REG_LIST KVM: arm64: Implement vq_present() as a macro xdp: check device pointer before clearing bpf: net: Set sk_bpf_storage back to NULL for cloned sk Btrfs: fix race between block group removal and block group allocation clocksource/drivers/arm_arch_timer: Don't trace count reader functions i2c: pca-platform: Fix GPIO lookup code thunderbolt: Make sure device runtime resume completes before taking domain lock drm: add fallback override/firmware EDID modes workaround i2c: acorn: fix i2c warning arm64: Don't unconditionally add -Wno-psabi to KBUILD_CFLAGS drm/edid: abstract override/firmware EDID retrieval platform/mellanox: mlxreg-hotplug: Add devm_free_irq call to remove flow platform/x86: mlx-platform: Fix parent device in i2c-mux-reg device registration platform/x86: intel-vbtn: Report switch events when event wakes device platform/x86: asus-wmi: Only Tell EC the OS will handle display hotkeys from asus_nb_wmi ARM: mvebu_v7_defconfig: fix Ethernet on Clearfog x86/resctrl: Prevent NULL pointer dereference when local MBM is disabled x86/resctrl: Don't stop walking closids when a locksetup group is found iommu/arm-smmu: Avoid constant zero in TLBI writes drm/i915/perf: fix whitelist on Gen10+ drm/i915/sdvo: Implement proper HDMI audio support for SDVO drm/i915: Fix per-pixel alpha with CCS drm/i915/dmc: protect against reading random memory drm/i915/dsi: Use a fuzzy check for burst mode clock check Input: imx_keypad - make sure keyboard can always wake up system selinux: log raw contexts as untrusted strings ptrace: restore smp_rmb() in __ptrace_may_access() IB/hfi1: Correct tid qp rcd to match verbs context IB/hfi1: Close PSM sdma_progress sleep window IB/hfi1: Validate fault injection opcode user input geneve: Don't assume linear buffers in error handler vxlan: Don't assume linear buffers in error handler net: openvswitch: do not free vport if register_netdevice() is failed. net: correct udp zerocopy refcnt also when zerocopy only on append drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc ovl: fix wrong flags check in FS_IOC_FS[SG]ETXATTR ioctls riscv: Fix udelay in RV32. drm/vmwgfx: fix a warning due to missing dma_parms riscv: export pm_power_off again drm/vmwgfx: Honor the sg list segment size limitation RISC-V: defconfig: enable clocks, serial console drm/vmwgfx: Use the backdoor port if the HB port is not available bpf: lpm_trie: check left child of last leftmost node for NULL Revert "fuse: require /dev/fuse reads to have enough buffer capacity" ALSA: ice1712: Check correct return value to snd_i2c_sendbytes (EWS/DMX 6Fire) ALSA: oxfw: allow PCM capture for Stanton SCS.1m ALSA: firewire-motu: fix destruction of data for isochronous resources s390/ctl_reg: mark __ctl_set_bit and __ctl_clear_bit as __always_inline s390/boot: disable address-of-packed-member warning ANDROID: update gki aarch64 ABI representation cgroup: Fix css_task_iter_advance_css_set() cset skip condition drm/panfrost: Require the simple_ondemand governor drm/panfrost: make devfreq optional again drm/gem_shmem: Use a writecombine mapping for ->vaddr mmc: sdhi: disallow HS400 for M3-W ES1.2, RZ/G2M, and V3H ASoC: Intel: sst: fix kmalloc call with wrong flags ASoC: core: Fix deadlock in snd_soc_instantiate_card() cgroup/bfq: revert bfq.weight symlink change ARM: dts: am335x phytec boards: Fix cd-gpios active level ARM: dts: dra72x: Disable usb4_tm target module nfp: ensure skb network header is set for packet redirect tcp: fix undo spurious SYNACK in passive Fast Open mpls: fix af_mpls dependencies ibmvnic: Fix unchecked return codes of memory allocations ibmvnic: Refresh device multicast list after reset ibmvnic: Do not close unopened driver during reset mpls: fix warning with multi-label encap net: phy: rename Asix Electronics PHY driver ipv6: flowlabel: fl6_sock_lookup() must use atomic_inc_not_zero net: ipv4: fib_semantics: fix uninitialized variable Input: iqs5xx - get axis info before calling input_mt_init_slots() Linux 5.2-rc4 drm: panel-orientation-quirks: Add quirk for GPD MicroPC drm: panel-orientation-quirks: Add quirk for GPD pocket2 counter/ftm-quaddec: Add missing dependencies in Kconfig staging: iio: adt7316: Fix build errors when GPIOLIB is not set x86/fpu: Update kernel's FPU state before using for the fsave header MAINTAINERS: Karthikeyan Ramasubramanian is MIA i2c: xiic: Add max_read_len quirk ANDROID: update ABI representation gpio: pca953x: hack to fix 24 bit gpio expanders net/mlx5e: Support tagged tunnel over bond net/mlx5e: Avoid detaching non-existing netdev under switchdev mode net/mlx5e: Fix source port matching in fdb peer flow rule net/mlx5e: Replace reciprocal_scale in TX select queue function net/mlx5e: Add ndo_set_feature for uplink representor net/mlx5: Avoid reloading already removed devices net/mlx5: Update pci error handler entries and command translation RAS/CEC: Convert the timer callback to a workqueue RAS/CEC: Fix binary search function x86/mm/KASLR: Compute the size of the vmemmap section properly can: purge socket error queue on sock destruct can: flexcan: Remove unneeded registration message can: af_can: Fix error path of can_init() can: m_can: implement errata "Needless activation of MRAF irq" can: mcp251x: add support for mcp25625 dt-bindings: can: mcp251x: add mcp25625 support can: xilinx_can: use correct bittiming_const for CAN FD core can: flexcan: fix timeout when set small bitrate can: usb: Kconfig: Remove duplicate menu entry lockref: Limit number of cmpxchg loop retries uaccess: add noop untagged_addr definition x86/insn-eval: Fix use-after-free access to LDT entry kbuild: use more portable 'command -v' for cc-cross-prefix s390/unwind: correct stack switching during unwind scsi: hpsa: correct ioaccel2 chaining btrfs: Always trim all unallocated space in btrfs_trim_free_extents netfilter: ipv6: nf_defrag: accept duplicate fragments again powerpc/32s: fix booting with CONFIG_PPC_EARLY_DEBUG_BOOTX drm/meson: fix G12A primary plane disabling drm/meson: fix primary plane disabling drm/meson: fix G12A HDMI PLL settings for 4K60 1000/1001 variations block, bfq: add weight symlink to the bfq.weight cgroup parameter cgroup: let a symlink too be created with a cftype file powerpc/64s: __find_linux_pte() synchronization vs pmdp_invalidate() powerpc/64s: Fix THP PMD collapse serialisation powerpc: Fix kexec failure on book3s/32 drm/nouveau/secboot/gp10[2467]: support newer FW to fix SEC2 failures on some boards drm/nouveau/secboot: enable loading of versioned LS PMU/SEC2 ACR msgqueue FW drm/nouveau/secboot: split out FW version-specific LS function pointers drm/nouveau/secboot: pass max supported FW version to LS load funcs drm/nouveau/core: support versioned firmware loading drm/nouveau/core: pass subdev into nvkm_firmware_get, rather than device block: free sched's request pool in blk_cleanup_queue bpf: expand section tests for test_section_names bpf: more msg_name rewrite tests to test_sock_addr bpf, bpftool: enable recvmsg attach types bpf, libbpf: enable recvmsg attach types bpf: sync tooling uapi header bpf: fix unconnected udp hooks vfio/mdev: Synchronize device create/remove with parent removal vfio/mdev: Avoid creating sysfs remove file on stale device removal pktgen: do not sleep with the thread lock held. net: mvpp2: Use strscpy to handle stat strings net: rds: fix memory leak in rds_ib_flush_mr_pool ipv6: fix EFAULT on sendto with icmpv6 and hdrincl ipv6: use READ_ONCE() for inet->hdrincl as in ipv4 soundwire: intel: set dai min and max channels correctly soundwire: stream: fix bad unlock balance x86/fpu: Use fault_in_pages_writeable() for pre-faulting nvme-rdma: use dynamic dma mapping per command nvme: Fix u32 overflow in the number of namespace list calculation vfio/mdev: Improve the create/remove sequence SoC: rt274: Fix internal jack assignment in set_jack callback ALSA: hdac: fix memory release for SST and SOF drivers ASoC: SOF: Intel: hda: use the defined ppcap functions ASoC: core: move DAI pre-links initiation to snd_soc_instantiate_card ASoC: Intel: cht_bsw_rt5672: fix kernel oops with platform_name override ASoC: Intel: cht_bsw_nau8824: fix kernel oops with platform_name override ASoC: Intel: bytcht_es8316: fix kernel oops with platform_name override ASoC: Intel: cht_bsw_max98090: fix kernel oops with platform_name override Revert "gfs2: Replace gl_revokes with a GLF flag" arm64: Silence gcc warnings about arch ABI drift parisc: Fix crash due alternative coding for NP iopdir_fdc bit parisc: Use lpa instruction to load physical addresses in driver code parisc: configs: Remove useless UEVENT_HELPER_PATH parisc: Use implicit space register selection for loading the coherence index of I/O pdirs usb: gadget: udc: lpc32xx: fix return value check in lpc32xx_udc_probe() usb: gadget: dwc2: fix zlp handling usb: dwc2: Set actual frame number for completed ISOC transfer for none DDMA usb: gadget: udc: lpc32xx: allocate descriptor with GFP_ATOMIC usb: gadget: fusb300_udc: Fix memory leak of fusb300->ep[i] usb: phy: mxs: Disable external charger detect in mxs_phy_hw_init() usb: dwc2: Fix DMA cache alignment issues usb: dwc2: host: Fix wMaxPacketSize handling (fix webcam regression) ARM64: trivial: s/TIF_SECOMP/TIF_SECCOMP/ comment typo fix drm/komeda: Potential error pointer dereference drm/komeda: remove set but not used variable 'kcrtc' x86/CPU: Add more Icelake model numbers hwmon: (pmbus/core) Treat parameters as paged if on multiple pages hwmon: (pmbus/core) mutex_lock write in pmbus_set_samples hwmon: (core) add thermal sensors only if dev->of_node is present Revert "fib_rules: return 0 directly if an exactly same rule exists when NLM_F_EXCL not supplied" net: aquantia: fix wol configuration not applied sometimes ethtool: fix potential userspace buffer overflow Fix memory leak in sctp_process_init net: rds: fix memory leak when unload rds_rdma ipv6: fix the check before getting the cookie in rt6_get_cookie ipv4: not do cache for local delivery if bc_forwarding is enabled selftests: vm: Fix test build failure when built by itself tools: bpftool: Fix JSON output when lookup fails mmc: also set max_segment_size in the device mtip32xx: also set max_segment_size in the device rsxx: don't call dma_set_max_seg_size nvme-pci: don't limit DMA segement size s390/qeth: handle error when updating TX queue count s390/qeth: fix VLAN attribute in bridge_hostnotify udev event s390/qeth: check dst entry before use s390/qeth: handle limited IPv4 broadcast in L3 TX path ceph: fix error handling in ceph_get_caps() ceph: avoid iput_final() while holding mutex or in dispatch thread ceph: single workqueue for inode related works cgroup: css_task_iter_skip()'d iterators must be advanced before accessed drm/amd/amdgpu: add RLC firmware to support raven1 refresh drm/amd/powerplay: add set_power_profile_mode for raven1_refresh drm/amdgpu: fix ring test failure issue during s3 in vce 3.0 (V2) treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 450 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 449 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 448 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 444 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 443 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 442 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 440 treewide: Replace GPLv2 boilerplate/reference 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Handle Clang auto-initialization pattern block: Drop unlikely before IS_ERR(_OR_NULL) xen/swiotlb: don't initialize swiotlb twice on arm64 s390/mm: fix address space detection in exception handling HID: logitech-dj: Fix 064d:c52f receiver support Revert "HID: core: Call request_module before doing device_add" Revert "HID: core: Do not call request_module() in async context" Revert "HID: Increase maximum report size allowed by hid_field_extract()" tests: fix pidfd-test compilation signal: improve comments samples: fix pidfd-metadata compilation arm64: arch_timer: mark functions as __always_inline arm64: smp: Moved cpu_logical_map[] to smp.h arm64: cpufeature: Fix missing ZFR0 in __read_sysreg_by_encoding() selftests/bpf: move test_lirc_mode2_user to TEST_GEN_PROGS_EXTENDED USB: Fix chipmunk-like voice when using Logitech C270 for recording audio. USB: usb-storage: Add new ID to ums-realtek udmabuf: actually unmap the scatterlist net: fix indirect calls helpers for ptype list hooks. net: ipvlan: Fix ipvlan device tso disabled while NETIF_F_IP_CSUM is set scsi: smartpqi: unlock on error in pqi_submit_raid_request_synchronous() scsi: ufs: Check that space was properly alloced in copy_query_response udp: only choose unbound UDP socket for multicast when not in a VRF net/tls: replace the sleeping lock around RX resync with a bit lock Revert "net/tls: avoid NULL-deref on resync during device removal" block: aoe: no need to check return value of debugfs_create functions net: dsa: sja1105: Fix link speed not working at 100 Mbps and below net: phylink: avoid reducing support mask scripts/checkstack.pl: Fix arm64 wrong or unknown architecture kbuild: tar-pkg: enable communication with jobserver kconfig: tests: fix recursive inclusion unit test kbuild: teach kselftest-merge to find nested config files nvmet: fix data_len to 0 for bdev-backed write_zeroes MAINTAINERS: Hand over skd maintainership ASoC: sun4i-i2s: Add offset to RX channel select ASoC: sun4i-i2s: Fix sun8i tx channel offset mask ASoC: max98090: remove 24-bit format support if RJ is 0 ASoC: da7219: Fix build error without CONFIG_I2C ASoC: SOF: Intel: hda: Fix COMPILE_TEST build error drm/arm/hdlcd: Allow a bit of clock tolerance drm/arm/hdlcd: Actually validate CRTC modes drm/arm/mali-dp: Add a loop around the second set CVAL and try 5 times drm/komeda: fixing of DMA mapping sg segment warning netfilter: ipv6: nf_defrag: fix leakage of unqueued fragments habanalabs: Read upper bits of trace buffer from RWPHI arm64: arch_k3: Fix kconfig dependency warning drm: don't block fb changes for async plane updates drm/vc4: fix fb references in async update drm/msm: fix fb references in async update drm/amd: fix fb references in async update drm/rockchip: fix fb references in async update xen-blkfront: switch kcalloc to kvcalloc for large array allocation drm/mediatek: call mtk_dsi_stop() after mtk_drm_crtc_atomic_disable() drm/mediatek: clear num_pipes when unbind driver drm/mediatek: call drm_atomic_helper_shutdown() when unbinding driver drm/mediatek: unbind components in mtk_drm_unbind() drm/mediatek: fix unbind functions net: sfp: read eeprom in maximum 16 byte increments selftests: set sysctl bc_forwarding properly in router_broadcast.sh ANDROID: update gki aarch64 ABI representation net: ethernet: mediatek: Use NET_IP_ALIGN to judge if HW RX_2BYTE_OFFSET is enabled net: ethernet: mediatek: Use hw_feature to judge if HWLRO is supported net: ethernet: ti: cpsw_ethtool: fix ethtool ring param set ANDROID: gki_defconfig: Enable CMA, SLAB_FREELIST (RANDOM and HARDENED) on x86 bpf: udp: Avoid calling reuseport's bpf_prog from udp_gro bpf: udp: ipv6: Avoid running reuseport's bpf_prog from __udp6_lib_err rcu: locking and unlocking need to always be at least barriers ANDROID: gki_defconfig: enable SLAB_FREELIST_RANDOM, SLAB_FREELIST_HARDENED ANDROID: gki_defconfig: enable CMA and increase CMA_AREAS ASoC: SOF: fix DSP oops definitions in FW ABI ASoC: hda: fix unbalanced codec dev refcount for HDA_DEV_ASOC ASoC: SOF: ipc: replace fw ready bitfield with explicit bit ordering ASoC: SOF: bump to ABI 3.6 ASoC: SOF: soundwire: add initial soundwire support ASoC: SOF: uapi: mirror firmware changes ASoC: Intel: Baytrail: add quirk for Aegex 10 (RU2) tablet xfs: inode btree scrubber should calculate im_boffset correctly mmc: sdhci_am654: Fix SLOTTYPE write usb: typec: ucsi: ccg: fix memory leak in do_flash ANDROID: update gki aarch64 ABI representation habanalabs: Fix virtual address access via debugfs for 2MB pages drm/komeda: Constify the usage of komeda_component/pipeline/dev_funcs x86/power: Fix 'nosmt' vs hibernation triple fault during resume mm/vmalloc: Avoid rare case of flushing TLB with weird arguments mm/vmalloc: Fix calculation of direct map addr range PM: sleep: Add kerneldoc comments to some functions drm/i915/gvt: save RING_HEAD into vreg when vgpu switched out sparc: perf: fix updated event period in response to PERF_EVENT_IOC_PERIOD mdesc: fix a missing-check bug in get_vdev_port_node_info() drm/i915/gvt: add F_CMD_ACCESS flag for wa regs sparc64: Fix regression in non-hypervisor TLB flush xcall packet: unconditionally free po->rollover Update my email address net: hns: Fix loopback test failed at copper ports Linux 5.2-rc3 net: dsa: mv88e6xxx: avoid error message on remove from VLAN 0 mm, compaction: make sure we isolate a valid PFN include/linux/generic-radix-tree.h: fix kerneldoc comment kernel/signal.c: trace_signal_deliver when signal_group_exit drivers/iommu/intel-iommu.c: fix variable 'iommu' set but not used spdxcheck.py: fix directory structures kasan: initialize tag to 0xff in __kasan_kmalloc z3fold: fix sheduling while atomic scripts/gdb: fix invocation when CONFIG_COMMON_CLK is not set mm/gup: continue VM_FAULT_RETRY processing even for pre-faults ocfs2: fix error path kobject memory leak memcg: make it work on sparse non-0-node systems mm, memcg: consider subtrees in memory.events prctl_set_mm: downgrade mmap_sem to read lock prctl_set_mm: refactor checks from validate_prctl_map kernel/fork.c: make max_threads symbol static arch/arm/boot/compressed/decompress.c: fix build error due to lz4 changes arch/parisc/configs/c8000_defconfig: remove obsoleted CONFIG_DEBUG_SLAB_LEAK mm/vmalloc.c: fix typo in comment lib/sort.c: fix kernel-doc notation warnings mm: fix Documentation/vm/hmm.rst Sphinx warnings treewide: fix typos of SPDX-License-Identifier crypto: ux500 - fix license comment syntax error MAINTAINERS: add I2C DT bindings to ARM platforms MAINTAINERS: add DT bindings to i2c drivers mwifiex: Fix heap overflow in mwifiex_uap_parse_tail_ies() iwlwifi: mvm: change TLC config cmd sent by rs to be async iwlwifi: Fix double-free problems in iwl_req_fw_callback() iwlwifi: fix AX201 killer sku loading firmware issue iwlwifi: print fseq info upon fw assert iwlwifi: clear persistence bit according to device family iwlwifi: fix load in rfkill flow for unified firmware iwlwifi: mvm: remove d3_sram debugfs file bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh libbpf: Return btf_fd for load_sk_storage_btf HID: a4tech: fix horizontal scrolling HID: hyperv: Add a module description line net: dsa: sja1105: Don't store frame type in skb->cb block: print offending values when cloned rq limits are exceeded blk-mq: Document the blk_mq_hw_queue_to_node() arguments blk-mq: Fix spelling in a source code comment block: Fix bsg_setup_queue() kernel-doc header block: Fix rq_qos_wait() kernel-doc header block: Fix blk_mq_*_map_queues() kernel-doc headers block: Fix throtl_pending_timer_fn() kernel-doc header block: Convert blk_invalidate_devt() header into a non-kernel-doc header block/partitions/ldm: Convert a kernel-doc header into a non-kernel-doc header leds: avoid flush_work in atomic context cgroup: Include dying leaders with live threads in PROCS iterations cgroup: Implement css_task_iter_skip() cgroup: Call cgroup_release() before __exit_signal() netfilter: nf_tables: fix module autoload with inet family Revert "lockd: Show pid of lockd for remote locks" ALSA: hda/realtek - Update headset mode for ALC256 fs/adfs: fix filename fixup handling for "/" and "//" names fs/adfs: move append_filetype_suffix() into adfs_object_fixup() fs/adfs: remove truncated filename hashing fs/adfs: factor out filename fixup fs/adfs: factor out object fixups fs/adfs: factor out filename case lowering fs/adfs: factor out filename comparison ovl: doc: add non-standard corner cases pstore/ram: Run without kernel crash dump region MAINTAINERS: add Vasily Gorbik and Christian Borntraeger for s390 MAINTAINERS: Farewell Martin Schwidefsky pstore: Set tfm to NULL on free_buf_for_compression nds32: add new emulations for floating point instruction nds32: Avoid IEX status being incorrectly modified math-emu: Use statement expressions to fix Wshift-count-overflow warning net: correct zerocopy refcnt with udp MSG_MORE ethtool: Check for vlan etype or vlan tci when parsing flow_rule net: don't clear sock->sk early to avoid trouble in strparser net-gro: fix use-after-free read in napi_gro_frags() net: dsa: tag_8021q: Create a stable binary format net: dsa: tag_8021q: Change order of rx_vid setup net: mvpp2: fix bad MVPP2_TXQ_SCHED_TOKEN_CNTR_REG queue value docs cgroups: add another example size for hugetlb NFSv4.1: Fix bug only first CB_NOTIFY_LOCK is handled NFSv4.1: Again fix a race where CB_NOTIFY_LOCK fails to wake a waiter ipv4: tcp_input: fix stack out of bounds when parsing TCP options. mlxsw: spectrum: Prevent force of 56G mlxsw: spectrum_acl: Avoid warning after identical rules insertion SUNRPC: Fix a use after free when a server rejects the RPCSEC_GSS credential net: dsa: mv88e6xxx: fix handling of upper half of STATS_TYPE_PORT SUNRPC fix regression in umount of a secure mount r8169: fix MAC address being lost in PCI D3 treewide: Add SPDX license identifier - Kbuild treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 225 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 224 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 223 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 222 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 221 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 220 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 218 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 217 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 216 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 215 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 214 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 213 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 211 treewide: Replace GPLv2 boilerplate/reference with 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Replace GPLv2 boilerplate/reference with SPDX - rule 133 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 132 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 131 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 130 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 129 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 128 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 127 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 126 net: core: support XDP generic on stacked devices. netvsc: unshare skb in VF rx handler udp: Avoid post-GRO UDP checksum recalculation nvme-tcp: fix queue mapping when queue count is limited nvme-rdma: fix queue mapping when queue count is limited fpga: zynqmp-fpga: Correctly handle error pointer selftests: vm: install test_vmalloc.sh for run_vmtests userfaultfd: selftest: fix compiler warning kselftest/cgroup: fix incorrect test_core skip kselftest/cgroup: fix unexpected testing failure on test_core kselftest/cgroup: fix unexpected testing failure on test_memcontrol xtensa: Fix section mismatch between memblock_reserve and mem_reserve signal/ptrace: Don't leak unitialized kernel memory with PTRACE_PEEK_SIGINFO mwifiex: Abort at too short BSS descriptor element mwifiex: Fix possible buffer overflows at parsing bss descriptor drm/i915/gvt: Assign NULL to the pointer after memory free. drm/i915/gvt: Check if cur_pt_type is valid x86: intel_epb: Do not build when CONFIG_PM is unset crypto: hmac - fix memory leak in hmac_init_tfm() crypto: jitterentropy - change back to module_init() ARM: dts: Drop bogus CLKSEL for timer12 on dra7 KVM: PPC: Book3S HV: Restore SPRG3 in kvmhv_p9_guest_entry() KVM: PPC: Book3S HV: Fix lockdep warning when entering guest on POWER9 KVM: PPC: Book3S HV: XIVE: Fix page offset when clearing ESB pages KVM: PPC: Book3S HV: XIVE: Take the srcu read lock when accessing memslots KVM: PPC: Book3S HV: XIVE: Do not clear IRQ data of passthrough interrupts KVM: PPC: Book3S HV: XIVE: Introduce a new mutex for the XIVE device drm/i915/gvt: Fix cmd length of VEB_DI_IECP drm/i915/gvt: refine ggtt range validation drm/i915/gvt: Fix vGPU CSFE_CHICKEN1_REG mmio handler drm/i915/gvt: Fix GFX_MODE handling drm/i915/gvt: Update force-to-nonpriv register whitelist drm/i915/gvt: Initialize intel_gvt_gtt_entry in stack ima: show rules with IMA_INMASK correctly evm: check hash algorithm passed to init_desc() scsi: libsas: delete sas port if expander discover failed scsi: libsas: only clear phy->in_shutdown after shutdown event done scsi: scsi_dh_alua: Fix possible null-ptr-deref scsi: smartpqi: properly set both the DMA mask and the coherent DMA mask scsi: zfcp: fix to prevent port_remove with pure auto scan LUNs (only sdevs) scsi: zfcp: fix missing zfcp_port reference put on -EBUSY from port_remove scsi: libcxgbi: add a check for NULL pointer in cxgbi_check_route() net: phy: dp83867: Set up RGMII TX delay net: phy: dp83867: do not call config_init twice net: phy: dp83867: increase SGMII autoneg timer duration net: phy: dp83867: fix speed 10 in sgmii mode net: phy: marvell10g: report if the PHY fails to boot firmware net: phylink: ensure consistent phy interface mode cgroup: Use css_tryget() instead of css_tryget_online() in task_get_css() blk-mq: Fix memory leak in error handling usbip: usbip_host: fix stub_dev lock context imbalance regression net: sh_eth: fix mdio access in sh_eth_close() for R-Car Gen2 and RZ/A1 SoCs MIPS: uprobes: remove set but not used variable 'epc' s390/crypto: fix possible sleep during spinlock aquired MIPS: pistachio: Build uImage.gz by default MIPS: Make virt_addr_valid() return bool MIPS: Bounds check virt_addr_valid CIFS: cifs_read_allocate_pages: don't iterate through whole page array on ENOMEM RDMA/efa: Remove MAYEXEC flag check from mmap flow mlx5: avoid 64-bit division IB/hfi1: Validate page aligned for a given virtual address IB/{qib, hfi1, rdmavt}: Correct ibv_devinfo max_mr value IB/hfi1: Insure freeze_work work_struct is canceled on shutdown IB/rdmavt: Fix alloc_qpn() WARN_ON() ASoC: sun4i-codec: fix first delay on Speaker drm/amdgpu: reserve stollen vram for raven series media: venus: hfi_parser: fix a regression in parser selftests: bpf: fix compiler warning in flow_dissector test arm64: use the correct function type for __arm64_sys_ni_syscall arm64: use the correct function type in SYSCALL_DEFINE0 arm64: fix syscall_fn_t type block: don't protect generic_make_request_checks with blk_queue_enter block: move blk_exit_queue into __blk_release_queue selftests: bpf: complete sub-register zero extension checks selftests: bpf: move sub-register zero extension checks into subreg.c ovl: detect overlapping layers drm/i915/icl: Add WaDisableBankHangMode ALSA: fireface: Use ULL suffixes for 64-bit constants signal/arm64: Use force_sig not force_sig_fault for SIGKILL nl80211: fill all policy .type entries mac80211: free peer keys before vif down in mesh ANDROID: ABI out: Use the extension .xml rather then .out drm/mediatek: respect page offset for PRIME mmap calls drm/mediatek: adjust ddp clock control flow ALSA: hda/realtek - Improve the headset mic for Acer Aspire laptops KVM: PPC: Book3S HV: XIVE: Fix the enforced limit on the vCPU identifier KVM: PPC: Book3S HV: XIVE: Do not test the EQ flag validity when resetting KVM: PPC: Book3S HV: XIVE: Clear file mapping when device is released KVM: PPC: Book3S HV: Don't take kvm->lock around kvm_for_each_vcpu KVM: PPC: Book3S: Use new mutex to synchronize access to rtas token list KVM: PPC: Book3S HV: Use new mutex to synchronize MMU setup KVM: PPC: Book3S HV: Avoid touching arch.mmu_ready in XIVE release functions Revert "drivers: thermal: tsens: Add new operation to check if a sensor is enabled" net/mlx5e: Disable rxhash when CQE compress is enabled net/mlx5e: restrict the real_dev of vlan device is the same as uplink device net/mlx5: Allocate root ns memory using kzalloc to match kfree net/mlx5: Avoid double free in fs init error unwinding path net/mlx5: Avoid double free of root ns in the error flow path net/mlx5: Fix error handling in mlx5_load() Documentation: net-sysfs: Remove duplicate PHY device documentation llc: fix skb leak in llc_build_and_send_ui_pkt() selftests: pmtu: Fix encapsulating device in pmtu_vti6_link_change_mtu dfs_cache: fix a wrong use of kfree in flush_cache_ent() fs/cifs/smb2pdu.c: fix buffer free in SMB2_ioctl_free cifs: fix memory leak of pneg_inbuf on -EOPNOTSUPP ioctl case xenbus: Avoid deadlock during suspend due to open transactions xen/pvcalls: Remove set but not used variable tracing: Avoid memory leak in predicate_parse() habanalabs: fix bug in checking huge page optimization mmc: sdhci: Fix SDIO IRQ thread deadlock dpaa_eth: use only online CPU portals net: mvneta: Fix err code path of probe net: stmmac: Do not output error on deferred probe Btrfs: fix race updating log root item during fsync Btrfs: fix wrong ctime and mtime of a directory after log replay ARC: [plat-hsdk] Get rid of inappropriate PHY settings ARC: [plat-hsdk]: Add support of Vivante GPU ARC: [plat-hsdk]: enable creg-gpio controller Btrfs: fix fsync not persisting changed attributes of a directory btrfs: qgroup: Check bg while resuming relocation to avoid NULL pointer dereference btrfs: reloc: Also queue orphan reloc tree for cleanup to avoid BUG_ON() Btrfs: incremental send, fix emission of invalid clone operations Btrfs: incremental send, fix file corruption when no-holes feature is enabled btrfs: correct zstd workspace manager lock to use spin_lock_bh() btrfs: Ensure replaced device doesn't have pending chunk allocation ia64: fix build errors by exporting paddr_to_nid() ASoC: SOF: Intel: hda: fix the hda init chip ASoC: SOF: ipc: fix a race, leading to IPC timeouts ASoC: SOF: control: correct the copy size for bytes kcontrol put ASoC: SOF: pcm: remove warning - initialize workqueue on open ASoC: SOF: pcm: clear hw_params_upon_resume flag correctly ASoC: SOF: core: fix error handling with the probe workqueue ASoC: SOF: core: remove snd_soc_unregister_component in case of error ASoC: SOF: core: remove DSP after unregistering machine driver ASoC: soc-core: fixup references at soc_cleanup_card_resources() arm64/module: revert to unsigned interpretation of ABS16/32 relocations KVM: s390: Do not report unusabled IDs via KVM_CAP_MAX_VCPU_ID kvm: fix compile on s390 part 2 xprtrdma: Use struct_size() in kzalloc() tools headers UAPI: Sync kvm.h headers with the kernel sources perf record: Fix s390 missing module symbol and warning for non-root users perf machine: Read also the end of the kernel perf test vmlinux-kallsyms: Ignore aliases to _etext when searching on kallsyms perf session: Add missing swap ops for namespace events perf namespace: Protect reading thread's namespace tools headers UAPI: Sync drm/drm.h with the kernel s390/crypto: fix gcm-aes-s390 selftest failures s390/zcrypt: Fix wrong dispatching for control domain CPRBs s390/pci: fix assignment of bus resources s390/pci: fix struct definition for set PCI function s390: mark __cpacf_check_opcode() and cpacf_query_func() as __always_inline s390: add unreachable() to dump_fault_info() to fix -Wmaybe-uninitialized tools headers UAPI: Sync drm/i915_drm.h with the kernel tools headers UAPI: Sync linux/fs.h with the kernel tools headers UAPI: Sync linux/sched.h with the kernel tools arch x86: Sync asm/cpufeatures.h with the with the kernel tools include UAPI: Update copy of files related to new fspick, fsmount, fsconfig, fsopen, move_mount and open_tree syscalls perf arm64: Fix mksyscalltbl when system kernel headers are ahead of the kernel perf data: Fix 'strncat may truncate' build failure with recent gcc arm64: Fix the arm64_personality() syscall wrapper redirection rtw88: Make some symbols static rtw88: avoid circular locking between local->iflist_mtx and rtwdev->mutex rsi: Properly initialize data in rsi_sdio_ta_reset rtw88: fix unassigned rssi_level in rtw_sta_info rtw88: fix subscript above array bounds compiler warning fuse: extract helper for range writeback fuse: fix copy_file_range() in the writeback case mmc: meson-gx: fix irq ack mmc: tmio: fix SCC error handling to avoid false positive CRC error mmc: tegra: Fix a warning message memstick: mspro_block: Fix an error code in mspro_block_issue_req() mac80211: mesh: fix RCU warning nl80211: fix station_info pertid memory leak mac80211: Do not use stack memory with scatterlist for GMAC ALSA: line6: Assure canceling delayed work at disconnection configfs: Fix use-after-free when accessing sd->s_dentry ALSA: hda - Force polling mode on CNL for fixing codec communication i2c: synquacer: fix synquacer_i2c_doxfer() return value i2c: mlxcpld: Fix wrong initialization order in probe i2c: dev: fix potential memory leak in i2cdev_ioctl_rdwr RDMA/core: Fix panic when port_data isn't initialized RDMA/uverbs: Pass udata on uverbs error unwind RDMA/core: Clear out the udata before error unwind net: aquantia: tcp checksum 0xffff being handled incorrectly net: aquantia: fix LRO with FCS error net: aquantia: check rx csum for all packets in LRO session net: aquantia: tx clean budget logic error vhost: scsi: add weight support vhost: vsock: add weight support vhost_net: fix possible infinite loop vhost: introduce vhost_exceeds_weight() virtio: Fix indentation of VIRTIO_MMIO virtio: add unlikely() to WARN_ON_ONCE() iommu/vt-d: Set the right field for Page Walk Snoop iommu/vt-d: Fix lock inversion between iommu->lock and device_domain_lock iommu: Add missing new line for dma type drm/etnaviv: lock MMU while dumping core block: Don't revalidate bdev of hidden gendisk loop: Don't change loop device under exclusive opener drm/imx: ipuv3-plane: fix atomic update status query for non-plus i.MX6Q drm/qxl: drop WARN_ONCE() iio: temperature: mlx90632 Relax the compatibility check iio: imu: st_lsm6dsx: fix PM support for st_lsm6dsx i2c controller staging:iio:ad7150: fix threshold mode config bit fuse: add FUSE_WRITE_KILL_PRIV fuse: fallocate: fix return with locked inode PCI: PM: Avoid possible suspend-to-idle issue ACPI: PM: Call pm_set_suspend_via_firmware() during hibernation ACPI/PCI: PM: Add missing wakeup.flags.valid checks ovl: support the FS_IOC_FS[SG]ETXATTR ioctls soundwire: stream: fix out of boundary access on port properties net: tulip: de4x5: Drop redundant MODULE_DEVICE_TABLE() selftests/tls: add test for sleeping even though there is data net/tls: fix no wakeup on partial reads selftests/tls: test for lowat overshoot with multiple records net/tls: fix lowat calculation if some data came from previous record dpaa2-eth: Make constant 64-bit long dpaa2-eth: Use PTR_ERR_OR_ZERO where appropriate dpaa2-eth: Fix potential spectre issue bonding/802.3ad: fix slave link initialization transition states io_uring: Fix __io_uring_register() false success net: ethtool: Document get_rxfh_context and set_rxfh_context ethtool ops net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail net: stmmac: fix csr_clk can't be zero issue net: stmmac: update rx tail pointer register to fix rx dma hang issue. ip_sockglue: Fix missing-check bug in ip_ra_control() ipv6_sockglue: Fix a missing-check bug in ip6_ra_control() efi: Allow the number of EFI configuration tables entries to be zero efi/x86/Add missing error handling to old_memmap 1:1 mapping code parisc: Fix compiler warnings in float emulation code parisc/slab: cleanup after /proc/slab_allocators removal bpf: sockmap, fix use after free from sleep in psock backlog workqueue net: sched: don't use tc_action->order during action dump cxgb4: Revert "cxgb4: Remove SGE_HOST_PAGE_SIZE dependency on page size" net: fec: fix the clk mismatch in failed_reset path habanalabs: Avoid using a non-initialized MMU cache mutex habanalabs: fix debugfs code uapi/habanalabs: add opcode for enable/disable device debug mode habanalabs: halt debug engines on user process close selftests: rtc: rtctest: specify timeouts selftests/harness: Allow test to configure timeout selftests/ftrace: Add checkbashisms meta-testcase selftests/ftrace: Make a script checkbashisms clean media: smsusb: better handle optional alignment test_firmware: Use correct snprintf() limit genwqe: Prevent an integer overflow in the ioctl parport: Fix mem leak in parport_register_dev_model fpga: dfl: expand minor range when registering chrdev region fpga: dfl: Add lockdep classes for pdata->lock fpga: dfl: afu: Pass the correct device to dma_mapping_error() fpga: stratix10-soc: fix use-after-free on s10_init() w1: ds2408: Fix typo after 49695ac46861 (reset on output_write retry with readback) kheaders: Do not regenerate archive if config is not changed kheaders: Move from proc to sysfs drm/amd/display: Don't load DMCU for Raven 1 (v2) drm/i915: Maintain consistent documentation subsection ordering scripts/sphinx-pre-install: make it handle Sphinx versions docs: Fix conf.py for Sphinx 2.0 vt/fbcon: deinitialize resources in visual_init() after failed memory allocation xfs: fix broken log reservation debugging clocksource/drivers/timer-ti-dm: Change to new style declaration ASoC: core: lock client_mutex while removing link components ASoC: simple-card: Restore original configuration of DAI format {nl,mac}80211: allow 4addr AP operation on crypto controlled devices mac80211_hwsim: mark expected switch fall-through mac80211: fix rate reporting inside cfg80211_calculate_bitrate_he() mac80211: remove set but not used variable 'old' mac80211: handle deauthentication/disassociation from TDLS peer gpio: fix gpio-adp5588 build errors pinctrl: stmfx: Fix compile issue when CONFIG_OF_GPIO is not defined staging: kpc2000: Add dependency on MFD_CORE to kconfig symbol 'KPC2000' perf/ring-buffer: Use regular variables for nesting perf/ring-buffer: Always use {READ,WRITE}_ONCE() for rb->user_page data perf/ring_buffer: Add ordering to rb->nest increment perf/ring_buffer: Fix exposing a temporarily decreased data_head x86/CPU/AMD: Don't force the CPB cap when running under a hypervisor x86/boot: Provide KASAN compatible aliases for string routines ALSA: hda/realtek - Enable micmute LED for Huawei laptops Input: uinput - add compat ioctl number translation for UI_*_FF_UPLOAD Input: silead - add MSSL0017 to acpi_device_id cxgb4: offload VLAN flows regardless of VLAN ethtype hsr: fix don't prune the master node from the node_db net: mvpp2: cls: Fix leaked ethtool_rx_flow_rule docs: fix multiple doc build warnings in enumeration.rst lib/list_sort: fix kerneldoc build error docs: fix numaperf.rst and add it to the doc tree doc: Cope with the deprecation of AutoReporter doc: Cope with Sphinx logging deprecations bpf: sockmap, restore sk_write_space when psock gets dropped selftests: bpf: add zero extend checks for ALU32 and/or/xor bpf, riscv: clear target register high 32-bits for and/or/xor on ALU32 spi: abort spi_sync if failed to prepare_transfer_hardware ALSA: hda/realtek - Set default power save node to 0 ipv4/igmp: fix build error if !CONFIG_IP_MULTICAST powerpc/kexec: Fix loading of kernel + initramfs with kexec_file_load() MIPS: TXx9: Fix boot crash in free_initmem() MIPS: remove a space after -I to cope with header search paths for VDSO MIPS: mark ginvt() as __always_inline ipv4/igmp: fix another memory leak in igmpv3_del_delrec() bnxt_en: Device serial number is supported only for PFs. bnxt_en: Reduce memory usage when running in kdump kernel. bnxt_en: Fix possible BUG() condition when calling pci_disable_msix(). bnxt_en: Fix aggregation buffer leak under OOM condition. ipv6: Fix redirect with VRF net: stmmac: fix reset gpio free missing mISDN: make sure device name is NUL terminated net: macb: save/restore the remaining registers and features media: dvb: warning about dvb frequency limits produces too much noise net/tls: don't ignore netdev notifications if no TLS features net/tls: fix state removal with feature flags off net/tls: avoid NULL-deref on resync during device removal Documentation: add TLS offload documentation Documentation: tls: RSTify the ktls documentation Documentation: net: move device drivers docs to a submenu mISDN: Fix indenting in dsp_cmx.c ocelot: Dont allocate another multicast list, use __dev_mc_sync Validate required parameters in inet6_validate_link_af xhci: Use %zu for printing size_t type xhci: Convert xhci_handshake() to use readl_poll_timeout_atomic() xhci: Fix immediate data transfer if buffer is already DMA mapped usb: xhci: avoid null pointer deref when bos field is NULL usb: xhci: Fix a potential null pointer dereference in xhci_debugfs_create_endpoint() xhci: update bounce buffer with correct sg num media: usb: siano: Fix false-positive "uninitialized variable" warning spi: spi-fsl-spi: call spi_finalize_current_message() at the end ALSA: hda/realtek - Check headset type by unplug and resume powerpc/perf: Fix MMCRA corruption by bhrb_filter powerpc/powernv: Return for invalid IMC domain HID: logitech-hidpp: Add support for the S510 remote control HID: multitouch: handle faulty Elo touch device selftests: netfilter: add flowtable test script netfilter: nft_flow_offload: IPCB is only valid for ipv4 family netfilter: nft_flow_offload: don't offload when sequence numbers need adjustment netfilter: nft_flow_offload: set liberal tracking mode for tcp netfilter: nf_flow_table: ignore DF bit setting ASoC: Intel: sof-rt5682: fix AMP quirk support ASoC: Intel: sof-rt5682: fix for codec button mapping clk: ti: clkctrl: Fix clkdm_clk handling clk: imx: imx8mm: fix int pll clk gate clk: sifive: restrict Kconfig scope for the FU540 PRCI driver RDMA/hns: Fix PD memory leak for internal allocation netfilter: nat: fix udp checksum corruption selftests: netfilter: missing error check when setting up veth interface RDMA/srp: Rename SRP sysfs name after IB device rename trigger ipvs: Fix use-after-free in ip_vs_in ARC: [plat-hsdk]: Add missing FIFO size entry in GMAC node ARC: [plat-hsdk]: Add missing multicast filter bins number to GMAC node samples, bpf: suppress compiler warning samples, bpf: fix to change the buffer size for read() bpf: Check sk_fullsock() before returning from bpf_sk_lookup() bpf: fix out-of-bounds read in __bpf_skc_lookup Documentation/networking: fix af_xdp.rst Sphinx warnings netfilter: nft_fib: Fix existence check support netfilter: nf_queue: fix reinject verdict handling dmaengine: sprd: Add interrupt support for 2-stage transfer dmaengine: sprd: Fix the right place to configure 2-stage transfer dmaengine: sprd: Fix block length overflow dmaengine: sprd: Fix the incorrect start for 2-stage destination channels dmaengine: sprd: Add validation of current descriptor in irq handler dmaengine: sprd: Fix the possible crash when getting descriptor status tty: max310x: Fix external crystal register setup serial: sh-sci: disable DMA for uart_console serial: imx: remove log spamming error message tty: serial: msm_serial: Fix XON/XOFF USB: serial: option: add Telit 0x1260 and 0x1261 compositions USB: serial: pl2303: add Allied Telesis VT-Kit3 USB: serial: option: add support for Simcom SIM7500/SIM7600 RNDIS mode dmaengine: tegra210-adma: Fix spelling dmaengine: tegra210-adma: Fix channel FIFO configuration dmaengine: tegra210-adma: Fix crash during probe dmaengine: mediatek-cqdma: sleeping in atomic context dmaengine: dw-axi-dmac: fix null dereference when pointer first is null perf/x86/intel/ds: Fix EVENT vs. UEVENT PEBS constraints USB: rio500: update Documentation USB: rio500: simplify locking USB: rio500: fix memory leak in close after disconnect USB: rio500: refuse more than one device at a time usbip: usbip_host: fix BUG: sleeping function called from invalid context USB: sisusbvga: fix oops in error path of sisusb_probe USB: Add LPM quirk for Surface Dock GigE adapter media: usb: siano: Fix general protection fault in smsusb usb: mtu3: fix up undefined reference to usb_debug_root USB: Fix slab-out-of-bounds write in usb_get_bos_descriptor Input: elantech - enable middle button support on 2 ThinkPads dmaengine: fsl-qdma: Add improvement dmaengine: jz4780: Fix transfers being ACKed too soon gcc-plugins: Fix build failures under Darwin host MAINTAINERS: Update Stefan Wahren email address netfilter: nf_tables: fix oops during rule dump ARC: mm: SIGSEGV userspace trying to access kernel virtual memory ARC: fix build warnings ARM: dts: bcm: Add missing device_type = "memory" property soc: bcm: brcmstb: biuctrl: Register writes require a barrier soc: brcmstb: Fix error path for unsupported CPUs ARM: dts: dra71x: Disable usb4_tm target module ARM: dts: dra71x: Disable rtc target module ARM: dts: dra76x: Disable usb4_tm target module ARM: dts: dra76x: Disable rtc target module ASoC: simple-card: Fix configuration of DAI format ASoC: Intel: soc-acpi: Fix machine selection order ASoC: rt5677-spi: Handle over reading when flipping bytes ASoC: soc-dpm: fixup DAI active unbalance pinctrl: intel: Clear interrupt status in mask/unmask callback pinctrl: intel: Use GENMASK() consistently parisc: Allow building 64-bit kernel without -mlong-calls compiler option parisc: Kconfig: remove ARCH_DISCARD_MEMBLOCK staging: wilc1000: Fix some double unlock bugs in wilc_wlan_cleanup() staging: vc04_services: prevent integer overflow in create_pagelist() Staging: vc04_services: Fix a couple error codes staging: wlan-ng: fix adapter initialization failure staging: kpc2000: double unlock in error handling in kpc_dma_transfer() staging: kpc2000: Fix build error without CONFIG_UIO staging: kpc2000: fix build error on xtensa staging: erofs: set sb->s_root to NULL when failing from __getname() ARM: imx: cpuidle-imx6sx: Restrict the SW2ISO increase to i.MX6SX firmware: imx: SCU irq should ONLY be enabled after SCU IPC is ready arm64: imx: Fix build error without CONFIG_SOC_BUS ima: fix wrong signed policy requirement when not appraising x86/ima: Check EFI_RUNTIME_SERVICES before using stacktrace: Unbreak stack_trace_save_tsk_reliable() HID: wacom: Sync INTUOSP2_BT touch state after each frame if necessary HID: wacom: Correct button numbering 2nd-gen Intuos Pro over Bluetooth HID: wacom: Send BTN_TOUCH in response to INTUOSP2_BT eraser contact HID: wacom: Don't report anything prior to the tool entering range HID: wacom: Don't set tool type until we're in range ASoC: cs42xx8: Add regcache mask dirty regulator: tps6507x: Fix boot regression due to testing wrong init_data pointer ASoC: fsl_asrc: Fix the issue about unsupported rate spi: bitbang: Fix NULL pointer dereference in spi_unregister_master Input: elan_i2c - increment wakeup count if wake source wireless: Skip directory when generating certificates ASoC: ak4458: rstn_control - return a non-zero on error only ASoC: soc-pcm: BE dai needs prepare when pause release after resume ASoC: ak4458: add return value for ak4458_probe ASoC : cs4265 : readable register too low ASoC: SOF: fix error in verbose ipc command parsing ASoC: SOF: fix race in FW boot timeout handling ASoC: SOF: nocodec: fix undefined reference iio: adc: ti-ads8688: fix timestamp is not updated in buffer iio: dac: ds4422/ds4424 fix chip verification HID: rmi: Use SET_REPORT request on control endpoint for Acer Switch 3 and 5 HID: logitech-hidpp: add support for the MX5500 keyboard HID: logitech-dj: add support for the Logitech MX5500's Bluetooth Mini-Receiver HID: i2c-hid: add iBall Aer3 to descriptor override spi: Fix Raspberry Pi breakage ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values ARM: dts: am57xx-idk: Remove support for voltage switching for SD card bus: ti-sysc: Handle devices with no control registers ARM: dts: Configure osc clock for d_can on am335x iio: imu: mpu6050: Fix FIFO layout for ICM20602 lkdtm/bugs: Adjust recursion test to avoid elision lkdtm/usercopy: Moves the KERNEL_DS test to non-canonical iio: adc: ads124: avoid buffer overflow iio: adc: modify NPCM ADC read reference voltage Change-Id: I98c823993370027391cc21dfb239c3049f025136 Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2019-06-24 20:30:20 -04:00
/* SPDX-License-Identifier: GPL-2.0-only */
msm: iommu: Use ASID tagging instead of VMID tagging Use ASID tags in the TLB instead of VMID tags in preparation for changes to the secure environment. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2011-02-24 21:00:41 -05:00
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
*/
#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
#define CTX_SHIFT 12
#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
#define GET_CTX_REG(reg, base, ctx) \
(readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg)))
#define SET_CTX_REG(reg, base, ctx, val) \
writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
/* Wrappers for numbered registers */
#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
#define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2)))
/* Field wrappers */
#define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
#define GET_CONTEXT_FIELD(b, c, r, F) \
GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
#define SET_GLOBAL_FIELD(b, r, F, v) \
SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
#define SET_CONTEXT_FIELD(b, c, r, F, v) \
SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
#define GET_FIELD(addr, mask, shift) ((readl(addr) >> (shift)) & (mask))
#define SET_FIELD(addr, mask, shift, v) \
do { \
int t = readl(addr); \
writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
} while (0)
#define NUM_FL_PTE 4096
#define NUM_SL_PTE 256
msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-11-15 21:19:35 -05:00
#define NUM_TEX_CLASS 8
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
/* First-level page table bits */
#define FL_BASE_MASK 0xFFFFFC00
#define FL_TYPE_TABLE (1 << 0)
#define FL_TYPE_SECT (2 << 0)
#define FL_SUPERSECTION (1 << 18)
#define FL_AP_WRITE (1 << 10)
#define FL_AP_READ (1 << 11)
#define FL_SHARED (1 << 16)
msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-11-15 21:19:35 -05:00
#define FL_BUFFERABLE (1 << 2)
#define FL_CACHEABLE (1 << 3)
#define FL_TEX0 (1 << 12)
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
msm: iommu: Use ASID tagging instead of VMID tagging Use ASID tags in the TLB instead of VMID tags in preparation for changes to the secure environment. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2011-02-24 21:00:41 -05:00
#define FL_NG (1 << 17)
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
/* Second-level page table bits */
#define SL_BASE_MASK_LARGE 0xFFFF0000
#define SL_BASE_MASK_SMALL 0xFFFFF000
#define SL_TYPE_LARGE (1 << 0)
#define SL_TYPE_SMALL (2 << 0)
#define SL_AP0 (1 << 4)
#define SL_AP1 (2 << 4)
#define SL_SHARED (1 << 10)
msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-11-15 21:19:35 -05:00
#define SL_BUFFERABLE (1 << 2)
#define SL_CACHEABLE (1 << 3)
#define SL_TEX0 (1 << 6)
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
msm: iommu: Use ASID tagging instead of VMID tagging Use ASID tags in the TLB instead of VMID tags in preparation for changes to the secure environment. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2011-02-24 21:00:41 -05:00
#define SL_NG (1 << 11)
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-11-15 21:19:35 -05:00
/* Memory type and cache policy attributes */
#define MT_SO 0
#define MT_DEV 1
#define MT_NORMAL 2
#define CP_NONCACHED 0
#define CP_WB_WA 1
#define CP_WT 2
#define CP_WB_NWA 3
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
/* Global register setters / getters */
#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
#define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v))
#define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v))
#define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v))
#define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v))
#define SET_TESTBUSCR(b, v) SET_GLOBAL_REG(TESTBUSCR, (b), (v))
#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
#define SET_TLBIVMID(b, v) SET_GLOBAL_REG(TLBIVMID, (b), (v))
#define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v))
#define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v))
#define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v))
#define SET_ESRRESTORE(b, v) SET_GLOBAL_REG(ESRRESTORE, (b), (v))
#define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v))
#define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v))
#define SET_RPU_ACR(b, v) SET_GLOBAL_REG(RPU_ACR, (b), (v))
#define GET_M2VCBR_N(b, N) GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
#define GET_CBACR_N(b, N) GET_GLOBAL_REG_N(CBACR_N, N, (b))
#define GET_TLBTR0(b) GET_GLOBAL_REG(TLBTR0, (b))
#define GET_TLBTR1(b) GET_GLOBAL_REG(TLBTR1, (b))
#define GET_TLBTR2(b) GET_GLOBAL_REG(TLBTR2, (b))
#define GET_TESTBUSCR(b) GET_GLOBAL_REG(TESTBUSCR, (b))
#define GET_GLOBAL_TLBIALL(b) GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
#define GET_TLBIVMID(b) GET_GLOBAL_REG(TLBIVMID, (b))
#define GET_CR(b) GET_GLOBAL_REG(CR, (b))
#define GET_EAR(b) GET_GLOBAL_REG(EAR, (b))
#define GET_ESR(b) GET_GLOBAL_REG(ESR, (b))
#define GET_ESRRESTORE(b) GET_GLOBAL_REG(ESRRESTORE, (b))
#define GET_ESYNR0(b) GET_GLOBAL_REG(ESYNR0, (b))
#define GET_ESYNR1(b) GET_GLOBAL_REG(ESYNR1, (b))
#define GET_REV(b) GET_GLOBAL_REG(REV, (b))
#define GET_IDR(b) GET_GLOBAL_REG(IDR, (b))
#define GET_RPU_ACR(b) GET_GLOBAL_REG(RPU_ACR, (b))
/* Context register setters/getters */
#define SET_SCTLR(b, c, v) SET_CTX_REG(SCTLR, (b), (c), (v))
#define SET_ACTLR(b, c, v) SET_CTX_REG(ACTLR, (b), (c), (v))
#define SET_CONTEXTIDR(b, c, v) SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
#define SET_TTBR0(b, c, v) SET_CTX_REG(TTBR0, (b), (c), (v))
#define SET_TTBR1(b, c, v) SET_CTX_REG(TTBR1, (b), (c), (v))
#define SET_TTBCR(b, c, v) SET_CTX_REG(TTBCR, (b), (c), (v))
#define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v))
#define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v))
#define SET_FSRRESTORE(b, c, v) SET_CTX_REG(FSRRESTORE, (b), (c), (v))
#define SET_FAR(b, c, v) SET_CTX_REG(FAR, (b), (c), (v))
#define SET_FSYNR0(b, c, v) SET_CTX_REG(FSYNR0, (b), (c), (v))
#define SET_FSYNR1(b, c, v) SET_CTX_REG(FSYNR1, (b), (c), (v))
#define SET_PRRR(b, c, v) SET_CTX_REG(PRRR, (b), (c), (v))
#define SET_NMRR(b, c, v) SET_CTX_REG(NMRR, (b), (c), (v))
#define SET_TLBLKCR(b, c, v) SET_CTX_REG(TLBLCKR, (b), (c), (v))
#define SET_V2PSR(b, c, v) SET_CTX_REG(V2PSR, (b), (c), (v))
#define SET_TLBFLPTER(b, c, v) SET_CTX_REG(TLBFLPTER, (b), (c), (v))
#define SET_TLBSLPTER(b, c, v) SET_CTX_REG(TLBSLPTER, (b), (c), (v))
#define SET_BFBCR(b, c, v) SET_CTX_REG(BFBCR, (b), (c), (v))
#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
#define SET_TLBIASID(b, c, v) SET_CTX_REG(TLBIASID, (b), (c), (v))
#define SET_TLBIVA(b, c, v) SET_CTX_REG(TLBIVA, (b), (c), (v))
#define SET_TLBIVAA(b, c, v) SET_CTX_REG(TLBIVAA, (b), (c), (v))
#define SET_V2PPR(b, c, v) SET_CTX_REG(V2PPR, (b), (c), (v))
#define SET_V2PPW(b, c, v) SET_CTX_REG(V2PPW, (b), (c), (v))
#define SET_V2PUR(b, c, v) SET_CTX_REG(V2PUR, (b), (c), (v))
#define SET_V2PUW(b, c, v) SET_CTX_REG(V2PUW, (b), (c), (v))
#define SET_RESUME(b, c, v) SET_CTX_REG(RESUME, (b), (c), (v))
#define GET_SCTLR(b, c) GET_CTX_REG(SCTLR, (b), (c))
#define GET_ACTLR(b, c) GET_CTX_REG(ACTLR, (b), (c))
#define GET_CONTEXTIDR(b, c) GET_CTX_REG(CONTEXTIDR, (b), (c))
#define GET_TTBR0(b, c) GET_CTX_REG(TTBR0, (b), (c))
#define GET_TTBR1(b, c) GET_CTX_REG(TTBR1, (b), (c))
#define GET_TTBCR(b, c) GET_CTX_REG(TTBCR, (b), (c))
#define GET_PAR(b, c) GET_CTX_REG(PAR, (b), (c))
#define GET_FSR(b, c) GET_CTX_REG(FSR, (b), (c))
#define GET_FSRRESTORE(b, c) GET_CTX_REG(FSRRESTORE, (b), (c))
#define GET_FAR(b, c) GET_CTX_REG(FAR, (b), (c))
#define GET_FSYNR0(b, c) GET_CTX_REG(FSYNR0, (b), (c))
#define GET_FSYNR1(b, c) GET_CTX_REG(FSYNR1, (b), (c))
#define GET_PRRR(b, c) GET_CTX_REG(PRRR, (b), (c))
#define GET_NMRR(b, c) GET_CTX_REG(NMRR, (b), (c))
#define GET_TLBLCKR(b, c) GET_CTX_REG(TLBLCKR, (b), (c))
#define GET_V2PSR(b, c) GET_CTX_REG(V2PSR, (b), (c))
#define GET_TLBFLPTER(b, c) GET_CTX_REG(TLBFLPTER, (b), (c))
#define GET_TLBSLPTER(b, c) GET_CTX_REG(TLBSLPTER, (b), (c))
#define GET_BFBCR(b, c) GET_CTX_REG(BFBCR, (b), (c))
#define GET_CTX_TLBIALL(b, c) GET_CTX_REG(CTX_TLBIALL, (b), (c))
#define GET_TLBIASID(b, c) GET_CTX_REG(TLBIASID, (b), (c))
#define GET_TLBIVA(b, c) GET_CTX_REG(TLBIVA, (b), (c))
#define GET_TLBIVAA(b, c) GET_CTX_REG(TLBIVAA, (b), (c))
#define GET_V2PPR(b, c) GET_CTX_REG(V2PPR, (b), (c))
#define GET_V2PPW(b, c) GET_CTX_REG(V2PPW, (b), (c))
#define GET_V2PUR(b, c) GET_CTX_REG(V2PUR, (b), (c))
#define GET_V2PUW(b, c) GET_CTX_REG(V2PUW, (b), (c))
#define GET_RESUME(b, c) GET_CTX_REG(RESUME, (b), (c))
/* Global field setters / getters */
/* Global Field Setters: */
/* CBACR_N */
#define SET_RWVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
#define SET_RWE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
#define SET_RWGE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
#define SET_CBVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
#define SET_IRPTNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
/* M2VCBR_N */
#define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
#define SET_CBNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
#define SET_BYPASSD(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
#define SET_BPRCOSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
#define SET_BPRCISH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
#define SET_BPRCNSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
#define SET_BPSHCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
#define SET_NSCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
#define SET_BPMTCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
#define SET_BPMEMTYPE(b, n, v) \
SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
/* CR */
#define SET_RPUE(b, v) SET_GLOBAL_FIELD(b, CR, RPUE, v)
#define SET_RPUERE(b, v) SET_GLOBAL_FIELD(b, CR, RPUERE, v)
#define SET_RPUEIE(b, v) SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
#define SET_DCDEE(b, v) SET_GLOBAL_FIELD(b, CR, DCDEE, v)
#define SET_CLIENTPD(b, v) SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
#define SET_STALLD(b, v) SET_GLOBAL_FIELD(b, CR, STALLD, v)
#define SET_TLBLKCRWE(b, v) SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
#define SET_CR_TLBIALLCFG(b, v) SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
#define SET_TLBIVMIDCFG(b, v) SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
#define SET_CR_HUME(b, v) SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
/* ESR */
#define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v)
#define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
#define SET_ESR_MULTI(b, v) SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
/* ESYNR0 */
#define SET_ESYNR0_AMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
#define SET_ESYNR0_APID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
#define SET_ESYNR0_ABID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
#define SET_ESYNR0_AVMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
#define SET_ESYNR0_ATID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
/* ESYNR1 */
#define SET_ESYNR1_AMEMTYPE(b, v) \
SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
#define SET_ESYNR1_ASHARED(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
#define SET_ESYNR1_AINNERSHARED(b, v) \
SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
#define SET_ESYNR1_APRIV(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
#define SET_ESYNR1_AINST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
#define SET_ESYNR1_AWRITE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
#define SET_ESYNR1_ABURST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
#define SET_ESYNR1_ALEN(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
#define SET_ESYNR1_ASIZE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
#define SET_ESYNR1_ALOCK(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
#define SET_ESYNR1_AOOO(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
#define SET_ESYNR1_AFULL(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
#define SET_ESYNR1_AC(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
#define SET_ESYNR1_DCD(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
/* TESTBUSCR */
#define SET_TBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
#define SET_SPDMBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
#define SET_WGSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
#define SET_TBLSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
#define SET_TBHSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
#define SET_SPDM0SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
#define SET_SPDM1SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
#define SET_SPDM2SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
#define SET_SPDM3SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
/* TLBIVMID */
#define SET_TLBIVMID_VMID(b, v) SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
/* TLBRSW */
#define SET_TLBRSW_INDEX(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
#define SET_TLBBFBS(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
/* TLBTR0 */
#define SET_PR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
#define SET_PW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
#define SET_UR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
#define SET_UW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
#define SET_XN(b, v) SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
#define SET_NSDESC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
#define SET_ISH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
#define SET_SH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
#define SET_MT(b, v) SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
#define SET_DPSIZR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
#define SET_DPSIZC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
/* TLBTR1 */
#define SET_TLBTR1_VMID(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
#define SET_TLBTR1_PA(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
/* TLBTR2 */
#define SET_TLBTR2_ASID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
#define SET_TLBTR2_V(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
#define SET_TLBTR2_NSTID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
#define SET_TLBTR2_NV(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
#define SET_TLBTR2_VA(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
/* Global Field Getters */
/* CBACR_N */
#define GET_RWVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
#define GET_RWE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
#define GET_RWGE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
#define GET_CBVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
#define GET_IRPTNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
/* M2VCBR_N */
#define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
#define GET_CBNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
#define GET_BYPASSD(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
#define GET_BPRCOSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
#define GET_BPRCISH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
#define GET_BPRCNSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
#define GET_BPSHCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
#define GET_NSCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
#define GET_BPMTCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
#define GET_BPMEMTYPE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
/* CR */
#define GET_RPUE(b) GET_GLOBAL_FIELD(b, CR, RPUE)
#define GET_RPUERE(b) GET_GLOBAL_FIELD(b, CR, RPUERE)
#define GET_RPUEIE(b) GET_GLOBAL_FIELD(b, CR, RPUEIE)
#define GET_DCDEE(b) GET_GLOBAL_FIELD(b, CR, DCDEE)
#define GET_CLIENTPD(b) GET_GLOBAL_FIELD(b, CR, CLIENTPD)
#define GET_STALLD(b) GET_GLOBAL_FIELD(b, CR, STALLD)
#define GET_TLBLKCRWE(b) GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
#define GET_CR_TLBIALLCFG(b) GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
#define GET_TLBIVMIDCFG(b) GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
#define GET_CR_HUME(b) GET_GLOBAL_FIELD(b, CR, CR_HUME)
/* ESR */
#define GET_CFG(b) GET_GLOBAL_FIELD(b, ESR, CFG)
#define GET_BYPASS(b) GET_GLOBAL_FIELD(b, ESR, BYPASS)
#define GET_ESR_MULTI(b) GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
/* ESYNR0 */
#define GET_ESYNR0_AMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
#define GET_ESYNR0_APID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
#define GET_ESYNR0_ABID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
#define GET_ESYNR0_AVMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
#define GET_ESYNR0_ATID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
/* ESYNR1 */
#define GET_ESYNR1_AMEMTYPE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
#define GET_ESYNR1_ASHARED(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
#define GET_ESYNR1_AINNERSHARED(b) \
GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
#define GET_ESYNR1_APRIV(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
#define GET_ESYNR1_APROTNS(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
#define GET_ESYNR1_AINST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
#define GET_ESYNR1_AWRITE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
#define GET_ESYNR1_ABURST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
#define GET_ESYNR1_ALEN(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
#define GET_ESYNR1_ASIZE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
#define GET_ESYNR1_ALOCK(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
#define GET_ESYNR1_AOOO(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
#define GET_ESYNR1_AFULL(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
#define GET_ESYNR1_AC(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
#define GET_ESYNR1_DCD(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
/* IDR */
#define GET_NM2VCBMT(b) GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
#define GET_HTW(b) GET_GLOBAL_FIELD(b, IDR, HTW)
#define GET_HUM(b) GET_GLOBAL_FIELD(b, IDR, HUM)
#define GET_TLBSIZE(b) GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
#define GET_NCB(b) GET_GLOBAL_FIELD(b, IDR, NCB)
#define GET_NIRPT(b) GET_GLOBAL_FIELD(b, IDR, NIRPT)
/* REV */
#define GET_MAJOR(b) GET_GLOBAL_FIELD(b, REV, MAJOR)
#define GET_MINOR(b) GET_GLOBAL_FIELD(b, REV, MINOR)
/* TESTBUSCR */
#define GET_TBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
#define GET_SPDMBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
#define GET_WGSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
#define GET_TBLSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
#define GET_TBHSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
#define GET_SPDM0SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
#define GET_SPDM1SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
#define GET_SPDM2SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
#define GET_SPDM3SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
/* TLBIVMID */
#define GET_TLBIVMID_VMID(b) GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
/* TLBTR0 */
#define GET_PR(b) GET_GLOBAL_FIELD(b, TLBTR0, PR)
#define GET_PW(b) GET_GLOBAL_FIELD(b, TLBTR0, PW)
#define GET_UR(b) GET_GLOBAL_FIELD(b, TLBTR0, UR)
#define GET_UW(b) GET_GLOBAL_FIELD(b, TLBTR0, UW)
#define GET_XN(b) GET_GLOBAL_FIELD(b, TLBTR0, XN)
#define GET_NSDESC(b) GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
#define GET_ISH(b) GET_GLOBAL_FIELD(b, TLBTR0, ISH)
#define GET_SH(b) GET_GLOBAL_FIELD(b, TLBTR0, SH)
#define GET_MT(b) GET_GLOBAL_FIELD(b, TLBTR0, MT)
#define GET_DPSIZR(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
#define GET_DPSIZC(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
/* TLBTR1 */
#define GET_TLBTR1_VMID(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
#define GET_TLBTR1_PA(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
/* TLBTR2 */
#define GET_TLBTR2_ASID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
#define GET_TLBTR2_V(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
#define GET_TLBTR2_NSTID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
#define GET_TLBTR2_NV(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
#define GET_TLBTR2_VA(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
/* Context Register setters / getters */
/* Context Register setters */
/* ACTLR */
#define SET_CFERE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
#define SET_CFEIE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
#define SET_PTSHCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
#define SET_RCOSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
#define SET_RCISH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
#define SET_RCNSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
#define SET_PRIVCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
#define SET_DNA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
#define SET_DNLV2PA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
#define SET_TLBMCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
#define SET_CFCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
#define SET_TIPCF(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
#define SET_V2PCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
#define SET_HUME(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
#define SET_PTMTCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
#define SET_PTMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
/* BFBCR */
#define SET_BFBDFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
#define SET_BFBSFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
#define SET_SFVS(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
#define SET_FLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
#define SET_SLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
/* CONTEXTIDR */
#define SET_CONTEXTIDR_ASID(b, c, v) \
SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
#define SET_CONTEXTIDR_PROCID(b, c, v) \
SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
/* FSR */
#define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v)
#define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
#define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v)
#define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
#define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
#define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
#define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
#define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v)
#define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v)
#define SET_MULTI(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
/* FSYNR0 */
#define SET_AMID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
#define SET_APID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
#define SET_ABID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
#define SET_ATID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
/* FSYNR1 */
#define SET_AMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
#define SET_ASHARED(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
#define SET_AINNERSHARED(b, c, v) \
SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
#define SET_APRIV(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
#define SET_APROTNS(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
#define SET_AINST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
#define SET_AWRITE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
#define SET_ABURST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
#define SET_ALEN(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
#define SET_FSYNR1_ASIZE(b, c, v) \
SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
#define SET_ALOCK(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
#define SET_AFULL(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
/* NMRR */
#define SET_ICPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
#define SET_ICPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
#define SET_ICPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
#define SET_ICPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
#define SET_ICPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
#define SET_ICPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
#define SET_ICPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
#define SET_ICPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
#define SET_OCPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
#define SET_OCPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
#define SET_OCPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
#define SET_OCPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
#define SET_OCPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
#define SET_OCPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
#define SET_OCPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
#define SET_OCPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
/* PAR */
#define SET_FAULT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
#define SET_FAULT_TF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
#define SET_FAULT_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
#define SET_FAULT_APF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
#define SET_FAULT_HTWDEEF(b, c, v) \
SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
#define SET_FAULT_HTWSEEF(b, c, v) \
SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
#define SET_FAULT_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
#define SET_FAULT_SL(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
#define SET_FAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
#define SET_NOFAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
#define SET_NOFAULT_MT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
#define SET_NOFAULT_SH(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
#define SET_NOFAULT_NS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
#define SET_NPFAULT_PA(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
/* PRRR */
#define SET_MTC0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
#define SET_MTC1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
#define SET_MTC2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
#define SET_MTC3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
#define SET_MTC4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
#define SET_MTC5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
#define SET_MTC6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
#define SET_MTC7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
#define SET_SHDSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
#define SET_SHDSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
#define SET_SHNMSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
#define SET_SHNMSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
#define SET_NOS0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
#define SET_NOS1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
#define SET_NOS2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
#define SET_NOS3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
#define SET_NOS4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
#define SET_NOS5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
#define SET_NOS6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
#define SET_NOS7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
/* RESUME */
#define SET_TNR(b, c, v) SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
/* SCTLR */
#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
#define SET_TRE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
#define SET_AFE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
#define SET_HAF(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
#define SET_BE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
#define SET_AFFD(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
/* TLBLKCR */
#define SET_LKE(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
#define SET_TLBIASIDCFG(b, c, v) \
SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
#define SET_FLOOR(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
#define SET_VICTIM(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
/* TTBCR */
#define SET_N(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
#define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
#define SET_PD1(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
/* TTBR0 */
#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
#define SET_TTBR0_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
#define SET_TTBR0_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
#define SET_TTBR0_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
#define SET_TTBR0_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
/* TTBR1 */
#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
#define SET_TTBR1_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
#define SET_TTBR1_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
#define SET_TTBR1_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
#define SET_TTBR1_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
/* V2PSR */
#define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
/* Context Register getters */
/* ACTLR */
#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
#define GET_CFEIE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
#define GET_PTSHCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
#define GET_RCOSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
#define GET_RCISH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
#define GET_RCNSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
#define GET_PRIVCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
#define GET_DNA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
#define GET_DNLV2PA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
#define GET_TLBMCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
#define GET_CFCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
#define GET_TIPCF(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
#define GET_V2PCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
#define GET_HUME(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
#define GET_PTMTCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
#define GET_PTMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
/* BFBCR */
#define GET_BFBDFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
#define GET_BFBSFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
#define GET_SFVS(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
#define GET_FLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
#define GET_SLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
/* CONTEXTIDR */
#define GET_CONTEXTIDR_ASID(b, c) \
GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
/* FSR */
#define GET_TF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TF)
#define GET_AFF(b, c) GET_CONTEXT_FIELD(b, c, FSR, AFF)
#define GET_APF(b, c) GET_CONTEXT_FIELD(b, c, FSR, APF)
#define GET_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
#define GET_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
#define GET_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
#define GET_MHF(b, c) GET_CONTEXT_FIELD(b, c, FSR, MHF)
#define GET_SL(b, c) GET_CONTEXT_FIELD(b, c, FSR, SL)
#define GET_SS(b, c) GET_CONTEXT_FIELD(b, c, FSR, SS)
#define GET_MULTI(b, c) GET_CONTEXT_FIELD(b, c, FSR, MULTI)
/* FSYNR0 */
#define GET_AMID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
#define GET_APID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
#define GET_ABID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
#define GET_ATID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
/* FSYNR1 */
#define GET_AMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
#define GET_ASHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
#define GET_AINNERSHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
#define GET_APRIV(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
#define GET_APROTNS(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
#define GET_AINST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
#define GET_AWRITE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
#define GET_ABURST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
#define GET_ALEN(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
#define GET_FSYNR1_ASIZE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
#define GET_ALOCK(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
#define GET_AFULL(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
/* NMRR */
#define GET_ICPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
#define GET_ICPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
#define GET_ICPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
#define GET_ICPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
#define GET_ICPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
#define GET_ICPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
#define GET_ICPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
#define GET_ICPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
#define GET_OCPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
#define GET_OCPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
#define GET_OCPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
#define GET_OCPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
#define GET_OCPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
#define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
#define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
#define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-11-15 21:19:35 -05:00
#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2))
#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \
((n) * 2 + 16))
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
/* PAR */
#define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT)
#define GET_FAULT_TF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
#define GET_FAULT_AFF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
#define GET_FAULT_APF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
#define GET_FAULT_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
#define GET_FAULT_MHF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
#define GET_FAULT_SL(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
#define GET_FAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
#define GET_NOFAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
#define GET_NOFAULT_MT(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
#define GET_NOFAULT_SH(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
#define GET_NOFAULT_NS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
#define GET_NOFAULT_NOS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
#define GET_NPFAULT_PA(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
/* PRRR */
#define GET_MTC0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
#define GET_MTC1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
#define GET_MTC2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
#define GET_MTC3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
#define GET_MTC4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
#define GET_MTC5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
#define GET_MTC6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
#define GET_MTC7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
#define GET_SHDSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
#define GET_SHDSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
#define GET_SHNMSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
#define GET_SHNMSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
#define GET_NOS0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
#define GET_NOS1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
#define GET_NOS2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
#define GET_NOS3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
#define GET_NOS4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
#define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
#define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
#define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-11-15 21:19:35 -05:00
#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0)
#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2)))
msm: Add MSM IOMMU support Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
2010-08-24 21:31:10 -04:00
/* RESUME */
#define GET_TNR(b, c) GET_CONTEXT_FIELD(b, c, RESUME, TNR)
/* SCTLR */
#define GET_M(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, M)
#define GET_TRE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
#define GET_AFE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
#define GET_HAF(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
#define GET_BE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, BE)
#define GET_AFFD(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
/* TLBLKCR */
#define GET_LKE(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
#define GET_TLBLCKR_TLBIALLCFG(b, c) \
GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
#define GET_TLBIASIDCFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
#define GET_TLBIVAACFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
#define GET_FLOOR(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
#define GET_VICTIM(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
/* TTBCR */
#define GET_N(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, N)
#define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
#define GET_PD1(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
/* TTBR0 */
#define GET_TTBR0_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
#define GET_TTBR0_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
#define GET_TTBR0_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
#define GET_TTBR0_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
#define GET_TTBR0_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
#define GET_TTBR0_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
/* TTBR1 */
#define GET_TTBR1_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
#define GET_TTBR1_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
#define GET_TTBR1_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
#define GET_TTBR1_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
#define GET_TTBR1_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
#define GET_TTBR1_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
/* V2PSR */
#define GET_HIT(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
/* Global Registers */
#define M2VCBR_N (0xFF000)
#define CBACR_N (0xFF800)
#define TLBRSW (0xFFE00)
#define TLBTR0 (0xFFE80)
#define TLBTR1 (0xFFE84)
#define TLBTR2 (0xFFE88)
#define TESTBUSCR (0xFFE8C)
#define GLOBAL_TLBIALL (0xFFF00)
#define TLBIVMID (0xFFF04)
#define CR (0xFFF80)
#define EAR (0xFFF84)
#define ESR (0xFFF88)
#define ESRRESTORE (0xFFF8C)
#define ESYNR0 (0xFFF90)
#define ESYNR1 (0xFFF94)
#define REV (0xFFFF4)
#define IDR (0xFFFF8)
#define RPU_ACR (0xFFFFC)
/* Context Bank Registers */
#define SCTLR (0x000)
#define ACTLR (0x004)
#define CONTEXTIDR (0x008)
#define TTBR0 (0x010)
#define TTBR1 (0x014)
#define TTBCR (0x018)
#define PAR (0x01C)
#define FSR (0x020)
#define FSRRESTORE (0x024)
#define FAR (0x028)
#define FSYNR0 (0x02C)
#define FSYNR1 (0x030)
#define PRRR (0x034)
#define NMRR (0x038)
#define TLBLCKR (0x03C)
#define V2PSR (0x040)
#define TLBFLPTER (0x044)
#define TLBSLPTER (0x048)
#define BFBCR (0x04C)
#define CTX_TLBIALL (0x800)
#define TLBIASID (0x804)
#define TLBIVA (0x808)
#define TLBIVAA (0x80C)
#define V2PPR (0x810)
#define V2PPW (0x814)
#define V2PUR (0x818)
#define V2PUW (0x81C)
#define RESUME (0x820)
/* Global Register Fields */
/* CBACRn */
#define RWVMID (RWVMID_MASK << RWVMID_SHIFT)
#define RWE (RWE_MASK << RWE_SHIFT)
#define RWGE (RWGE_MASK << RWGE_SHIFT)
#define CBVMID (CBVMID_MASK << CBVMID_SHIFT)
#define IRPTNDX (IRPTNDX_MASK << IRPTNDX_SHIFT)
/* CR */
#define RPUE (RPUE_MASK << RPUE_SHIFT)
#define RPUERE (RPUERE_MASK << RPUERE_SHIFT)
#define RPUEIE (RPUEIE_MASK << RPUEIE_SHIFT)
#define DCDEE (DCDEE_MASK << DCDEE_SHIFT)
#define CLIENTPD (CLIENTPD_MASK << CLIENTPD_SHIFT)
#define STALLD (STALLD_MASK << STALLD_SHIFT)
#define TLBLKCRWE (TLBLKCRWE_MASK << TLBLKCRWE_SHIFT)
#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
#define TLBIVMIDCFG (TLBIVMIDCFG_MASK << TLBIVMIDCFG_SHIFT)
#define CR_HUME (CR_HUME_MASK << CR_HUME_SHIFT)
/* ESR */
#define CFG (CFG_MASK << CFG_SHIFT)
#define BYPASS (BYPASS_MASK << BYPASS_SHIFT)
#define ESR_MULTI (ESR_MULTI_MASK << ESR_MULTI_SHIFT)
/* ESYNR0 */
#define ESYNR0_AMID (ESYNR0_AMID_MASK << ESYNR0_AMID_SHIFT)
#define ESYNR0_APID (ESYNR0_APID_MASK << ESYNR0_APID_SHIFT)
#define ESYNR0_ABID (ESYNR0_ABID_MASK << ESYNR0_ABID_SHIFT)
#define ESYNR0_AVMID (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
#define ESYNR0_ATID (ESYNR0_ATID_MASK << ESYNR0_ATID_SHIFT)
/* ESYNR1 */
#define ESYNR1_AMEMTYPE (ESYNR1_AMEMTYPE_MASK << ESYNR1_AMEMTYPE_SHIFT)
#define ESYNR1_ASHARED (ESYNR1_ASHARED_MASK << ESYNR1_ASHARED_SHIFT)
#define ESYNR1_AINNERSHARED (ESYNR1_AINNERSHARED_MASK<< \
ESYNR1_AINNERSHARED_SHIFT)
#define ESYNR1_APRIV (ESYNR1_APRIV_MASK << ESYNR1_APRIV_SHIFT)
#define ESYNR1_APROTNS (ESYNR1_APROTNS_MASK << ESYNR1_APROTNS_SHIFT)
#define ESYNR1_AINST (ESYNR1_AINST_MASK << ESYNR1_AINST_SHIFT)
#define ESYNR1_AWRITE (ESYNR1_AWRITE_MASK << ESYNR1_AWRITE_SHIFT)
#define ESYNR1_ABURST (ESYNR1_ABURST_MASK << ESYNR1_ABURST_SHIFT)
#define ESYNR1_ALEN (ESYNR1_ALEN_MASK << ESYNR1_ALEN_SHIFT)
#define ESYNR1_ASIZE (ESYNR1_ASIZE_MASK << ESYNR1_ASIZE_SHIFT)
#define ESYNR1_ALOCK (ESYNR1_ALOCK_MASK << ESYNR1_ALOCK_SHIFT)
#define ESYNR1_AOOO (ESYNR1_AOOO_MASK << ESYNR1_AOOO_SHIFT)
#define ESYNR1_AFULL (ESYNR1_AFULL_MASK << ESYNR1_AFULL_SHIFT)
#define ESYNR1_AC (ESYNR1_AC_MASK << ESYNR1_AC_SHIFT)
#define ESYNR1_DCD (ESYNR1_DCD_MASK << ESYNR1_DCD_SHIFT)
/* IDR */
#define NM2VCBMT (NM2VCBMT_MASK << NM2VCBMT_SHIFT)
#define HTW (HTW_MASK << HTW_SHIFT)
#define HUM (HUM_MASK << HUM_SHIFT)
#define TLBSIZE (TLBSIZE_MASK << TLBSIZE_SHIFT)
#define NCB (NCB_MASK << NCB_SHIFT)
#define NIRPT (NIRPT_MASK << NIRPT_SHIFT)
/* M2VCBRn */
#define VMID (VMID_MASK << VMID_SHIFT)
#define CBNDX (CBNDX_MASK << CBNDX_SHIFT)
#define BYPASSD (BYPASSD_MASK << BYPASSD_SHIFT)
#define BPRCOSH (BPRCOSH_MASK << BPRCOSH_SHIFT)
#define BPRCISH (BPRCISH_MASK << BPRCISH_SHIFT)
#define BPRCNSH (BPRCNSH_MASK << BPRCNSH_SHIFT)
#define BPSHCFG (BPSHCFG_MASK << BPSHCFG_SHIFT)
#define NSCFG (NSCFG_MASK << NSCFG_SHIFT)
#define BPMTCFG (BPMTCFG_MASK << BPMTCFG_SHIFT)
#define BPMEMTYPE (BPMEMTYPE_MASK << BPMEMTYPE_SHIFT)
/* REV */
#define IDR_MINOR (MINOR_MASK << MINOR_SHIFT)
#define IDR_MAJOR (MAJOR_MASK << MAJOR_SHIFT)
/* TESTBUSCR */
#define TBE (TBE_MASK << TBE_SHIFT)
#define SPDMBE (SPDMBE_MASK << SPDMBE_SHIFT)
#define WGSEL (WGSEL_MASK << WGSEL_SHIFT)
#define TBLSEL (TBLSEL_MASK << TBLSEL_SHIFT)
#define TBHSEL (TBHSEL_MASK << TBHSEL_SHIFT)
#define SPDM0SEL (SPDM0SEL_MASK << SPDM0SEL_SHIFT)
#define SPDM1SEL (SPDM1SEL_MASK << SPDM1SEL_SHIFT)
#define SPDM2SEL (SPDM2SEL_MASK << SPDM2SEL_SHIFT)
#define SPDM3SEL (SPDM3SEL_MASK << SPDM3SEL_SHIFT)
/* TLBIVMID */
#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
/* TLBRSW */
#define TLBRSW_INDEX (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
#define TLBBFBS (TLBBFBS_MASK << TLBBFBS_SHIFT)
/* TLBTR0 */
#define PR (PR_MASK << PR_SHIFT)
#define PW (PW_MASK << PW_SHIFT)
#define UR (UR_MASK << UR_SHIFT)
#define UW (UW_MASK << UW_SHIFT)
#define XN (XN_MASK << XN_SHIFT)
#define NSDESC (NSDESC_MASK << NSDESC_SHIFT)
#define ISH (ISH_MASK << ISH_SHIFT)
#define SH (SH_MASK << SH_SHIFT)
#define MT (MT_MASK << MT_SHIFT)
#define DPSIZR (DPSIZR_MASK << DPSIZR_SHIFT)
#define DPSIZC (DPSIZC_MASK << DPSIZC_SHIFT)
/* TLBTR1 */
#define TLBTR1_VMID (TLBTR1_VMID_MASK << TLBTR1_VMID_SHIFT)
#define TLBTR1_PA (TLBTR1_PA_MASK << TLBTR1_PA_SHIFT)
/* TLBTR2 */
#define TLBTR2_ASID (TLBTR2_ASID_MASK << TLBTR2_ASID_SHIFT)
#define TLBTR2_V (TLBTR2_V_MASK << TLBTR2_V_SHIFT)
#define TLBTR2_NSTID (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
#define TLBTR2_NV (TLBTR2_NV_MASK << TLBTR2_NV_SHIFT)
#define TLBTR2_VA (TLBTR2_VA_MASK << TLBTR2_VA_SHIFT)
/* Context Register Fields */
/* ACTLR */
#define CFERE (CFERE_MASK << CFERE_SHIFT)
#define CFEIE (CFEIE_MASK << CFEIE_SHIFT)
#define PTSHCFG (PTSHCFG_MASK << PTSHCFG_SHIFT)
#define RCOSH (RCOSH_MASK << RCOSH_SHIFT)
#define RCISH (RCISH_MASK << RCISH_SHIFT)
#define RCNSH (RCNSH_MASK << RCNSH_SHIFT)
#define PRIVCFG (PRIVCFG_MASK << PRIVCFG_SHIFT)
#define DNA (DNA_MASK << DNA_SHIFT)
#define DNLV2PA (DNLV2PA_MASK << DNLV2PA_SHIFT)
#define TLBMCFG (TLBMCFG_MASK << TLBMCFG_SHIFT)
#define CFCFG (CFCFG_MASK << CFCFG_SHIFT)
#define TIPCF (TIPCF_MASK << TIPCF_SHIFT)
#define V2PCFG (V2PCFG_MASK << V2PCFG_SHIFT)
#define HUME (HUME_MASK << HUME_SHIFT)
#define PTMTCFG (PTMTCFG_MASK << PTMTCFG_SHIFT)
#define PTMEMTYPE (PTMEMTYPE_MASK << PTMEMTYPE_SHIFT)
/* BFBCR */
#define BFBDFE (BFBDFE_MASK << BFBDFE_SHIFT)
#define BFBSFE (BFBSFE_MASK << BFBSFE_SHIFT)
#define SFVS (SFVS_MASK << SFVS_SHIFT)
#define FLVIC (FLVIC_MASK << FLVIC_SHIFT)
#define SLVIC (SLVIC_MASK << SLVIC_SHIFT)
/* CONTEXTIDR */
#define CONTEXTIDR_ASID (CONTEXTIDR_ASID_MASK << CONTEXTIDR_ASID_SHIFT)
#define PROCID (PROCID_MASK << PROCID_SHIFT)
/* FSR */
#define TF (TF_MASK << TF_SHIFT)
#define AFF (AFF_MASK << AFF_SHIFT)
#define APF (APF_MASK << APF_SHIFT)
#define TLBMF (TLBMF_MASK << TLBMF_SHIFT)
#define HTWDEEF (HTWDEEF_MASK << HTWDEEF_SHIFT)
#define HTWSEEF (HTWSEEF_MASK << HTWSEEF_SHIFT)
#define MHF (MHF_MASK << MHF_SHIFT)
#define SL (SL_MASK << SL_SHIFT)
#define SS (SS_MASK << SS_SHIFT)
#define MULTI (MULTI_MASK << MULTI_SHIFT)
/* FSYNR0 */
#define AMID (AMID_MASK << AMID_SHIFT)
#define APID (APID_MASK << APID_SHIFT)
#define ABID (ABID_MASK << ABID_SHIFT)
#define ATID (ATID_MASK << ATID_SHIFT)
/* FSYNR1 */
#define AMEMTYPE (AMEMTYPE_MASK << AMEMTYPE_SHIFT)
#define ASHARED (ASHARED_MASK << ASHARED_SHIFT)
#define AINNERSHARED (AINNERSHARED_MASK << AINNERSHARED_SHIFT)
#define APRIV (APRIV_MASK << APRIV_SHIFT)
#define APROTNS (APROTNS_MASK << APROTNS_SHIFT)
#define AINST (AINST_MASK << AINST_SHIFT)
#define AWRITE (AWRITE_MASK << AWRITE_SHIFT)
#define ABURST (ABURST_MASK << ABURST_SHIFT)
#define ALEN (ALEN_MASK << ALEN_SHIFT)
#define FSYNR1_ASIZE (FSYNR1_ASIZE_MASK << FSYNR1_ASIZE_SHIFT)
#define ALOCK (ALOCK_MASK << ALOCK_SHIFT)
#define AFULL (AFULL_MASK << AFULL_SHIFT)
/* NMRR */
#define ICPC0 (ICPC0_MASK << ICPC0_SHIFT)
#define ICPC1 (ICPC1_MASK << ICPC1_SHIFT)
#define ICPC2 (ICPC2_MASK << ICPC2_SHIFT)
#define ICPC3 (ICPC3_MASK << ICPC3_SHIFT)
#define ICPC4 (ICPC4_MASK << ICPC4_SHIFT)
#define ICPC5 (ICPC5_MASK << ICPC5_SHIFT)
#define ICPC6 (ICPC6_MASK << ICPC6_SHIFT)
#define ICPC7 (ICPC7_MASK << ICPC7_SHIFT)
#define OCPC0 (OCPC0_MASK << OCPC0_SHIFT)
#define OCPC1 (OCPC1_MASK << OCPC1_SHIFT)
#define OCPC2 (OCPC2_MASK << OCPC2_SHIFT)
#define OCPC3 (OCPC3_MASK << OCPC3_SHIFT)
#define OCPC4 (OCPC4_MASK << OCPC4_SHIFT)
#define OCPC5 (OCPC5_MASK << OCPC5_SHIFT)
#define OCPC6 (OCPC6_MASK << OCPC6_SHIFT)
#define OCPC7 (OCPC7_MASK << OCPC7_SHIFT)
/* PAR */
#define FAULT (FAULT_MASK << FAULT_SHIFT)
/* If a fault is present, these are the
same as the fault fields in the FAR */
#define FAULT_TF (FAULT_TF_MASK << FAULT_TF_SHIFT)
#define FAULT_AFF (FAULT_AFF_MASK << FAULT_AFF_SHIFT)
#define FAULT_APF (FAULT_APF_MASK << FAULT_APF_SHIFT)
#define FAULT_TLBMF (FAULT_TLBMF_MASK << FAULT_TLBMF_SHIFT)
#define FAULT_HTWDEEF (FAULT_HTWDEEF_MASK << FAULT_HTWDEEF_SHIFT)
#define FAULT_HTWSEEF (FAULT_HTWSEEF_MASK << FAULT_HTWSEEF_SHIFT)
#define FAULT_MHF (FAULT_MHF_MASK << FAULT_MHF_SHIFT)
#define FAULT_SL (FAULT_SL_MASK << FAULT_SL_SHIFT)
#define FAULT_SS (FAULT_SS_MASK << FAULT_SS_SHIFT)
/* If NO fault is present, the following fields are in effect */
/* (FAULT remains as before) */
#define PAR_NOFAULT_SS (PAR_NOFAULT_SS_MASK << PAR_NOFAULT_SS_SHIFT)
#define PAR_NOFAULT_MT (PAR_NOFAULT_MT_MASK << PAR_NOFAULT_MT_SHIFT)
#define PAR_NOFAULT_SH (PAR_NOFAULT_SH_MASK << PAR_NOFAULT_SH_SHIFT)
#define PAR_NOFAULT_NS (PAR_NOFAULT_NS_MASK << PAR_NOFAULT_NS_SHIFT)
#define PAR_NOFAULT_NOS (PAR_NOFAULT_NOS_MASK << PAR_NOFAULT_NOS_SHIFT)
#define PAR_NPFAULT_PA (PAR_NPFAULT_PA_MASK << PAR_NPFAULT_PA_SHIFT)
/* PRRR */
#define MTC0 (MTC0_MASK << MTC0_SHIFT)
#define MTC1 (MTC1_MASK << MTC1_SHIFT)
#define MTC2 (MTC2_MASK << MTC2_SHIFT)
#define MTC3 (MTC3_MASK << MTC3_SHIFT)
#define MTC4 (MTC4_MASK << MTC4_SHIFT)
#define MTC5 (MTC5_MASK << MTC5_SHIFT)
#define MTC6 (MTC6_MASK << MTC6_SHIFT)
#define MTC7 (MTC7_MASK << MTC7_SHIFT)
#define SHDSH0 (SHDSH0_MASK << SHDSH0_SHIFT)
#define SHDSH1 (SHDSH1_MASK << SHDSH1_SHIFT)
#define SHNMSH0 (SHNMSH0_MASK << SHNMSH0_SHIFT)
#define SHNMSH1 (SHNMSH1_MASK << SHNMSH1_SHIFT)
#define NOS0 (NOS0_MASK << NOS0_SHIFT)
#define NOS1 (NOS1_MASK << NOS1_SHIFT)
#define NOS2 (NOS2_MASK << NOS2_SHIFT)
#define NOS3 (NOS3_MASK << NOS3_SHIFT)
#define NOS4 (NOS4_MASK << NOS4_SHIFT)
#define NOS5 (NOS5_MASK << NOS5_SHIFT)
#define NOS6 (NOS6_MASK << NOS6_SHIFT)
#define NOS7 (NOS7_MASK << NOS7_SHIFT)
/* RESUME */
#define TNR (TNR_MASK << TNR_SHIFT)
/* SCTLR */
#define M (M_MASK << M_SHIFT)
#define TRE (TRE_MASK << TRE_SHIFT)
#define AFE (AFE_MASK << AFE_SHIFT)
#define HAF (HAF_MASK << HAF_SHIFT)
#define BE (BE_MASK << BE_SHIFT)
#define AFFD (AFFD_MASK << AFFD_SHIFT)
/* TLBIASID */
#define TLBIASID_ASID (TLBIASID_ASID_MASK << TLBIASID_ASID_SHIFT)
/* TLBIVA */
#define TLBIVA_ASID (TLBIVA_ASID_MASK << TLBIVA_ASID_SHIFT)
#define TLBIVA_VA (TLBIVA_VA_MASK << TLBIVA_VA_SHIFT)
/* TLBIVAA */
#define TLBIVAA_VA (TLBIVAA_VA_MASK << TLBIVAA_VA_SHIFT)
/* TLBLCKR */
#define LKE (LKE_MASK << LKE_SHIFT)
#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
#define TLBIASIDCFG (TLBIASIDCFG_MASK << TLBIASIDCFG_SHIFT)
#define TLBIVAACFG (TLBIVAACFG_MASK << TLBIVAACFG_SHIFT)
#define FLOOR (FLOOR_MASK << FLOOR_SHIFT)
#define VICTIM (VICTIM_MASK << VICTIM_SHIFT)
/* TTBCR */
#define N (N_MASK << N_SHIFT)
#define PD0 (PD0_MASK << PD0_SHIFT)
#define PD1 (PD1_MASK << PD1_SHIFT)
/* TTBR0 */
#define TTBR0_IRGNH (TTBR0_IRGNH_MASK << TTBR0_IRGNH_SHIFT)
#define TTBR0_SH (TTBR0_SH_MASK << TTBR0_SH_SHIFT)
#define TTBR0_ORGN (TTBR0_ORGN_MASK << TTBR0_ORGN_SHIFT)
#define TTBR0_NOS (TTBR0_NOS_MASK << TTBR0_NOS_SHIFT)
#define TTBR0_IRGNL (TTBR0_IRGNL_MASK << TTBR0_IRGNL_SHIFT)
#define TTBR0_PA (TTBR0_PA_MASK << TTBR0_PA_SHIFT)
/* TTBR1 */
#define TTBR1_IRGNH (TTBR1_IRGNH_MASK << TTBR1_IRGNH_SHIFT)
#define TTBR1_SH (TTBR1_SH_MASK << TTBR1_SH_SHIFT)
#define TTBR1_ORGN (TTBR1_ORGN_MASK << TTBR1_ORGN_SHIFT)
#define TTBR1_NOS (TTBR1_NOS_MASK << TTBR1_NOS_SHIFT)
#define TTBR1_IRGNL (TTBR1_IRGNL_MASK << TTBR1_IRGNL_SHIFT)
#define TTBR1_PA (TTBR1_PA_MASK << TTBR1_PA_SHIFT)
/* V2PSR */
#define HIT (HIT_MASK << HIT_SHIFT)
#define INDEX (INDEX_MASK << INDEX_SHIFT)
/* V2Pxx */
#define V2Pxx_INDEX (V2Pxx_INDEX_MASK << V2Pxx_INDEX_SHIFT)
#define V2Pxx_VA (V2Pxx_VA_MASK << V2Pxx_VA_SHIFT)
/* Global Register Masks */
/* CBACRn */
#define RWVMID_MASK 0x1F
#define RWE_MASK 0x01
#define RWGE_MASK 0x01
#define CBVMID_MASK 0x1F
#define IRPTNDX_MASK 0xFF
/* CR */
#define RPUE_MASK 0x01
#define RPUERE_MASK 0x01
#define RPUEIE_MASK 0x01
#define DCDEE_MASK 0x01
#define CLIENTPD_MASK 0x01
#define STALLD_MASK 0x01
#define TLBLKCRWE_MASK 0x01
#define CR_TLBIALLCFG_MASK 0x01
#define TLBIVMIDCFG_MASK 0x01
#define CR_HUME_MASK 0x01
/* ESR */
#define CFG_MASK 0x01
#define BYPASS_MASK 0x01
#define ESR_MULTI_MASK 0x01
/* ESYNR0 */
#define ESYNR0_AMID_MASK 0xFF
#define ESYNR0_APID_MASK 0x1F
#define ESYNR0_ABID_MASK 0x07
#define ESYNR0_AVMID_MASK 0x1F
#define ESYNR0_ATID_MASK 0xFF
/* ESYNR1 */
#define ESYNR1_AMEMTYPE_MASK 0x07
#define ESYNR1_ASHARED_MASK 0x01
#define ESYNR1_AINNERSHARED_MASK 0x01
#define ESYNR1_APRIV_MASK 0x01
#define ESYNR1_APROTNS_MASK 0x01
#define ESYNR1_AINST_MASK 0x01
#define ESYNR1_AWRITE_MASK 0x01
#define ESYNR1_ABURST_MASK 0x01
#define ESYNR1_ALEN_MASK 0x0F
#define ESYNR1_ASIZE_MASK 0x01
#define ESYNR1_ALOCK_MASK 0x03
#define ESYNR1_AOOO_MASK 0x01
#define ESYNR1_AFULL_MASK 0x01
#define ESYNR1_AC_MASK 0x01
#define ESYNR1_DCD_MASK 0x01
/* IDR */
#define NM2VCBMT_MASK 0x1FF
#define HTW_MASK 0x01
#define HUM_MASK 0x01
#define TLBSIZE_MASK 0x0F
#define NCB_MASK 0xFF
#define NIRPT_MASK 0xFF
/* M2VCBRn */
#define VMID_MASK 0x1F
#define CBNDX_MASK 0xFF
#define BYPASSD_MASK 0x01
#define BPRCOSH_MASK 0x01
#define BPRCISH_MASK 0x01
#define BPRCNSH_MASK 0x01
#define BPSHCFG_MASK 0x03
#define NSCFG_MASK 0x03
#define BPMTCFG_MASK 0x01
#define BPMEMTYPE_MASK 0x07
/* REV */
#define MINOR_MASK 0x0F
#define MAJOR_MASK 0x0F
/* TESTBUSCR */
#define TBE_MASK 0x01
#define SPDMBE_MASK 0x01
#define WGSEL_MASK 0x03
#define TBLSEL_MASK 0x03
#define TBHSEL_MASK 0x03
#define SPDM0SEL_MASK 0x0F
#define SPDM1SEL_MASK 0x0F
#define SPDM2SEL_MASK 0x0F
#define SPDM3SEL_MASK 0x0F
/* TLBIMID */
#define TLBIVMID_VMID_MASK 0x1F
/* TLBRSW */
#define TLBRSW_INDEX_MASK 0xFF
#define TLBBFBS_MASK 0x03
/* TLBTR0 */
#define PR_MASK 0x01
#define PW_MASK 0x01
#define UR_MASK 0x01
#define UW_MASK 0x01
#define XN_MASK 0x01
#define NSDESC_MASK 0x01
#define ISH_MASK 0x01
#define SH_MASK 0x01
#define MT_MASK 0x07
#define DPSIZR_MASK 0x07
#define DPSIZC_MASK 0x07
/* TLBTR1 */
#define TLBTR1_VMID_MASK 0x1F
#define TLBTR1_PA_MASK 0x000FFFFF
/* TLBTR2 */
#define TLBTR2_ASID_MASK 0xFF
#define TLBTR2_V_MASK 0x01
#define TLBTR2_NSTID_MASK 0x01
#define TLBTR2_NV_MASK 0x01
#define TLBTR2_VA_MASK 0x000FFFFF
/* Global Register Shifts */
/* CBACRn */
#define RWVMID_SHIFT 0
#define RWE_SHIFT 8
#define RWGE_SHIFT 9
#define CBVMID_SHIFT 16
#define IRPTNDX_SHIFT 24
/* CR */
#define RPUE_SHIFT 0
#define RPUERE_SHIFT 1
#define RPUEIE_SHIFT 2
#define DCDEE_SHIFT 3
#define CLIENTPD_SHIFT 4
#define STALLD_SHIFT 5
#define TLBLKCRWE_SHIFT 6
#define CR_TLBIALLCFG_SHIFT 7
#define TLBIVMIDCFG_SHIFT 8
#define CR_HUME_SHIFT 9
/* ESR */
#define CFG_SHIFT 0
#define BYPASS_SHIFT 1
#define ESR_MULTI_SHIFT 31
/* ESYNR0 */
#define ESYNR0_AMID_SHIFT 0
#define ESYNR0_APID_SHIFT 8
#define ESYNR0_ABID_SHIFT 13
#define ESYNR0_AVMID_SHIFT 16
#define ESYNR0_ATID_SHIFT 24
/* ESYNR1 */
#define ESYNR1_AMEMTYPE_SHIFT 0
#define ESYNR1_ASHARED_SHIFT 3
#define ESYNR1_AINNERSHARED_SHIFT 4
#define ESYNR1_APRIV_SHIFT 5
#define ESYNR1_APROTNS_SHIFT 6
#define ESYNR1_AINST_SHIFT 7
#define ESYNR1_AWRITE_SHIFT 8
#define ESYNR1_ABURST_SHIFT 10
#define ESYNR1_ALEN_SHIFT 12
#define ESYNR1_ASIZE_SHIFT 16
#define ESYNR1_ALOCK_SHIFT 20
#define ESYNR1_AOOO_SHIFT 22
#define ESYNR1_AFULL_SHIFT 24
#define ESYNR1_AC_SHIFT 30
#define ESYNR1_DCD_SHIFT 31
/* IDR */
#define NM2VCBMT_SHIFT 0
#define HTW_SHIFT 9
#define HUM_SHIFT 10
#define TLBSIZE_SHIFT 12
#define NCB_SHIFT 16
#define NIRPT_SHIFT 24
/* M2VCBRn */
#define VMID_SHIFT 0
#define CBNDX_SHIFT 8
#define BYPASSD_SHIFT 16
#define BPRCOSH_SHIFT 17
#define BPRCISH_SHIFT 18
#define BPRCNSH_SHIFT 19
#define BPSHCFG_SHIFT 20
#define NSCFG_SHIFT 22
#define BPMTCFG_SHIFT 24
#define BPMEMTYPE_SHIFT 25
/* REV */
#define MINOR_SHIFT 0
#define MAJOR_SHIFT 4
/* TESTBUSCR */
#define TBE_SHIFT 0
#define SPDMBE_SHIFT 1
#define WGSEL_SHIFT 8
#define TBLSEL_SHIFT 12
#define TBHSEL_SHIFT 14
#define SPDM0SEL_SHIFT 16
#define SPDM1SEL_SHIFT 20
#define SPDM2SEL_SHIFT 24
#define SPDM3SEL_SHIFT 28
/* TLBIMID */
#define TLBIVMID_VMID_SHIFT 0
/* TLBRSW */
#define TLBRSW_INDEX_SHIFT 0
#define TLBBFBS_SHIFT 8
/* TLBTR0 */
#define PR_SHIFT 0
#define PW_SHIFT 1
#define UR_SHIFT 2
#define UW_SHIFT 3
#define XN_SHIFT 4
#define NSDESC_SHIFT 6
#define ISH_SHIFT 7
#define SH_SHIFT 8
#define MT_SHIFT 9
#define DPSIZR_SHIFT 16
#define DPSIZC_SHIFT 20
/* TLBTR1 */
#define TLBTR1_VMID_SHIFT 0
#define TLBTR1_PA_SHIFT 12
/* TLBTR2 */
#define TLBTR2_ASID_SHIFT 0
#define TLBTR2_V_SHIFT 8
#define TLBTR2_NSTID_SHIFT 9
#define TLBTR2_NV_SHIFT 10
#define TLBTR2_VA_SHIFT 12
/* Context Register Masks */
/* ACTLR */
#define CFERE_MASK 0x01
#define CFEIE_MASK 0x01
#define PTSHCFG_MASK 0x03
#define RCOSH_MASK 0x01
#define RCISH_MASK 0x01
#define RCNSH_MASK 0x01
#define PRIVCFG_MASK 0x03
#define DNA_MASK 0x01
#define DNLV2PA_MASK 0x01
#define TLBMCFG_MASK 0x03
#define CFCFG_MASK 0x01
#define TIPCF_MASK 0x01
#define V2PCFG_MASK 0x03
#define HUME_MASK 0x01
#define PTMTCFG_MASK 0x01
#define PTMEMTYPE_MASK 0x07
/* BFBCR */
#define BFBDFE_MASK 0x01
#define BFBSFE_MASK 0x01
#define SFVS_MASK 0x01
#define FLVIC_MASK 0x0F
#define SLVIC_MASK 0x0F
/* CONTEXTIDR */
#define CONTEXTIDR_ASID_MASK 0xFF
#define PROCID_MASK 0x00FFFFFF
/* FSR */
#define TF_MASK 0x01
#define AFF_MASK 0x01
#define APF_MASK 0x01
#define TLBMF_MASK 0x01
#define HTWDEEF_MASK 0x01
#define HTWSEEF_MASK 0x01
#define MHF_MASK 0x01
#define SL_MASK 0x01
#define SS_MASK 0x01
#define MULTI_MASK 0x01
/* FSYNR0 */
#define AMID_MASK 0xFF
#define APID_MASK 0x1F
#define ABID_MASK 0x07
#define ATID_MASK 0xFF
/* FSYNR1 */
#define AMEMTYPE_MASK 0x07
#define ASHARED_MASK 0x01
#define AINNERSHARED_MASK 0x01
#define APRIV_MASK 0x01
#define APROTNS_MASK 0x01
#define AINST_MASK 0x01
#define AWRITE_MASK 0x01
#define ABURST_MASK 0x01
#define ALEN_MASK 0x0F
#define FSYNR1_ASIZE_MASK 0x07
#define ALOCK_MASK 0x03
#define AFULL_MASK 0x01
/* NMRR */
#define ICPC0_MASK 0x03
#define ICPC1_MASK 0x03
#define ICPC2_MASK 0x03
#define ICPC3_MASK 0x03
#define ICPC4_MASK 0x03
#define ICPC5_MASK 0x03
#define ICPC6_MASK 0x03
#define ICPC7_MASK 0x03
#define OCPC0_MASK 0x03
#define OCPC1_MASK 0x03
#define OCPC2_MASK 0x03
#define OCPC3_MASK 0x03
#define OCPC4_MASK 0x03
#define OCPC5_MASK 0x03
#define OCPC6_MASK 0x03
#define OCPC7_MASK 0x03
/* PAR */
#define FAULT_MASK 0x01
/* If a fault is present, these are the
same as the fault fields in the FAR */
#define FAULT_TF_MASK 0x01
#define FAULT_AFF_MASK 0x01
#define FAULT_APF_MASK 0x01
#define FAULT_TLBMF_MASK 0x01
#define FAULT_HTWDEEF_MASK 0x01
#define FAULT_HTWSEEF_MASK 0x01
#define FAULT_MHF_MASK 0x01
#define FAULT_SL_MASK 0x01
#define FAULT_SS_MASK 0x01
/* If NO fault is present, the following
* fields are in effect
* (FAULT remains as before) */
#define PAR_NOFAULT_SS_MASK 0x01
#define PAR_NOFAULT_MT_MASK 0x07
#define PAR_NOFAULT_SH_MASK 0x01
#define PAR_NOFAULT_NS_MASK 0x01
#define PAR_NOFAULT_NOS_MASK 0x01
#define PAR_NPFAULT_PA_MASK 0x000FFFFF
/* PRRR */
#define MTC0_MASK 0x03
#define MTC1_MASK 0x03
#define MTC2_MASK 0x03
#define MTC3_MASK 0x03
#define MTC4_MASK 0x03
#define MTC5_MASK 0x03
#define MTC6_MASK 0x03
#define MTC7_MASK 0x03
#define SHDSH0_MASK 0x01
#define SHDSH1_MASK 0x01
#define SHNMSH0_MASK 0x01
#define SHNMSH1_MASK 0x01
#define NOS0_MASK 0x01
#define NOS1_MASK 0x01
#define NOS2_MASK 0x01
#define NOS3_MASK 0x01
#define NOS4_MASK 0x01
#define NOS5_MASK 0x01
#define NOS6_MASK 0x01
#define NOS7_MASK 0x01
/* RESUME */
#define TNR_MASK 0x01
/* SCTLR */
#define M_MASK 0x01
#define TRE_MASK 0x01
#define AFE_MASK 0x01
#define HAF_MASK 0x01
#define BE_MASK 0x01
#define AFFD_MASK 0x01
/* TLBIASID */
#define TLBIASID_ASID_MASK 0xFF
/* TLBIVA */
#define TLBIVA_ASID_MASK 0xFF
#define TLBIVA_VA_MASK 0x000FFFFF
/* TLBIVAA */
#define TLBIVAA_VA_MASK 0x000FFFFF
/* TLBLCKR */
#define LKE_MASK 0x01
#define TLBLCKR_TLBIALLCFG_MASK 0x01
#define TLBIASIDCFG_MASK 0x01
#define TLBIVAACFG_MASK 0x01
#define FLOOR_MASK 0xFF
#define VICTIM_MASK 0xFF
/* TTBCR */
#define N_MASK 0x07
#define PD0_MASK 0x01
#define PD1_MASK 0x01
/* TTBR0 */
#define TTBR0_IRGNH_MASK 0x01
#define TTBR0_SH_MASK 0x01
#define TTBR0_ORGN_MASK 0x03
#define TTBR0_NOS_MASK 0x01
#define TTBR0_IRGNL_MASK 0x01
#define TTBR0_PA_MASK 0x0003FFFF
/* TTBR1 */
#define TTBR1_IRGNH_MASK 0x01
#define TTBR1_SH_MASK 0x01
#define TTBR1_ORGN_MASK 0x03
#define TTBR1_NOS_MASK 0x01
#define TTBR1_IRGNL_MASK 0x01
#define TTBR1_PA_MASK 0x0003FFFF
/* V2PSR */
#define HIT_MASK 0x01
#define INDEX_MASK 0xFF
/* V2Pxx */
#define V2Pxx_INDEX_MASK 0xFF
#define V2Pxx_VA_MASK 0x000FFFFF
/* Context Register Shifts */
/* ACTLR */
#define CFERE_SHIFT 0
#define CFEIE_SHIFT 1
#define PTSHCFG_SHIFT 2
#define RCOSH_SHIFT 4
#define RCISH_SHIFT 5
#define RCNSH_SHIFT 6
#define PRIVCFG_SHIFT 8
#define DNA_SHIFT 10
#define DNLV2PA_SHIFT 11
#define TLBMCFG_SHIFT 12
#define CFCFG_SHIFT 14
#define TIPCF_SHIFT 15
#define V2PCFG_SHIFT 16
#define HUME_SHIFT 18
#define PTMTCFG_SHIFT 20
#define PTMEMTYPE_SHIFT 21
/* BFBCR */
#define BFBDFE_SHIFT 0
#define BFBSFE_SHIFT 1
#define SFVS_SHIFT 2
#define FLVIC_SHIFT 4
#define SLVIC_SHIFT 8
/* CONTEXTIDR */
#define CONTEXTIDR_ASID_SHIFT 0
#define PROCID_SHIFT 8
/* FSR */
#define TF_SHIFT 1
#define AFF_SHIFT 2
#define APF_SHIFT 3
#define TLBMF_SHIFT 4
#define HTWDEEF_SHIFT 5
#define HTWSEEF_SHIFT 6
#define MHF_SHIFT 7
#define SL_SHIFT 16
#define SS_SHIFT 30
#define MULTI_SHIFT 31
/* FSYNR0 */
#define AMID_SHIFT 0
#define APID_SHIFT 8
#define ABID_SHIFT 13
#define ATID_SHIFT 24
/* FSYNR1 */
#define AMEMTYPE_SHIFT 0
#define ASHARED_SHIFT 3
#define AINNERSHARED_SHIFT 4
#define APRIV_SHIFT 5
#define APROTNS_SHIFT 6
#define AINST_SHIFT 7
#define AWRITE_SHIFT 8
#define ABURST_SHIFT 10
#define ALEN_SHIFT 12
#define FSYNR1_ASIZE_SHIFT 16
#define ALOCK_SHIFT 20
#define AFULL_SHIFT 24
/* NMRR */
#define ICPC0_SHIFT 0
#define ICPC1_SHIFT 2
#define ICPC2_SHIFT 4
#define ICPC3_SHIFT 6
#define ICPC4_SHIFT 8
#define ICPC5_SHIFT 10
#define ICPC6_SHIFT 12
#define ICPC7_SHIFT 14
#define OCPC0_SHIFT 16
#define OCPC1_SHIFT 18
#define OCPC2_SHIFT 20
#define OCPC3_SHIFT 22
#define OCPC4_SHIFT 24
#define OCPC5_SHIFT 26
#define OCPC6_SHIFT 28
#define OCPC7_SHIFT 30
/* PAR */
#define FAULT_SHIFT 0
/* If a fault is present, these are the
same as the fault fields in the FAR */
#define FAULT_TF_SHIFT 1
#define FAULT_AFF_SHIFT 2
#define FAULT_APF_SHIFT 3
#define FAULT_TLBMF_SHIFT 4
#define FAULT_HTWDEEF_SHIFT 5
#define FAULT_HTWSEEF_SHIFT 6
#define FAULT_MHF_SHIFT 7
#define FAULT_SL_SHIFT 16
#define FAULT_SS_SHIFT 30
/* If NO fault is present, the following
* fields are in effect
* (FAULT remains as before) */
#define PAR_NOFAULT_SS_SHIFT 1
#define PAR_NOFAULT_MT_SHIFT 4
#define PAR_NOFAULT_SH_SHIFT 7
#define PAR_NOFAULT_NS_SHIFT 9
#define PAR_NOFAULT_NOS_SHIFT 10
#define PAR_NPFAULT_PA_SHIFT 12
/* PRRR */
#define MTC0_SHIFT 0
#define MTC1_SHIFT 2
#define MTC2_SHIFT 4
#define MTC3_SHIFT 6
#define MTC4_SHIFT 8
#define MTC5_SHIFT 10
#define MTC6_SHIFT 12
#define MTC7_SHIFT 14
#define SHDSH0_SHIFT 16
#define SHDSH1_SHIFT 17
#define SHNMSH0_SHIFT 18
#define SHNMSH1_SHIFT 19
#define NOS0_SHIFT 24
#define NOS1_SHIFT 25
#define NOS2_SHIFT 26
#define NOS3_SHIFT 27
#define NOS4_SHIFT 28
#define NOS5_SHIFT 29
#define NOS6_SHIFT 30
#define NOS7_SHIFT 31
/* RESUME */
#define TNR_SHIFT 0
/* SCTLR */
#define M_SHIFT 0
#define TRE_SHIFT 1
#define AFE_SHIFT 2
#define HAF_SHIFT 3
#define BE_SHIFT 4
#define AFFD_SHIFT 5
/* TLBIASID */
#define TLBIASID_ASID_SHIFT 0
/* TLBIVA */
#define TLBIVA_ASID_SHIFT 0
#define TLBIVA_VA_SHIFT 12
/* TLBIVAA */
#define TLBIVAA_VA_SHIFT 12
/* TLBLCKR */
#define LKE_SHIFT 0
#define TLBLCKR_TLBIALLCFG_SHIFT 1
#define TLBIASIDCFG_SHIFT 2
#define TLBIVAACFG_SHIFT 3
#define FLOOR_SHIFT 8
#define VICTIM_SHIFT 8
/* TTBCR */
#define N_SHIFT 3
#define PD0_SHIFT 4
#define PD1_SHIFT 5
/* TTBR0 */
#define TTBR0_IRGNH_SHIFT 0
#define TTBR0_SH_SHIFT 1
#define TTBR0_ORGN_SHIFT 3
#define TTBR0_NOS_SHIFT 5
#define TTBR0_IRGNL_SHIFT 6
#define TTBR0_PA_SHIFT 14
/* TTBR1 */
#define TTBR1_IRGNH_SHIFT 0
#define TTBR1_SH_SHIFT 1
#define TTBR1_ORGN_SHIFT 3
#define TTBR1_NOS_SHIFT 5
#define TTBR1_IRGNL_SHIFT 6
#define TTBR1_PA_SHIFT 14
/* V2PSR */
#define HIT_SHIFT 0
#define INDEX_SHIFT 8
/* V2Pxx */
#define V2Pxx_INDEX_SHIFT 0
#define V2Pxx_VA_SHIFT 12
#endif
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