2019-01-17 18:14:18 -05:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2018-05-11 08:12:49 -04:00
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/*
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* AEGIS common definitions
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*
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* Copyright (c) 2018 Ondrej Mosnacek <omosnacek@gmail.com>
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* Copyright (c) 2018 Red Hat, Inc. All rights reserved.
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*/
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#ifndef _CRYPTO_AEGIS_H
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#define _CRYPTO_AEGIS_H
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#include <crypto/aes.h>
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crypto: aegis - avoid prerotated AES tables
The generic AES code provides four sets of lookup tables, where each
set consists of four tables containing the same 32-bit values, but
rotated by 0, 8, 16 and 24 bits, respectively. This makes sense for
CISC architectures such as x86 which support memory operands, but
for other architectures, the rotates are quite cheap, and using all
four tables needlessly thrashes the D-cache, and actually hurts rather
than helps performance.
Since x86 already has its own implementation of AEGIS based on AES-NI
instructions, let's tweak the generic implementation towards other
architectures, and avoid the prerotated tables, and perform the
rotations inline. On ARM Cortex-A53, this results in a ~8% speedup.
Acked-by: Ondrej Mosnacek <omosnace@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-03 04:55:09 -04:00
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#include <linux/bitops.h>
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2018-05-11 08:12:49 -04:00
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#include <linux/types.h>
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#define AEGIS_BLOCK_SIZE 16
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union aegis_block {
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__le64 words64[AEGIS_BLOCK_SIZE / sizeof(__le64)];
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2018-10-01 04:36:38 -04:00
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__le32 words32[AEGIS_BLOCK_SIZE / sizeof(__le32)];
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2018-05-11 08:12:49 -04:00
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u8 bytes[AEGIS_BLOCK_SIZE];
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};
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#define AEGIS_BLOCK_ALIGN (__alignof__(union aegis_block))
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#define AEGIS_ALIGNED(p) IS_ALIGNED((uintptr_t)p, AEGIS_BLOCK_ALIGN)
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2019-07-18 09:50:04 -04:00
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static __always_inline void crypto_aegis_block_xor(union aegis_block *dst,
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const union aegis_block *src)
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2018-05-11 08:12:49 -04:00
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{
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dst->words64[0] ^= src->words64[0];
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dst->words64[1] ^= src->words64[1];
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}
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2019-07-18 09:50:04 -04:00
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static __always_inline void crypto_aegis_block_and(union aegis_block *dst,
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const union aegis_block *src)
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2018-05-11 08:12:49 -04:00
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{
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dst->words64[0] &= src->words64[0];
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dst->words64[1] &= src->words64[1];
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}
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2019-07-18 09:50:04 -04:00
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static __always_inline void crypto_aegis_aesenc(union aegis_block *dst,
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const union aegis_block *src,
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const union aegis_block *key)
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2018-05-11 08:12:49 -04:00
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{
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const u8 *s = src->bytes;
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crypto: aegis - avoid prerotated AES tables
The generic AES code provides four sets of lookup tables, where each
set consists of four tables containing the same 32-bit values, but
rotated by 0, 8, 16 and 24 bits, respectively. This makes sense for
CISC architectures such as x86 which support memory operands, but
for other architectures, the rotates are quite cheap, and using all
four tables needlessly thrashes the D-cache, and actually hurts rather
than helps performance.
Since x86 already has its own implementation of AEGIS based on AES-NI
instructions, let's tweak the generic implementation towards other
architectures, and avoid the prerotated tables, and perform the
rotations inline. On ARM Cortex-A53, this results in a ~8% speedup.
Acked-by: Ondrej Mosnacek <omosnace@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-03 04:55:09 -04:00
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const u32 *t = crypto_ft_tab[0];
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2018-05-11 08:12:49 -04:00
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u32 d0, d1, d2, d3;
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crypto: aegis - avoid prerotated AES tables
The generic AES code provides four sets of lookup tables, where each
set consists of four tables containing the same 32-bit values, but
rotated by 0, 8, 16 and 24 bits, respectively. This makes sense for
CISC architectures such as x86 which support memory operands, but
for other architectures, the rotates are quite cheap, and using all
four tables needlessly thrashes the D-cache, and actually hurts rather
than helps performance.
Since x86 already has its own implementation of AEGIS based on AES-NI
instructions, let's tweak the generic implementation towards other
architectures, and avoid the prerotated tables, and perform the
rotations inline. On ARM Cortex-A53, this results in a ~8% speedup.
Acked-by: Ondrej Mosnacek <omosnace@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-07-03 04:55:09 -04:00
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d0 = t[s[ 0]] ^ rol32(t[s[ 5]], 8) ^ rol32(t[s[10]], 16) ^ rol32(t[s[15]], 24);
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d1 = t[s[ 4]] ^ rol32(t[s[ 9]], 8) ^ rol32(t[s[14]], 16) ^ rol32(t[s[ 3]], 24);
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d2 = t[s[ 8]] ^ rol32(t[s[13]], 8) ^ rol32(t[s[ 2]], 16) ^ rol32(t[s[ 7]], 24);
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d3 = t[s[12]] ^ rol32(t[s[ 1]], 8) ^ rol32(t[s[ 6]], 16) ^ rol32(t[s[11]], 24);
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2018-05-11 08:12:49 -04:00
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2018-10-01 04:36:38 -04:00
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dst->words32[0] = cpu_to_le32(d0) ^ key->words32[0];
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dst->words32[1] = cpu_to_le32(d1) ^ key->words32[1];
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dst->words32[2] = cpu_to_le32(d2) ^ key->words32[2];
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dst->words32[3] = cpu_to_le32(d3) ^ key->words32[3];
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2018-05-11 08:12:49 -04:00
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}
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#endif /* _CRYPTO_AEGIS_H */
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