449 lines
11 KiB
ArmAsm
449 lines
11 KiB
ArmAsm
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/*
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* CRISv32 kernel startup code.
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*
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* Copyright (C) 2003, Axis Communications AB
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*/
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#include <linux/config.h>
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#define ASSEMBLER_MACROS_ONLY
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/*
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* The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
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* -traditional must not be used when assembling this file.
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*/
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#include <asm/arch/hwregs/reg_rdwr.h>
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#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
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#include <asm/arch/hwregs/asm/reg_map_asm.h>
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#include <asm/arch/hwregs/asm/config_defs_asm.h>
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#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
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#define CRAMFS_MAGIC 0x28cd3d45
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#define RAM_INIT_MAGIC 0x56902387
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#define COMMAND_LINE_MAGIC 0x87109563
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;; NOTE: R8 and R9 carry information from the decompressor (if the
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;; kernel was compressed). They must not be used in the code below
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;; until they are read!
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;; Exported symbols.
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.global etrax_irv
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.global romfs_start
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.global romfs_length
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.global romfs_in_flash
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.global swapper_pg_dir
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.global crisv32_nand_boot
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.global crisv32_nand_cramfs_offset
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;; Dummy section to make it bootable with current VCS simulator
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#ifdef CONFIG_ETRAXFS_SIM
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.section ".boot", "ax"
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ba tstart
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nop
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#endif
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.text
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tstart:
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;; This is the entry point of the kernel. The CPU is currently in
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;; supervisor mode.
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;;
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;; 0x00000000 if flash.
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;; 0x40004000 if DRAM.
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;;
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di
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;; Start clocks for used blocks.
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move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
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move.d [$r1], $r0
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or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
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REG_STATE(config, rw_clk_ctrl, bif, yes) | \
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REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
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move.d $r0, [$r1]
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;; Set up waitstates etc
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move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
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move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
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move.d $r1, [$r0]
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move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
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move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
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move.d $r1, [$r0]
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move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
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move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
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move.d $r1, [$r0]
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move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
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move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
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move.d $r1, [$r0]
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#ifdef CONFIG_ETRAXFS_SIM
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;; Set up minimal flash waitstates
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move.d 0, $r10
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move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11
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move.d $r10, [$r11]
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#endif
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;; Setup and enable the MMU. Use same configuration for both the data
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;; and the instruction MMU.
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;;
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;; Note; 3 cycles is needed for a bank-select to take effect. Further;
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;; bank 1 is the instruction MMU, bank 2 is the data MMU.
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#ifndef CONFIG_ETRAXFS_SIM
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move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
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#else
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;; Map the virtual DRAM to the RW eprom area at address 0.
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;; Also map 0xa for the hook calls,
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move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) \
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| REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0
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#endif
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;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
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move.d REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4) \
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| REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1
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;; Enable certain page protections and setup linear mapping
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;; for f,e,c,b,4,0.
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#ifndef CONFIG_ETRAXFS_SIM
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move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
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| REG_STATE(mmu, rw_mm_cfg, acc, on) \
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| REG_STATE(mmu, rw_mm_cfg, ex, on) \
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| REG_STATE(mmu, rw_mm_cfg, inv, on) \
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| REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_d, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_a, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
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#else
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move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
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| REG_STATE(mmu, rw_mm_cfg, acc, on) \
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| REG_STATE(mmu, rw_mm_cfg, ex, on) \
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| REG_STATE(mmu, rw_mm_cfg, inv, on) \
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| REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_d, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_a, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
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| REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
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| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
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#endif
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;; Update instruction MMU.
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move 1, $srs
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nop
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nop
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nop
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move $r0, $s2 ; kbase_hi.
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move $r1, $s1 ; kbase_lo.
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move $r2, $s0 ; mm_cfg, virtual memory configuration.
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;; Update data MMU.
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move 2, $srs
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nop
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nop
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nop
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move $r0, $s2 ; kbase_hi.
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move $r1, $s1 ; kbase_lo
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move $r2, $s0 ; mm_cfg, virtual memory configuration.
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;; Enable data and instruction MMU.
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move 0, $srs
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moveq 0xf, $r0 ; IMMU, DMMU, DCache, Icache on
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nop
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nop
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nop
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move $r0, $s0
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nop
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nop
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nop
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#ifdef CONFIG_SMP
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;; Read CPU ID
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move 0, $srs
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nop
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nop
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nop
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move $s10, $r0
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cmpq 0, $r0
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beq master_cpu
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nop
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slave_cpu:
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; A slave waits for cpu_now_booting to be equal to CPU ID.
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move.d cpu_now_booting, $r1
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slave_wait:
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cmp.d [$r1], $r0
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bne slave_wait
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nop
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; Time to boot-up. Get stack location provided by master CPU.
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move.d smp_init_current_idle_thread, $r1
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move.d [$r1], $sp
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add.d 8192, $sp
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move.d ebp_start, $r0 ; Defined in linker-script.
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move $r0, $ebp
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jsr smp_callin
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nop
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master_cpu:
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#endif
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#ifndef CONFIG_ETRAXFS_SIM
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;; Check if starting from DRAM or flash.
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lapcq ., $r0
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and.d 0x7fffffff, $r0 ; Mask off the non-cache bit.
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cmp.d 0x10000, $r0 ; Arbitrary, something above this code.
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blo _inflash0
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nop
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#endif
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jump _inram ; Jump to cached RAM.
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nop
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;; Jumpgate.
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_inflash0:
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jump _inflash
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nop
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;; Put the following in a section so that storage for it can be
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;; reclaimed after init is finished.
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.section ".init.text", "ax"
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_inflash:
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;; Initialize DRAM.
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cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
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beq _dram_initialized
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nop
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#include "../lib/dram_init.S"
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_dram_initialized:
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;; Copy the text and data section to DRAM. This depends on that the
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;; variables used below are correctly set up by the linker script.
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;; The calculated value stored in R4 is used below.
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moveq 0, $r0 ; Source.
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move.d text_start, $r1 ; Destination.
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move.d __vmlinux_end, $r2
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move.d $r2, $r4
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sub.d $r1, $r4
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1: move.w [$r0+], $r3
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move.w $r3, [$r1+]
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cmp.d $r2, $r1
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blo 1b
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nop
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;; Keep CRAMFS in flash.
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moveq 0, $r0
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move.d romfs_length, $r1
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move.d $r0, [$r1]
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move.d [$r4], $r0 ; cramfs_super.magic
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cmp.d CRAMFS_MAGIC, $r0
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bne 1f
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nop
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addoq +4, $r4, $acr
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move.d [$acr], $r0
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move.d romfs_length, $r1
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move.d $r0, [$r1]
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add.d 0xf0000000, $r4 ; Add cached flash start in virtual memory.
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move.d romfs_start, $r1
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move.d $r4, [$r1]
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1: moveq 1, $r0
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move.d romfs_in_flash, $r1
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move.d $r0, [$r1]
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jump _start_it ; Jump to cached code.
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nop
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_inram:
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;; Check if booting from NAND flash (in that case we just remember the offset
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;; into the flash where cramfs should be).
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move.d REG_ADDR(config, regi_config, r_bootsel), $r0
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move.d [$r0], $r0
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and.d REG_MASK(config, r_bootsel, boot_mode), $r0
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cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0
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bne move_cramfs
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moveq 1,$r0
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move.d crisv32_nand_boot, $r1
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move.d $r0, [$r1]
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move.d crisv32_nand_cramfs_offset, $r1
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move.d $r9, [$r1]
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moveq 1, $r0
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move.d romfs_in_flash, $r1
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move.d $r0, [$r1]
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jump _start_it
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nop
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move_cramfs:
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;; Move the cramfs after BSS.
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moveq 0, $r0
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move.d romfs_length, $r1
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move.d $r0, [$r1]
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#ifndef CONFIG_ETRAXFS_SIM
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;; The kernel could have been unpacked to DRAM by the loader, but
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;; the cramfs image could still be inte the flash immediately
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;; following the compressed kernel image. The loaded passes the address
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;; of the bute succeeding the last compressed byte in the flash in
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;; register R9 when starting the kernel.
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cmp.d 0x0ffffff8, $r9
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bhs _no_romfs_in_flash ; R9 points outside the flash area.
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nop
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#else
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ba _no_romfs_in_flash
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nop
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#endif
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move.d [$r9], $r0 ; cramfs_super.magic
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cmp.d CRAMFS_MAGIC, $r0
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bne _no_romfs_in_flash
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nop
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addoq +4, $r9, $acr
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move.d [$acr], $r0
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move.d romfs_length, $r1
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move.d $r0, [$r1]
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add.d 0xf0000000, $r9 ; Add cached flash start in virtual memory.
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move.d romfs_start, $r1
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move.d $r9, [$r1]
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moveq 1, $r0
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move.d romfs_in_flash, $r1
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move.d $r0, [$r1]
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jump _start_it ; Jump to cached code.
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nop
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_no_romfs_in_flash:
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;; Look for cramfs.
|
||
|
|
#ifndef CONFIG_ETRAXFS_SIM
|
||
|
|
move.d __vmlinux_end, $r0
|
||
|
|
#else
|
||
|
|
move.d __end, $r0
|
||
|
|
#endif
|
||
|
|
move.d [$r0], $r1
|
||
|
|
cmp.d CRAMFS_MAGIC, $r1
|
||
|
|
bne 2f
|
||
|
|
nop
|
||
|
|
|
||
|
|
addoq +4, $r0, $acr
|
||
|
|
move.d [$acr], $r2
|
||
|
|
move.d _end, $r1
|
||
|
|
move.d romfs_start, $r3
|
||
|
|
move.d $r1, [$r3]
|
||
|
|
move.d romfs_length, $r3
|
||
|
|
move.d $r2, [$r3]
|
||
|
|
|
||
|
|
#ifndef CONFIG_ETRAXFS_SIM
|
||
|
|
add.d $r2, $r0
|
||
|
|
add.d $r2, $r1
|
||
|
|
|
||
|
|
lsrq 1, $r2 ; Size is in bytes, we copy words.
|
||
|
|
addq 1, $r2
|
||
|
|
1:
|
||
|
|
move.w [$r0], $r3
|
||
|
|
move.w $r3, [$r1]
|
||
|
|
subq 2, $r0
|
||
|
|
subq 2, $r1
|
||
|
|
subq 1, $r2
|
||
|
|
bne 1b
|
||
|
|
nop
|
||
|
|
#endif
|
||
|
|
|
||
|
|
2:
|
||
|
|
moveq 0, $r0
|
||
|
|
move.d romfs_in_flash, $r1
|
||
|
|
move.d $r0, [$r1]
|
||
|
|
|
||
|
|
jump _start_it ; Jump to cached code.
|
||
|
|
nop
|
||
|
|
|
||
|
|
_start_it:
|
||
|
|
|
||
|
|
;; Check if kernel command line is supplied
|
||
|
|
cmp.d COMMAND_LINE_MAGIC, $r10
|
||
|
|
bne no_command_line
|
||
|
|
nop
|
||
|
|
|
||
|
|
move.d 256, $r13
|
||
|
|
move.d cris_command_line, $r10
|
||
|
|
or.d 0x80000000, $r11 ; Make it virtual
|
||
|
|
1:
|
||
|
|
move.b [$r11+], $r12
|
||
|
|
move.b $r12, [$r10+]
|
||
|
|
subq 1, $r13
|
||
|
|
bne 1b
|
||
|
|
nop
|
||
|
|
|
||
|
|
no_command_line:
|
||
|
|
|
||
|
|
;; The kernel stack contains a task structure for each task. This
|
||
|
|
;; the initial kernel stack is in the same page as the init_task,
|
||
|
|
;; but starts at the top of the page, i.e. + 8192 bytes.
|
||
|
|
move.d init_thread_union + 8192, $sp
|
||
|
|
move.d ebp_start, $r0 ; Defined in linker-script.
|
||
|
|
move $r0, $ebp
|
||
|
|
move.d etrax_irv, $r1 ; Set the exception base register and pointer.
|
||
|
|
move.d $r0, [$r1]
|
||
|
|
|
||
|
|
#ifndef CONFIG_ETRAXFS_SIM
|
||
|
|
;; Clear the BSS region from _bss_start to _end.
|
||
|
|
move.d __bss_start, $r0
|
||
|
|
move.d _end, $r1
|
||
|
|
1: clear.d [$r0+]
|
||
|
|
cmp.d $r1, $r0
|
||
|
|
blo 1b
|
||
|
|
nop
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_ETRAXFS_SIM
|
||
|
|
/* Set the watchdog timeout to something big. Will be removed when */
|
||
|
|
/* watchdog can be disabled with command line option */
|
||
|
|
move.d 0x7fffffff, $r10
|
||
|
|
jsr CPU_WATCHDOG_TIMEOUT
|
||
|
|
nop
|
||
|
|
#endif
|
||
|
|
|
||
|
|
; Initialize registers to increase determinism
|
||
|
|
move.d __bss_start, $r0
|
||
|
|
movem [$r0], $r13
|
||
|
|
|
||
|
|
jump start_kernel ; Jump to start_kernel() in init/main.c.
|
||
|
|
nop
|
||
|
|
|
||
|
|
.data
|
||
|
|
etrax_irv:
|
||
|
|
.dword 0
|
||
|
|
romfs_start:
|
||
|
|
.dword 0
|
||
|
|
romfs_length:
|
||
|
|
.dword 0
|
||
|
|
romfs_in_flash:
|
||
|
|
.dword 0
|
||
|
|
crisv32_nand_boot:
|
||
|
|
.dword 0
|
||
|
|
crisv32_nand_cramfs_offset:
|
||
|
|
.dword 0
|
||
|
|
|
||
|
|
swapper_pg_dir = 0xc0002000
|
||
|
|
|
||
|
|
.section ".init.data", "aw"
|
||
|
|
|
||
|
|
#include "../lib/hw_settings.S"
|