264 lines
7.6 KiB
C
264 lines
7.6 KiB
C
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/*
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* Support for IBM PPC 405EP evaluation board (Bubinga).
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*
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* Author: SAW (IBM), derived from walnut.c.
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* Maintained by MontaVista Software <source@mvista.com>
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*
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* 2003 (c) MontaVista Softare Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/blkdev.h>
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#include <linux/pci.h>
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#include <linux/rtc.h>
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <asm/system.h>
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#include <asm/pci-bridge.h>
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#include <asm/processor.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/todc.h>
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#include <asm/kgdb.h>
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#include <asm/ocp.h>
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#include <asm/ibm_ocp_pci.h>
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#include <platforms/4xx/ibm405ep.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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extern bd_t __res;
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void *bubinga_rtc_base;
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/* Some IRQs unique to the board
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* Used by the generic 405 PCI setup functions in ppc4xx_pci.c
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*/
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int __init
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ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */
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{29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */
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{30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */
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{31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */
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};
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const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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};
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/* The serial clock for the chip is an internal clock determined by
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* different clock speeds/dividers.
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* Calculate the proper input baud rate and setup the serial driver.
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*/
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static void __init
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bubinga_early_serial_map(void)
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{
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u32 uart_div;
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int uart_clock;
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struct uart_port port;
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/* Calculate the serial clock input frequency
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*
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* The base baud is the PLL OUTA (provided in the board info
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* structure) divided by the external UART Divisor, divided
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* by 16.
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*/
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uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
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uart_clock = __res.bi_pllouta_freq / uart_div;
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/* Setup serial port access */
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memset(&port, 0, sizeof(port));
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port.membase = (void*)ACTING_UART0_IO_BASE;
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port.irq = ACTING_UART0_INT;
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port.uartclk = uart_clock;
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port.regshift = 0;
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port.iotype = SERIAL_IO_MEM;
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port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
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port.line = 0;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 0 failed\n");
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}
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port.membase = (void*)ACTING_UART1_IO_BASE;
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port.irq = ACTING_UART1_INT;
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port.line = 1;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 1 failed\n");
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}
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}
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void __init
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bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
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{
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unsigned int bar_response, bar;
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/*
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* Expected PCI mapping:
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*
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* PLB addr PCI memory addr
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* --------------------- ---------------------
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* 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
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* 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
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*
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* PLB addr PCI io addr
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* --------------------- ---------------------
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* e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
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*
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* The following code is simplified by assuming that the bootrom
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* has been well behaved in following this mapping.
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*/
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#ifdef DEBUG
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int i;
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printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
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printk("PCI bridge regs before fixup \n");
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for (i = 0; i <= 3; i++) {
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
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}
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printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
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printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
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printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
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printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
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#endif
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/* added for IBM boot rom version 1.15 bios bar changes -AK */
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/* Disable region first */
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out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
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/* PLB starting addr, PCI: 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
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/* PCI start addr, 0x80000000 */
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out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
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/* 512MB range of PLB to PCI */
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out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
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/* Enable no pre-fetch, enable region */
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out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
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(PPC405_PCI_UPPER_MEM -
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PPC405_PCI_MEM_BASE)) | 0x01));
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/* Disable region one */
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
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out_le32((void *) &(pcip->ptm1ms), 0x00000001);
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/* Disable region two */
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
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out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
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out_le32((void *) &(pcip->ptm2ms), 0x00000000);
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out_le32((void *) &(pcip->ptm2la), 0x00000000);
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/* Zero config bars */
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for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
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early_write_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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0x00000000);
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early_read_config_dword(hose, hose->first_busno,
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PCI_FUNC(hose->first_busno), bar,
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&bar_response);
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DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
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hose->first_busno, PCI_SLOT(hose->first_busno),
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PCI_FUNC(hose->first_busno), bar, bar_response);
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}
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/* end work arround */
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#ifdef DEBUG
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printk("PCI bridge regs after fixup \n");
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for (i = 0; i <= 3; i++) {
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
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printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
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}
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printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
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printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
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printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
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printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
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#endif
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}
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void __init
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bubinga_setup_arch(void)
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{
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ppc4xx_setup_arch();
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ibm_ocp_set_emac(0, 1);
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bubinga_early_serial_map();
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/* RTC step for the evb405ep */
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bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
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TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
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bubinga_rtc_base, 8);
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/* Identify the system */
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printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
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}
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void __init
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bubinga_map_io(void)
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{
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ppc4xx_map_io();
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io_block_mapping(BUBINGA_RTC_VADDR,
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BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
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}
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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ppc4xx_init(r3, r4, r5, r6, r7);
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ppc_md.setup_arch = bubinga_setup_arch;
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ppc_md.setup_io_mappings = bubinga_map_io;
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#ifdef CONFIG_GEN_RTC
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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#endif
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#ifdef CONFIG_KGDB
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ppc_md.early_serial_map = bubinga_early_serial_map;
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#endif
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}
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