2005-02-06 21:54:29 -05:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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2006-10-07 14:44:33 -04:00
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* Copyright (C) 2004, 05, 06 by Ralf Baechle
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2005-02-06 21:54:29 -05:00
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* Copyright (C) 2005 by MIPS Technologies, Inc.
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*/
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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2006-10-07 14:44:33 -04:00
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#include <asm/irq_regs.h>
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2005-02-06 21:54:29 -05:00
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#include "op_impl.h"
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2006-06-23 13:39:00 -04:00
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#define M_PERFCTL_EXL (1UL << 0)
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#define M_PERFCTL_KERNEL (1UL << 1)
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#define M_PERFCTL_SUPERVISOR (1UL << 2)
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#define M_PERFCTL_USER (1UL << 3)
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#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
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2006-10-22 19:44:02 -04:00
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#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5)
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2006-06-23 13:39:00 -04:00
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#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
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#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
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#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
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#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
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#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
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#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
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#define M_PERFCTL_WIDE (1UL << 30)
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#define M_PERFCTL_MORE (1UL << 31)
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#define M_COUNTER_OVERFLOW (1UL << 31)
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#ifdef CONFIG_MIPS_MT_SMP
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2006-10-23 08:22:06 -04:00
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#define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
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#define vpe_id() smp_processor_id()
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2006-06-23 13:39:00 -04:00
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#else
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2006-10-23 08:22:06 -04:00
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#define WHAT 0
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#define vpe_id() smp_processor_id()
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2006-06-23 13:39:00 -04:00
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#endif
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2005-02-06 21:54:29 -05:00
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2006-06-23 13:39:00 -04:00
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#define __define_perf_accessors(r, n, np) \
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\
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static inline unsigned int r_c0_ ## r ## n(void) \
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{ \
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2006-10-23 08:22:06 -04:00
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unsigned int cpu = vpe_id(); \
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2006-06-23 13:39:00 -04:00
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\
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switch (cpu) { \
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case 0: \
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return read_c0_ ## r ## n(); \
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case 1: \
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return read_c0_ ## r ## np(); \
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default: \
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BUG(); \
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} \
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2006-07-07 05:38:51 -04:00
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return 0; \
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2006-06-23 13:39:00 -04:00
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} \
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\
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static inline void w_c0_ ## r ## n(unsigned int value) \
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{ \
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2006-10-23 08:22:06 -04:00
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unsigned int cpu = vpe_id(); \
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2006-06-23 13:39:00 -04:00
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\
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switch (cpu) { \
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case 0: \
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write_c0_ ## r ## n(value); \
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return; \
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case 1: \
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write_c0_ ## r ## np(value); \
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return; \
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default: \
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BUG(); \
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} \
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2006-07-07 05:38:51 -04:00
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return; \
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2006-06-23 13:39:00 -04:00
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} \
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__define_perf_accessors(perfcntr, 0, 2)
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__define_perf_accessors(perfcntr, 1, 3)
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2007-03-01 12:58:24 -05:00
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__define_perf_accessors(perfcntr, 2, 0)
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__define_perf_accessors(perfcntr, 3, 1)
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2006-06-23 13:39:00 -04:00
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__define_perf_accessors(perfctrl, 0, 2)
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__define_perf_accessors(perfctrl, 1, 3)
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2007-03-01 12:58:24 -05:00
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__define_perf_accessors(perfctrl, 2, 0)
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__define_perf_accessors(perfctrl, 3, 1)
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2005-02-06 21:54:29 -05:00
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2006-05-23 03:42:38 -04:00
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struct op_mips_model op_model_mipsxx_ops;
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2005-02-06 21:54:29 -05:00
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static struct mipsxx_register_config {
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unsigned int control[4];
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unsigned int counter[4];
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} reg;
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/* Compute all of the registers in preparation for enabling profiling. */
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static void mipsxx_reg_setup(struct op_counter_config *ctr)
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{
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2006-05-23 03:42:38 -04:00
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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2005-02-06 21:54:29 -05:00
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int i;
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/* Compute the performance counter control word. */
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for (i = 0; i < counters; i++) {
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reg.control[i] = 0;
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reg.counter[i] = 0;
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if (!ctr[i].enabled)
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continue;
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reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
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M_PERFCTL_INTERRUPT_ENABLE;
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if (ctr[i].kernel)
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reg.control[i] |= M_PERFCTL_KERNEL;
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if (ctr[i].user)
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reg.control[i] |= M_PERFCTL_USER;
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if (ctr[i].exl)
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reg.control[i] |= M_PERFCTL_EXL;
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reg.counter[i] = 0x80000000 - ctr[i].count;
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}
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}
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/* Program all of the registers in preparation for enabling profiling. */
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static void mipsxx_cpu_setup (void *args)
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{
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2006-05-23 03:42:38 -04:00
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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2005-02-06 21:54:29 -05:00
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switch (counters) {
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case 4:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl3(0);
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w_c0_perfcntr3(reg.counter[3]);
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2005-02-06 21:54:29 -05:00
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case 3:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl2(0);
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w_c0_perfcntr2(reg.counter[2]);
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2005-02-06 21:54:29 -05:00
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case 2:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl1(0);
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w_c0_perfcntr1(reg.counter[1]);
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2005-02-06 21:54:29 -05:00
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case 1:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl0(0);
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w_c0_perfcntr0(reg.counter[0]);
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2005-02-06 21:54:29 -05:00
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}
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}
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/* Start all counters on current CPU */
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static void mipsxx_cpu_start(void *args)
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{
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2006-05-23 03:42:38 -04:00
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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2005-02-06 21:54:29 -05:00
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switch (counters) {
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case 4:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl3(WHAT | reg.control[3]);
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2005-02-06 21:54:29 -05:00
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case 3:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl2(WHAT | reg.control[2]);
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2005-02-06 21:54:29 -05:00
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case 2:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl1(WHAT | reg.control[1]);
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2005-02-06 21:54:29 -05:00
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case 1:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl0(WHAT | reg.control[0]);
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2005-02-06 21:54:29 -05:00
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}
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}
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/* Stop all counters on current CPU */
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static void mipsxx_cpu_stop(void *args)
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{
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2006-05-23 03:42:38 -04:00
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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2005-02-06 21:54:29 -05:00
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switch (counters) {
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case 4:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl3(0);
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2005-02-06 21:54:29 -05:00
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case 3:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl2(0);
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2005-02-06 21:54:29 -05:00
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case 2:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl1(0);
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2005-02-06 21:54:29 -05:00
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case 1:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl0(0);
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2005-02-06 21:54:29 -05:00
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}
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}
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2006-10-07 14:44:33 -04:00
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static int mipsxx_perfcount_handler(void)
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2005-02-06 21:54:29 -05:00
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{
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2006-05-23 03:42:38 -04:00
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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2005-02-06 21:54:29 -05:00
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unsigned int control;
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unsigned int counter;
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2005-12-09 07:29:38 -05:00
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int handled = 0;
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2005-02-06 21:54:29 -05:00
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switch (counters) {
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#define HANDLE_COUNTER(n) \
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case n + 1: \
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2006-06-23 13:39:00 -04:00
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control = r_c0_perfctrl ## n(); \
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counter = r_c0_perfcntr ## n(); \
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2005-02-06 21:54:29 -05:00
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if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
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(counter & M_COUNTER_OVERFLOW)) { \
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2006-10-07 14:44:33 -04:00
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oprofile_add_sample(get_irq_regs(), n); \
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2006-06-23 13:39:00 -04:00
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w_c0_perfcntr ## n(reg.counter[n]); \
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2005-12-09 07:29:38 -05:00
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handled = 1; \
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2005-02-06 21:54:29 -05:00
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}
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HANDLE_COUNTER(3)
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HANDLE_COUNTER(2)
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HANDLE_COUNTER(1)
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HANDLE_COUNTER(0)
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}
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2005-12-09 07:29:38 -05:00
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return handled;
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2005-02-06 21:54:29 -05:00
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}
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#define M_CONFIG1_PC (1 << 4)
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2006-06-23 13:39:00 -04:00
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static inline int __n_counters(void)
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2005-02-06 21:54:29 -05:00
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{
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if (!(read_c0_config1() & M_CONFIG1_PC))
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return 0;
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2006-06-23 13:39:00 -04:00
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if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
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2005-02-06 21:54:29 -05:00
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return 1;
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2006-06-23 13:39:00 -04:00
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if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
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2005-02-06 21:54:29 -05:00
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return 2;
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2006-06-23 13:39:00 -04:00
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if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
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2005-02-06 21:54:29 -05:00
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return 3;
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return 4;
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}
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2006-06-23 13:39:00 -04:00
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static inline int n_counters(void)
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{
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2006-10-22 19:44:02 -04:00
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int counters;
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switch (current_cpu_data.cputype) {
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case CPU_R10000:
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counters = 2;
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2007-02-28 10:34:22 -05:00
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break;
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2006-10-22 19:44:02 -04:00
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case CPU_R12000:
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case CPU_R14000:
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counters = 4;
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2007-02-28 10:34:22 -05:00
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break;
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2006-10-22 19:44:02 -04:00
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default:
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counters = __n_counters();
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}
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2006-06-23 13:39:00 -04:00
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return counters;
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}
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2005-02-06 21:54:29 -05:00
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static inline void reset_counters(int counters)
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{
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switch (counters) {
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case 4:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl3(0);
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w_c0_perfcntr3(0);
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2005-02-06 21:54:29 -05:00
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case 3:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl2(0);
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w_c0_perfcntr2(0);
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2005-02-06 21:54:29 -05:00
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case 2:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl1(0);
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w_c0_perfcntr1(0);
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2005-02-06 21:54:29 -05:00
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case 1:
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2006-06-23 13:39:00 -04:00
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w_c0_perfctrl0(0);
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w_c0_perfcntr0(0);
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2005-02-06 21:54:29 -05:00
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}
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}
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static int __init mipsxx_init(void)
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{
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int counters;
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counters = n_counters();
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2005-12-09 07:34:45 -05:00
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if (counters == 0) {
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printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
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2005-02-06 21:54:29 -05:00
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return -ENODEV;
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2005-12-09 07:34:45 -05:00
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}
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2005-02-06 21:54:29 -05:00
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reset_counters(counters);
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2007-03-01 12:58:24 -05:00
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#ifdef CONFIG_MIPS_MT_SMP
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counters >>= 1;
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#endif
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2006-05-23 03:42:38 -04:00
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op_model_mipsxx_ops.num_counters = counters;
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2005-02-06 21:54:29 -05:00
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switch (current_cpu_data.cputype) {
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2005-12-09 07:42:13 -05:00
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case CPU_20KC:
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2006-05-23 03:42:38 -04:00
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op_model_mipsxx_ops.cpu_type = "mips/20K";
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2005-12-09 07:42:13 -05:00
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break;
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2005-02-06 21:54:29 -05:00
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case CPU_24K:
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2006-05-23 03:42:38 -04:00
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op_model_mipsxx_ops.cpu_type = "mips/24K";
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2005-02-06 21:54:29 -05:00
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break;
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2005-12-09 07:42:13 -05:00
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case CPU_25KF:
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2006-05-23 03:42:38 -04:00
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op_model_mipsxx_ops.cpu_type = "mips/25K";
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2005-12-09 07:42:13 -05:00
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break;
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2006-02-01 12:54:30 -05:00
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case CPU_34K:
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2006-05-23 03:42:38 -04:00
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op_model_mipsxx_ops.cpu_type = "mips/34K";
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2006-02-01 12:54:30 -05:00
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break;
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2006-05-02 09:08:46 -04:00
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case CPU_74K:
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2006-05-23 03:42:38 -04:00
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op_model_mipsxx_ops.cpu_type = "mips/74K";
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2006-05-02 09:08:46 -04:00
|
|
|
break;
|
2006-02-01 12:54:30 -05:00
|
|
|
|
2005-12-09 07:42:13 -05:00
|
|
|
case CPU_5KC:
|
2006-05-23 03:42:38 -04:00
|
|
|
op_model_mipsxx_ops.cpu_type = "mips/5K";
|
2005-12-09 07:42:13 -05:00
|
|
|
break;
|
|
|
|
|
2006-10-22 19:44:02 -04:00
|
|
|
case CPU_R10000:
|
|
|
|
if ((current_cpu_data.processor_id & 0xff) == 0x20)
|
|
|
|
op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
|
|
|
|
else
|
|
|
|
op_model_mipsxx_ops.cpu_type = "mips/r10000";
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CPU_R12000:
|
|
|
|
case CPU_R14000:
|
|
|
|
op_model_mipsxx_ops.cpu_type = "mips/r12000";
|
|
|
|
break;
|
|
|
|
|
2006-01-17 15:06:32 -05:00
|
|
|
case CPU_SB1:
|
|
|
|
case CPU_SB1A:
|
2006-05-23 03:42:38 -04:00
|
|
|
op_model_mipsxx_ops.cpu_type = "mips/sb1";
|
2006-01-17 15:06:32 -05:00
|
|
|
break;
|
|
|
|
|
2005-02-06 21:54:29 -05:00
|
|
|
default:
|
|
|
|
printk(KERN_ERR "Profiling unsupported for this CPU\n");
|
|
|
|
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
perf_irq = mipsxx_perfcount_handler;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mipsxx_exit(void)
|
|
|
|
{
|
2007-03-01 12:58:24 -05:00
|
|
|
int counters = op_model_mipsxx_ops.num_counters;
|
|
|
|
#ifdef CONFIG_MIPS_MT_SMP
|
|
|
|
counters <<= 1;
|
|
|
|
#endif
|
|
|
|
reset_counters(counters);
|
2005-02-06 21:54:29 -05:00
|
|
|
|
|
|
|
perf_irq = null_perf_irq;
|
|
|
|
}
|
|
|
|
|
2006-05-23 03:42:38 -04:00
|
|
|
struct op_mips_model op_model_mipsxx_ops = {
|
2005-02-06 21:54:29 -05:00
|
|
|
.reg_setup = mipsxx_reg_setup,
|
|
|
|
.cpu_setup = mipsxx_cpu_setup,
|
|
|
|
.init = mipsxx_init,
|
|
|
|
.exit = mipsxx_exit,
|
|
|
|
.cpu_start = mipsxx_cpu_start,
|
|
|
|
.cpu_stop = mipsxx_cpu_stop,
|
|
|
|
};
|