372 lines
15 KiB
C
372 lines
15 KiB
C
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* SAA9730 ethernet driver description.
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*
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*/
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#ifndef _SAA9730_H
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#define _SAA9730_H
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/* Number of 6-byte entries in the CAM. */
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#define LAN_SAA9730_CAM_ENTRIES 10
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#define LAN_SAA9730_CAM_DWORDS ((LAN_SAA9730_CAM_ENTRIES*6)/4)
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/* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */
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#define LAN_SAA9730_PACKET_SIZE 2048
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/*
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* Number of TX buffers = number of RX buffers = 2, which is fixed according
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* to HW requirements.
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*/
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#define LAN_SAA9730_BUFFERS 2
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/* Number of RX packets per RX buffer. */
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#define LAN_SAA9730_RCV_Q_SIZE 15
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/* Number of TX packets per TX buffer. */
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#define LAN_SAA9730_TXM_Q_SIZE 15
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/*
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* We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
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* packets received.
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* If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
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* packets, the hardware can timeout after a certain time and still tell
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* us packets have arrived.
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* The timeout value in unit of 32 PCI clocks (33Mhz).
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* The value 200 approximates 0.0002 seconds.
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*/
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#define LAN_SAA9730_RCV_Q_INT_THRESHOLD 1
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#define LAN_SAA9730_DEFAULT_TIME_OUT_CNT 10
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#define RXSF_NDIS 0
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#define RXSF_READY 2
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#define RXSF_HWDONE 3
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#define TXSF_EMPTY 0
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#define TXSF_READY 2
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#define TXSF_HWDONE 3
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#define LANEND_LITTLE 0
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#define LANEND_BIG_2143 1
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#define LANEND_BIG_4321 2
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#define LANMB_ANY 0
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#define LANMB_8 1
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#define LANMB_32 2
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#define LANMB_64 3
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#define MACCM_AUTOMATIC 0
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#define MACCM_10MB 1
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#define MACCM_MII 2
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/*
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* PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board)
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*/
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#define PHY_CONTROL 0x0
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#define PHY_STATUS 0x1
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#define PHY_STATUS_LINK_UP 0x4
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#define PHY_CONTROL_RESET 0x8000
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#define PHY_CONTROL_AUTO_NEG 0x1000
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#define PHY_CONTROL_RESTART_AUTO_NEG 0x0200
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#define PHY_ADDRESS 0x0
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/* PK_COUNT register. */
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#define PK_COUNT_TX_A_SHF 24
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#define PK_COUNT_TX_A_MSK (0xff << PK_COUNT_TX_A_SHF)
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#define PK_COUNT_TX_B_SHF 16
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#define PK_COUNT_TX_B_MSK (0xff << PK_COUNT_TX_B_SHF)
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#define PK_COUNT_RX_A_SHF 8
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#define PK_COUNT_RX_A_MSK (0xff << PK_COUNT_RX_A_SHF)
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#define PK_COUNT_RX_B_SHF 0
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#define PK_COUNT_RX_B_MSK (0xff << PK_COUNT_RX_B_SHF)
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/* OK2USE register. */
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#define OK2USE_TX_A 0x8
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#define OK2USE_TX_B 0x4
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#define OK2USE_RX_A 0x2
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#define OK2USE_RX_B 0x1
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/* LAN DMA CONTROL register. */
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#define DMA_CTL_BLK_INT 0x80000000
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#define DMA_CTL_MAX_XFER_SHF 18
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#define DMA_CTL_MAX_XFER_MSK (0x3 << LAN_DMA_CTL_MAX_XFER_SHF)
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#define DMA_CTL_ENDIAN_SHF 16
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#define DMA_CTL_ENDIAN_MSK (0x3 << LAN_DMA_CTL_ENDIAN_SHF)
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#define DMA_CTL_RX_INT_COUNT_SHF 8
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#define DMA_CTL_RX_INT_COUNT_MSK (0xff << LAN_DMA_CTL_RX_INT_COUNT_SHF)
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#define DMA_CTL_EN_TX_DMA 0x00000080
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#define DMA_CTL_EN_RX_DMA 0x00000040
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#define DMA_CTL_RX_INT_BUFFUL_EN 0x00000020
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#define DMA_CTL_RX_INT_TO_EN 0x00000010
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#define DMA_CTL_RX_INT_EN 0x00000008
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#define DMA_CTL_TX_INT_EN 0x00000004
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#define DMA_CTL_MAC_TX_INT_EN 0x00000002
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#define DMA_CTL_MAC_RX_INT_EN 0x00000001
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/* DMA STATUS register. */
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#define DMA_STATUS_BAD_ADDR_SHF 16
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#define DMA_STATUS_BAD_ADDR_MSK (0xf << DMA_STATUS_BAD_ADDR_SHF)
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#define DMA_STATUS_RX_PKTS_RECEIVED_SHF 8
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#define DMA_STATUS_RX_PKTS_RECEIVED_MSK (0xff << DMA_STATUS_RX_PKTS_RECEIVED_SHF)
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#define DMA_STATUS_TX_EN_SYNC 0x00000080
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#define DMA_STATUS_RX_BUF_A_FUL 0x00000040
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#define DMA_STATUS_RX_BUF_B_FUL 0x00000020
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#define DMA_STATUS_RX_TO_INT 0x00000010
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#define DMA_STATUS_RX_INT 0x00000008
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#define DMA_STATUS_TX_INT 0x00000004
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#define DMA_STATUS_MAC_TX_INT 0x00000002
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#define DMA_STATUS_MAC_RX_INT 0x00000001
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/* DMA TEST/PANIC SWITHES register. */
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#define DMA_TEST_LOOPBACK 0x01000000
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#define DMA_TEST_SW_RESET 0x00000001
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/* MAC CONTROL register. */
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#define MAC_CONTROL_EN_MISS_ROLL 0x00002000
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#define MAC_CONTROL_MISS_ROLL 0x00000400
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#define MAC_CONTROL_LOOP10 0x00000080
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#define MAC_CONTROL_CONN_SHF 5
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#define MAC_CONTROL_CONN_MSK (0x3 << MAC_CONTROL_CONN_SHF)
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#define MAC_CONTROL_MAC_LOOP 0x00000010
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#define MAC_CONTROL_FULL_DUP 0x00000008
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#define MAC_CONTROL_RESET 0x00000004
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#define MAC_CONTROL_HALT_IMM 0x00000002
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#define MAC_CONTROL_HALT_REQ 0x00000001
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/* CAM CONTROL register. */
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#define CAM_CONTROL_COMP_EN 0x00000010
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#define CAM_CONTROL_NEG_CAM 0x00000008
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#define CAM_CONTROL_BROAD_ACC 0x00000004
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#define CAM_CONTROL_GROUP_ACC 0x00000002
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#define CAM_CONTROL_STATION_ACC 0x00000001
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/* TRANSMIT CONTROL register. */
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#define TX_CTL_EN_COMP 0x00004000
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#define TX_CTL_EN_TX_PAR 0x00002000
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#define TX_CTL_EN_LATE_COLL 0x00001000
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#define TX_CTL_EN_EX_COLL 0x00000800
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#define TX_CTL_EN_L_CARR 0x00000400
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#define TX_CTL_EN_EX_DEFER 0x00000200
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#define TX_CTL_EN_UNDER 0x00000100
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#define TX_CTL_MII10 0x00000080
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#define TX_CTL_SD_PAUSE 0x00000040
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#define TX_CTL_NO_EX_DEF0 0x00000020
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#define TX_CTL_F_BACK 0x00000010
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#define TX_CTL_NO_CRC 0x00000008
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#define TX_CTL_NO_PAD 0x00000004
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#define TX_CTL_TX_HALT 0x00000002
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#define TX_CTL_TX_EN 0x00000001
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/* TRANSMIT STATUS register. */
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#define TX_STATUS_SQ_ERR 0x00010000
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#define TX_STATUS_TX_HALTED 0x00008000
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#define TX_STATUS_COMP 0x00004000
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#define TX_STATUS_TX_PAR 0x00002000
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#define TX_STATUS_LATE_COLL 0x00001000
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#define TX_STATUS_TX10_STAT 0x00000800
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#define TX_STATUS_L_CARR 0x00000400
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#define TX_STATUS_EX_DEFER 0x00000200
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#define TX_STATUS_UNDER 0x00000100
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#define TX_STATUS_IN_TX 0x00000080
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#define TX_STATUS_PAUSED 0x00000040
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#define TX_STATUS_TX_DEFERRED 0x00000020
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#define TX_STATUS_EX_COLL 0x00000010
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#define TX_STATUS_TX_COLL_SHF 0
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#define TX_STATUS_TX_COLL_MSK (0xf << TX_STATUS_TX_COLL_SHF)
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/* RECEIVE CONTROL register. */
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#define RX_CTL_EN_GOOD 0x00004000
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#define RX_CTL_EN_RX_PAR 0x00002000
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#define RX_CTL_EN_LONG_ERR 0x00000800
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#define RX_CTL_EN_OVER 0x00000400
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#define RX_CTL_EN_CRC_ERR 0x00000200
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#define RX_CTL_EN_ALIGN 0x00000100
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#define RX_CTL_IGNORE_CRC 0x00000040
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#define RX_CTL_PASS_CTL 0x00000020
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#define RX_CTL_STRIP_CRC 0x00000010
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#define RX_CTL_SHORT_EN 0x00000008
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#define RX_CTL_LONG_EN 0x00000004
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#define RX_CTL_RX_HALT 0x00000002
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#define RX_CTL_RX_EN 0x00000001
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/* RECEIVE STATUS register. */
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#define RX_STATUS_RX_HALTED 0x00008000
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#define RX_STATUS_GOOD 0x00004000
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#define RX_STATUS_RX_PAR 0x00002000
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#define RX_STATUS_LONG_ERR 0x00000800
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#define RX_STATUS_OVERFLOW 0x00000400
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#define RX_STATUS_CRC_ERR 0x00000200
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#define RX_STATUS_ALIGN_ERR 0x00000100
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#define RX_STATUS_RX10_STAT 0x00000080
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#define RX_STATUS_INT_RX 0x00000040
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#define RX_STATUS_CTL_RECD 0x00000020
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/* MD_CA register. */
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#define MD_CA_PRE_SUP 0x00001000
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#define MD_CA_BUSY 0x00000800
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#define MD_CA_WR 0x00000400
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#define MD_CA_PHY_SHF 5
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#define MD_CA_PHY_MSK (0x1f << MD_CA_PHY_SHF)
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#define MD_CA_ADDR_SHF 0
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#define MD_CA_ADDR_MSK (0x1f << MD_CA_ADDR_SHF)
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/* Tx Status/Control. */
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#define TX_STAT_CTL_OWNER_SHF 30
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#define TX_STAT_CTL_OWNER_MSK (0x3 << TX_STAT_CTL_OWNER_SHF)
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#define TX_STAT_CTL_FRAME_SHF 27
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#define TX_STAT_CTL_FRAME_MSK (0x7 << TX_STAT_CTL_FRAME_SHF)
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#define TX_STAT_CTL_STATUS_SHF 11
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#define TX_STAT_CTL_STATUS_MSK (0x1ffff << TX_STAT_CTL_STATUS_SHF)
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#define TX_STAT_CTL_LENGTH_SHF 0
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#define TX_STAT_CTL_LENGTH_MSK (0x7ff << TX_STAT_CTL_LENGTH_SHF)
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#define TX_STAT_CTL_ERROR_MSK ((TX_STATUS_SQ_ERR | \
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TX_STATUS_TX_HALTED | \
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TX_STATUS_TX_PAR | \
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TX_STATUS_LATE_COLL | \
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TX_STATUS_L_CARR | \
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TX_STATUS_EX_DEFER | \
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TX_STATUS_UNDER | \
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TX_STATUS_PAUSED | \
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TX_STATUS_TX_DEFERRED | \
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TX_STATUS_EX_COLL | \
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TX_STATUS_TX_COLL_MSK) \
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<< TX_STAT_CTL_STATUS_SHF)
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#define TX_STAT_CTL_INT_AFTER_TX 0x4
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/* Rx Status/Control. */
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#define RX_STAT_CTL_OWNER_SHF 30
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#define RX_STAT_CTL_OWNER_MSK (0x3 << RX_STAT_CTL_OWNER_SHF)
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#define RX_STAT_CTL_STATUS_SHF 11
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#define RX_STAT_CTL_STATUS_MSK (0xffff << RX_STAT_CTL_STATUS_SHF)
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#define RX_STAT_CTL_LENGTH_SHF 0
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#define RX_STAT_CTL_LENGTH_MSK (0x7ff << RX_STAT_CTL_LENGTH_SHF)
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/* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */
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#define SAA9730_LAN_REGS_ADDR 0x20400
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struct lan_saa9730_regmap {
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volatile unsigned int TxBuffA; /* 0x20400 */
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volatile unsigned int TxBuffB; /* 0x20404 */
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volatile unsigned int RxBuffA; /* 0x20408 */
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volatile unsigned int RxBuffB; /* 0x2040c */
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volatile unsigned int PacketCount; /* 0x20410 */
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volatile unsigned int Ok2Use; /* 0x20414 */
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volatile unsigned int LanDmaCtl; /* 0x20418 */
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volatile unsigned int Timeout; /* 0x2041c */
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volatile unsigned int DmaStatus; /* 0x20420 */
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volatile unsigned int DmaTest; /* 0x20424 */
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volatile unsigned char filler20428[0x20430 - 0x20428];
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volatile unsigned int PauseCount; /* 0x20430 */
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volatile unsigned int RemotePauseCount; /* 0x20434 */
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volatile unsigned char filler20438[0x20440 - 0x20438];
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volatile unsigned int MacCtl; /* 0x20440 */
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volatile unsigned int CamCtl; /* 0x20444 */
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volatile unsigned int TxCtl; /* 0x20448 */
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volatile unsigned int TxStatus; /* 0x2044c */
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volatile unsigned int RxCtl; /* 0x20450 */
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volatile unsigned int RxStatus; /* 0x20454 */
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volatile unsigned int StationMgmtData; /* 0x20458 */
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volatile unsigned int StationMgmtCtl; /* 0x2045c */
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volatile unsigned int CamAddress; /* 0x20460 */
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volatile unsigned int CamData; /* 0x20464 */
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volatile unsigned int CamEnable; /* 0x20468 */
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volatile unsigned char filler2046c[0x20500 - 0x2046c];
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volatile unsigned int DebugPCIMasterAddr; /* 0x20500 */
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volatile unsigned int DebugLanTxStateMachine; /* 0x20504 */
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volatile unsigned int DebugLanRxStateMachine; /* 0x20508 */
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volatile unsigned int DebugLanTxFifoPointers; /* 0x2050c */
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volatile unsigned int DebugLanRxFifoPointers; /* 0x20510 */
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volatile unsigned int DebugLanCtlStateMachine; /* 0x20514 */
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};
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typedef volatile struct lan_saa9730_regmap t_lan_saa9730_regmap;
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/* EVM interrupt control registers. */
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#define EVM_LAN_INT 0x00010000
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#define EVM_MASTER_EN 0x00000001
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/* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */
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#define SAA9730_EVM_REGS_ADDR 0x02000
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struct evm_saa9730_regmap {
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volatile unsigned int InterruptStatus1; /* 0x2000 */
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volatile unsigned int InterruptEnable1; /* 0x2004 */
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volatile unsigned int InterruptMonitor1; /* 0x2008 */
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volatile unsigned int Counter; /* 0x200c */
|
||
|
|
volatile unsigned int CounterThreshold; /* 0x2010 */
|
||
|
|
volatile unsigned int CounterControl; /* 0x2014 */
|
||
|
|
volatile unsigned int GpioControl1; /* 0x2018 */
|
||
|
|
volatile unsigned int InterruptStatus2; /* 0x201c */
|
||
|
|
volatile unsigned int InterruptEnable2; /* 0x2020 */
|
||
|
|
volatile unsigned int InterruptMonitor2; /* 0x2024 */
|
||
|
|
volatile unsigned int GpioControl2; /* 0x2028 */
|
||
|
|
volatile unsigned int InterruptBlock1; /* 0x202c */
|
||
|
|
volatile unsigned int InterruptBlock2; /* 0x2030 */
|
||
|
|
};
|
||
|
|
typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap;
|
||
|
|
|
||
|
|
|
||
|
|
struct lan_saa9730_private {
|
||
|
|
/* Pointer for the SAA9730 LAN controller register set. */
|
||
|
|
t_lan_saa9730_regmap *lan_saa9730_regs;
|
||
|
|
|
||
|
|
/* Pointer to the SAA9730 EVM register. */
|
||
|
|
t_evm_saa9730_regmap *evm_saa9730_regs;
|
||
|
|
|
||
|
|
/* TRUE if the next buffer to write is RxBuffA, FALSE if RxBuffB. */
|
||
|
|
unsigned char NextRcvToUseIsA;
|
||
|
|
/* Rcv buffer Index. */
|
||
|
|
unsigned char NextRcvPacketIndex;
|
||
|
|
|
||
|
|
/* Index of next packet to use in that buffer. */
|
||
|
|
unsigned char NextTxmPacketIndex;
|
||
|
|
/* Next buffer index. */
|
||
|
|
unsigned char NextTxmBufferIndex;
|
||
|
|
|
||
|
|
/* Index of first pending packet ready to send. */
|
||
|
|
unsigned char PendingTxmPacketIndex;
|
||
|
|
/* Pending buffer index. */
|
||
|
|
unsigned char PendingTxmBufferIndex;
|
||
|
|
|
||
|
|
unsigned char DmaRcvPackets;
|
||
|
|
unsigned char DmaTxmPackets;
|
||
|
|
|
||
|
|
unsigned char RcvAIndex; /* index into RcvBufferSpace[] for Blk A */
|
||
|
|
unsigned char RcvBIndex; /* index into RcvBufferSpace[] for Blk B */
|
||
|
|
|
||
|
|
unsigned int
|
||
|
|
TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE];
|
||
|
|
unsigned int
|
||
|
|
RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE];
|
||
|
|
unsigned int TxBufferFree[LAN_SAA9730_BUFFERS];
|
||
|
|
|
||
|
|
unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6];
|
||
|
|
|
||
|
|
struct net_device_stats stats;
|
||
|
|
spinlock_t lock;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* _SAA9730_H */
|