2006-12-07 18:14:16 -05:00
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/*
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* drivers/ata/pata_mpc52xx.c
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*
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* libata driver for the Freescale MPC52xx on-chip IDE interface
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*
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* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/libata.h>
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#include <asm/types.h>
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#include <asm/prom.h>
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#include <asm/of_platform.h>
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#include <asm/mpc52xx.h>
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#define DRV_NAME "mpc52xx_ata"
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#define DRV_VERSION "0.1.0"
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/* Private structures used by the driver */
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struct mpc52xx_ata_timings {
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u32 pio1;
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u32 pio2;
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};
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struct mpc52xx_ata_priv {
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unsigned int ipb_period;
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struct mpc52xx_ata __iomem * ata_regs;
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int ata_irq;
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struct mpc52xx_ata_timings timings[2];
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int csel;
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};
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/* ATAPI-4 PIO specs (in ns) */
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static const int ataspec_t0[5] = {600, 383, 240, 180, 120};
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static const int ataspec_t1[5] = { 70, 50, 30, 30, 25};
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static const int ataspec_t2_8[5] = {290, 290, 290, 80, 70};
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static const int ataspec_t2_16[5] = {165, 125, 100, 80, 70};
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static const int ataspec_t2i[5] = { 0, 0, 0, 70, 25};
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static const int ataspec_t4[5] = { 30, 20, 15, 10, 10};
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static const int ataspec_ta[5] = { 35, 35, 35, 35, 35};
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#define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
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/* Bit definitions inside the registers */
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#define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
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#define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
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#define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
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#define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
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#define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
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#define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
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#define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
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#define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
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#define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
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#define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
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#define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
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#define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
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#define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
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#define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
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#define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
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#define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
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/* Structure of the hardware registers */
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struct mpc52xx_ata {
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/* Host interface registers */
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u32 config; /* ATA + 0x00 Host configuration */
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u32 host_status; /* ATA + 0x04 Host controller status */
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u32 pio1; /* ATA + 0x08 PIO Timing 1 */
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u32 pio2; /* ATA + 0x0c PIO Timing 2 */
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u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
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u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
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u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
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u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
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u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
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u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
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u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
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u32 share_cnt; /* ATA + 0x2c ATA share counter */
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u32 reserved0[3];
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/* FIFO registers */
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u32 fifo_data; /* ATA + 0x3c */
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u8 fifo_status_frame; /* ATA + 0x40 */
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u8 fifo_status; /* ATA + 0x41 */
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u16 reserved7[1];
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u8 fifo_control; /* ATA + 0x44 */
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u8 reserved8[5];
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u16 fifo_alarm; /* ATA + 0x4a */
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u16 reserved9;
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u16 fifo_rdp; /* ATA + 0x4e */
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u16 reserved10;
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u16 fifo_wrp; /* ATA + 0x52 */
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u16 reserved11;
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u16 fifo_lfrdp; /* ATA + 0x56 */
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u16 reserved12;
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u16 fifo_lfwrp; /* ATA + 0x5a */
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/* Drive TaskFile registers */
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u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
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u8 reserved13[3];
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u16 tf_data; /* ATA + 0x60 TASKFILE Data */
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u16 reserved14;
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u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
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u8 reserved15[3];
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u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
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u8 reserved16[3];
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u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
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u8 reserved17[3];
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u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
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u8 reserved18[3];
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u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
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u8 reserved19[3];
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u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
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u8 reserved20[3];
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u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
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u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
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u8 reserved21[2];
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};
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/* ======================================================================== */
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/* Aux fns */
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/* ======================================================================== */
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/* MPC52xx low level hw control */
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static int
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mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
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{
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struct mpc52xx_ata_timings *timing = &priv->timings[dev];
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unsigned int ipb_period = priv->ipb_period;
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unsigned int t0, t1, t2_8, t2_16, t2i, t4, ta;
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if ((pio<0) || (pio>4))
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return -EINVAL;
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t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
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t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
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t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
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t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
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t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
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t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
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ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
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timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
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timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
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return 0;
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}
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static void
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mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
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{
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struct mpc52xx_ata __iomem *regs = priv->ata_regs;
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struct mpc52xx_ata_timings *timing = &priv->timings[device];
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out_be32(®s->pio1, timing->pio1);
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out_be32(®s->pio2, timing->pio2);
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out_be32(®s->mdma1, 0);
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out_be32(®s->mdma2, 0);
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out_be32(®s->udma1, 0);
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out_be32(®s->udma2, 0);
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out_be32(®s->udma3, 0);
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out_be32(®s->udma4, 0);
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out_be32(®s->udma5, 0);
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priv->csel = device;
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}
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static int
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mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
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{
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struct mpc52xx_ata __iomem *regs = priv->ata_regs;
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int tslot;
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/* Clear share_cnt (all sample code do this ...) */
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out_be32(®s->share_cnt, 0);
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/* Configure and reset host */
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out_be32(®s->config,
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MPC52xx_ATA_HOSTCONF_IE |
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MPC52xx_ATA_HOSTCONF_IORDY |
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MPC52xx_ATA_HOSTCONF_SMR |
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MPC52xx_ATA_HOSTCONF_FR);
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udelay(10);
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out_be32(®s->config,
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MPC52xx_ATA_HOSTCONF_IE |
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MPC52xx_ATA_HOSTCONF_IORDY);
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/* Set the time slot to 1us */
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tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
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out_be32(®s->share_cnt, tslot << 16 );
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/* Init timings to PIO0 */
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memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
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mpc52xx_ata_compute_pio_timings(priv, 0, 0);
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mpc52xx_ata_compute_pio_timings(priv, 1, 0);
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mpc52xx_ata_apply_timings(priv, 0);
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return 0;
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}
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/* ======================================================================== */
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/* libata driver */
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/* ======================================================================== */
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static void
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mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct mpc52xx_ata_priv *priv = ap->host->private_data;
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int pio, rv;
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pio = adev->pio_mode - XFER_PIO_0;
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rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
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if (rv) {
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printk(KERN_ERR DRV_NAME
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": Trying to select invalid PIO mode %d\n", pio);
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return;
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}
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mpc52xx_ata_apply_timings(priv, adev->devno);
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}
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static void
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mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
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{
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struct mpc52xx_ata_priv *priv = ap->host->private_data;
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if (device != priv->csel)
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mpc52xx_ata_apply_timings(priv, device);
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ata_std_dev_select(ap,device);
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}
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static void
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mpc52xx_ata_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
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ata_std_postreset);
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}
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static struct scsi_host_template mpc52xx_ata_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations mpc52xx_ata_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = mpc52xx_ata_set_piomode,
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.dev_select = mpc52xx_ata_dev_select,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = mpc52xx_ata_error_handler,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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2007-02-01 01:06:36 -05:00
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.data_xfer = ata_data_xfer,
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2006-12-07 18:14:16 -05:00
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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2007-01-26 02:27:58 -05:00
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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2006-12-07 18:14:16 -05:00
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.port_start = ata_port_start,
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};
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static struct ata_probe_ent mpc52xx_ata_probe_ent = {
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.port_ops = &mpc52xx_ata_port_ops,
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.sht = &mpc52xx_ata_sht,
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.n_ports = 1,
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.pio_mask = 0x1f, /* Up to PIO4 */
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.mwdma_mask = 0x00, /* No MWDMA */
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.udma_mask = 0x00, /* No UDMA */
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.port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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2006-12-07 18:14:16 -05:00
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.irq_flags = 0,
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};
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static int __devinit
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mpc52xx_ata_init_one(struct device *dev, struct mpc52xx_ata_priv *priv)
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{
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struct ata_probe_ent *ae = &mpc52xx_ata_probe_ent;
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struct ata_ioports *aio = &ae->port[0];
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int rv;
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INIT_LIST_HEAD(&ae->node);
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ae->dev = dev;
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ae->irq = priv->ata_irq;
|
|
|
|
|
|
|
|
aio->cmd_addr = 0; /* Don't have a classic reg block */
|
2007-02-01 01:06:36 -05:00
|
|
|
aio->altstatus_addr = &priv->ata_regs->tf_control;
|
|
|
|
aio->ctl_addr = &priv->ata_regs->tf_control;
|
|
|
|
aio->data_addr = &priv->ata_regs->tf_data;
|
|
|
|
aio->error_addr = &priv->ata_regs->tf_features;
|
|
|
|
aio->feature_addr = &priv->ata_regs->tf_features;
|
|
|
|
aio->nsect_addr = &priv->ata_regs->tf_sec_count;
|
|
|
|
aio->lbal_addr = &priv->ata_regs->tf_sec_num;
|
|
|
|
aio->lbam_addr = &priv->ata_regs->tf_cyl_low;
|
|
|
|
aio->lbah_addr = &priv->ata_regs->tf_cyl_high;
|
|
|
|
aio->device_addr = &priv->ata_regs->tf_dev_head;
|
|
|
|
aio->status_addr = &priv->ata_regs->tf_command;
|
|
|
|
aio->command_addr = &priv->ata_regs->tf_command;
|
2006-12-07 18:14:16 -05:00
|
|
|
|
|
|
|
ae->private_data = priv;
|
|
|
|
|
|
|
|
rv = ata_device_add(ae);
|
|
|
|
|
|
|
|
return rv ? 0 : -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct mpc52xx_ata_priv *
|
|
|
|
mpc52xx_ata_remove_one(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
|
|
struct mpc52xx_ata_priv *priv = host->private_data;
|
|
|
|
|
2007-01-20 02:00:28 -05:00
|
|
|
ata_host_detach(host);
|
2006-12-07 18:14:16 -05:00
|
|
|
|
|
|
|
return priv;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
/* OF Platform driver */
|
|
|
|
/* ======================================================================== */
|
|
|
|
|
|
|
|
static int __devinit
|
|
|
|
mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
|
|
|
|
{
|
|
|
|
unsigned int ipb_freq;
|
|
|
|
struct resource res_mem;
|
|
|
|
int ata_irq = NO_IRQ;
|
2007-01-20 02:00:28 -05:00
|
|
|
struct mpc52xx_ata __iomem *ata_regs;
|
|
|
|
struct mpc52xx_ata_priv *priv;
|
2006-12-07 18:14:16 -05:00
|
|
|
int rv;
|
|
|
|
|
|
|
|
/* Get ipb frequency */
|
|
|
|
ipb_freq = mpc52xx_find_ipb_freq(op->node);
|
|
|
|
if (!ipb_freq) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": "
|
|
|
|
"Unable to find IPB Bus frequency\n" );
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get IRQ and register */
|
|
|
|
rv = of_address_to_resource(op->node, 0, &res_mem);
|
|
|
|
if (rv) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": "
|
|
|
|
"Error while parsing device node resource\n" );
|
|
|
|
return rv;
|
|
|
|
}
|
|
|
|
|
|
|
|
ata_irq = irq_of_parse_and_map(op->node, 0);
|
|
|
|
if (ata_irq == NO_IRQ) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": "
|
|
|
|
"Error while mapping the irq\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Request mem region */
|
2007-01-20 02:00:28 -05:00
|
|
|
if (!devm_request_mem_region(&op->dev, res_mem.start,
|
|
|
|
sizeof(struct mpc52xx_ata), DRV_NAME)) {
|
2006-12-07 18:14:16 -05:00
|
|
|
printk(KERN_ERR DRV_NAME ": "
|
|
|
|
"Error while requesting mem region\n");
|
2007-01-20 02:00:28 -05:00
|
|
|
rv = -EBUSY;
|
|
|
|
goto err;
|
2006-12-07 18:14:16 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Remap registers */
|
2007-01-20 02:00:28 -05:00
|
|
|
ata_regs = devm_ioremap(&op->dev, res_mem.start,
|
|
|
|
sizeof(struct mpc52xx_ata));
|
2006-12-07 18:14:16 -05:00
|
|
|
if (!ata_regs) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": "
|
|
|
|
"Error while mapping register set\n");
|
|
|
|
rv = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Prepare our private structure */
|
2007-01-20 02:00:28 -05:00
|
|
|
priv = devm_kzalloc(&op->dev, sizeof(struct mpc52xx_ata_priv),
|
|
|
|
GFP_ATOMIC);
|
2006-12-07 18:14:16 -05:00
|
|
|
if (!priv) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": "
|
|
|
|
"Error while allocating private structure\n");
|
|
|
|
rv = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->ipb_period = 1000000000 / (ipb_freq / 1000);
|
|
|
|
priv->ata_regs = ata_regs;
|
|
|
|
priv->ata_irq = ata_irq;
|
|
|
|
priv->csel = -1;
|
|
|
|
|
|
|
|
/* Init the hw */
|
|
|
|
rv = mpc52xx_ata_hw_init(priv);
|
|
|
|
if (rv) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": Error during HW init\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Register ourselves to libata */
|
|
|
|
rv = mpc52xx_ata_init_one(&op->dev, priv);
|
|
|
|
if (rv) {
|
|
|
|
printk(KERN_ERR DRV_NAME ": "
|
|
|
|
"Error while registering to ATA layer\n");
|
|
|
|
return rv;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Done */
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Error path */
|
|
|
|
err:
|
|
|
|
irq_dispose_mapping(ata_irq);
|
|
|
|
return rv;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc52xx_ata_remove(struct of_device *op)
|
|
|
|
{
|
|
|
|
struct mpc52xx_ata_priv *priv;
|
|
|
|
|
|
|
|
priv = mpc52xx_ata_remove_one(&op->dev);
|
|
|
|
irq_dispose_mapping(priv->ata_irq);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
|
|
|
|
{
|
|
|
|
return 0; /* FIXME : What to do here ? */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mpc52xx_ata_resume(struct of_device *op)
|
|
|
|
{
|
|
|
|
return 0; /* FIXME : What to do here ? */
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
static struct of_device_id mpc52xx_ata_of_match[] = {
|
|
|
|
{
|
2007-02-12 15:36:55 -05:00
|
|
|
.type = "ata",
|
|
|
|
.compatible = "mpc5200-ata",
|
2006-12-07 18:14:16 -05:00
|
|
|
},
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.match_table = mpc52xx_ata_of_match,
|
|
|
|
.probe = mpc52xx_ata_probe,
|
|
|
|
.remove = mpc52xx_ata_remove,
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
.suspend = mpc52xx_ata_suspend,
|
|
|
|
.resume = mpc52xx_ata_resume,
|
|
|
|
#endif
|
|
|
|
.driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* ======================================================================== */
|
|
|
|
/* Module */
|
|
|
|
/* ======================================================================== */
|
|
|
|
|
|
|
|
static int __init
|
|
|
|
mpc52xx_ata_init(void)
|
|
|
|
{
|
|
|
|
printk(KERN_INFO "ata: MPC52xx IDE/ATA libata driver\n");
|
|
|
|
return of_register_platform_driver(&mpc52xx_ata_of_platform_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit
|
|
|
|
mpc52xx_ata_exit(void)
|
|
|
|
{
|
|
|
|
of_unregister_platform_driver(&mpc52xx_ata_of_platform_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(mpc52xx_ata_init);
|
|
|
|
module_exit(mpc52xx_ata_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
|
|
|
|
MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|