2009-01-07 10:14:38 -05:00
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/* mach/dma.h - arch-specific DMA defines
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2008-11-18 04:48:21 -05:00
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*
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2009-01-07 10:14:38 -05:00
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* Copyright 2004-2008 Analog Devices Inc.
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2008-11-18 04:48:21 -05:00
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*
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2009-01-07 10:14:38 -05:00
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* Licensed under the GPL-2 or later.
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2008-11-18 04:48:21 -05:00
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*/
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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2009-01-07 10:14:39 -05:00
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#define MAX_DMA_CHANNELS 16
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2008-11-18 04:48:21 -05:00
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#define CH_PPI 0 /* PPI receive/transmit */
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#define CH_EMAC_RX 1 /* Ethernet MAC receive */
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#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
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#define CH_SPORT0_RX 3 /* SPORT0 receive */
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#define CH_SPORT0_TX 4 /* SPORT0 transmit */
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#define CH_RSI 4 /* RSI */
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#define CH_SPORT1_RX 5 /* SPORT1 receive */
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#define CH_SPI1 5 /* SPI1 transmit/receive */
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#define CH_SPORT1_TX 6 /* SPORT1 transmit */
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#define CH_SPI0 7 /* SPI0 transmit/receive */
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#define CH_UART0_RX 8 /* UART0 receive */
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#define CH_UART0_TX 9 /* UART0 transmit */
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#define CH_UART1_RX 10 /* UART1 receive */
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#define CH_UART1_TX 11 /* UART1 transmit */
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#define CH_MEM_STREAM0_SRC 12 /* RX */
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#define CH_MEM_STREAM0_DEST 13 /* TX */
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#define CH_MEM_STREAM1_SRC 14 /* RX */
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#define CH_MEM_STREAM1_DEST 15 /* TX */
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#endif
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