2006-12-01 19:36:17 -05:00
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/* $Date: 2005/11/12 02:13:49 $ $RCSfile: ixf1010.c,v $ $Revision: 1.36 $ */
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#include "gmac.h"
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#include "elmer0.h"
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/* Update fast changing statistics every 15 seconds */
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#define STATS_TICK_SECS 15
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/* 30 minutes for full statistics update */
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#define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS)
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/*
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* The IXF1010 can handle frames up to 16383 bytes but it's optimized for
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* frames up to 9831 (0x2667) bytes, so we limit jumbo frame size to this.
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* This length includes ethernet header and FCS.
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*/
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#define MAX_FRAME_SIZE 0x2667
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/* MAC registers */
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enum {
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/* Per-port registers */
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REG_MACADDR_LOW = 0,
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REG_MACADDR_HIGH = 0x4,
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REG_FDFC_TYPE = 0xC,
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REG_FC_TX_TIMER_VALUE = 0x1c,
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REG_IPG_RX_TIME1 = 0x28,
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REG_IPG_RX_TIME2 = 0x2c,
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REG_IPG_TX_TIME = 0x30,
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REG_PAUSE_THRES = 0x38,
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REG_MAX_FRAME_SIZE = 0x3c,
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REG_RGMII_SPEED = 0x40,
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REG_FC_ENABLE = 0x48,
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REG_DISCARD_CTRL_FRAMES = 0x54,
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REG_DIVERSE_CONFIG = 0x60,
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REG_RX_FILTER = 0x64,
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REG_MC_ADDR_LOW = 0x68,
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REG_MC_ADDR_HIGH = 0x6c,
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REG_RX_OCTETS_OK = 0x80,
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REG_RX_OCTETS_BAD = 0x84,
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REG_RX_UC_PKTS = 0x88,
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REG_RX_MC_PKTS = 0x8c,
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REG_RX_BC_PKTS = 0x90,
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REG_RX_FCS_ERR = 0xb0,
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REG_RX_TAGGED = 0xb4,
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REG_RX_DATA_ERR = 0xb8,
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REG_RX_ALIGN_ERR = 0xbc,
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REG_RX_LONG_ERR = 0xc0,
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REG_RX_JABBER_ERR = 0xc4,
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REG_RX_PAUSE_FRAMES = 0xc8,
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REG_RX_UNKNOWN_CTRL_FRAMES = 0xcc,
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REG_RX_VERY_LONG_ERR = 0xd0,
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REG_RX_RUNT_ERR = 0xd4,
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REG_RX_SHORT_ERR = 0xd8,
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REG_RX_SYMBOL_ERR = 0xe4,
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REG_TX_OCTETS_OK = 0x100,
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REG_TX_OCTETS_BAD = 0x104,
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REG_TX_UC_PKTS = 0x108,
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REG_TX_MC_PKTS = 0x10c,
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REG_TX_BC_PKTS = 0x110,
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REG_TX_EXCESSIVE_LEN_DROP = 0x14c,
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REG_TX_UNDERRUN = 0x150,
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REG_TX_TAGGED = 0x154,
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REG_TX_PAUSE_FRAMES = 0x15C,
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/* Global registers */
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REG_PORT_ENABLE = 0x1400,
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REG_JTAG_ID = 0x1430,
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RX_FIFO_HIGH_WATERMARK_BASE = 0x1600,
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RX_FIFO_LOW_WATERMARK_BASE = 0x1628,
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RX_FIFO_FRAMES_REMOVED_BASE = 0x1650,
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REG_RX_ERR_DROP = 0x167c,
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REG_RX_FIFO_OVERFLOW_EVENT = 0x1680,
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TX_FIFO_HIGH_WATERMARK_BASE = 0x1800,
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TX_FIFO_LOW_WATERMARK_BASE = 0x1828,
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TX_FIFO_XFER_THRES_BASE = 0x1850,
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REG_TX_FIFO_OVERFLOW_EVENT = 0x1878,
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REG_TX_FIFO_OOS_EVENT = 0x1884,
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TX_FIFO_FRAMES_REMOVED_BASE = 0x1888,
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REG_SPI_RX_BURST = 0x1c00,
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REG_SPI_RX_TRAINING = 0x1c04,
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REG_SPI_RX_CALENDAR = 0x1c08,
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REG_SPI_TX_SYNC = 0x1c0c
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};
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enum { /* RMON registers */
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REG_RxOctetsTotalOK = 0x80,
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REG_RxOctetsBad = 0x84,
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REG_RxUCPkts = 0x88,
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REG_RxMCPkts = 0x8c,
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REG_RxBCPkts = 0x90,
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REG_RxJumboPkts = 0xac,
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REG_RxFCSErrors = 0xb0,
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REG_RxDataErrors = 0xb8,
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REG_RxAlignErrors = 0xbc,
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REG_RxLongErrors = 0xc0,
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REG_RxJabberErrors = 0xc4,
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REG_RxPauseMacControlCounter = 0xc8,
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REG_RxVeryLongErrors = 0xd0,
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REG_RxRuntErrors = 0xd4,
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REG_RxShortErrors = 0xd8,
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REG_RxSequenceErrors = 0xe0,
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REG_RxSymbolErrors = 0xe4,
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REG_TxOctetsTotalOK = 0x100,
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REG_TxOctetsBad = 0x104,
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REG_TxUCPkts = 0x108,
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REG_TxMCPkts = 0x10c,
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REG_TxBCPkts = 0x110,
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REG_TxJumboPkts = 0x12C,
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REG_TxTotalCollisions = 0x134,
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REG_TxExcessiveLengthDrop = 0x14c,
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REG_TxUnderrun = 0x150,
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REG_TxCRCErrors = 0x158,
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REG_TxPauseFrames = 0x15c
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};
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enum {
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DIVERSE_CONFIG_PAD_ENABLE = 0x80,
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DIVERSE_CONFIG_CRC_ADD = 0x40
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};
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#define MACREG_BASE 0
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#define MACREG(mac, mac_reg) ((mac)->instance->mac_base + (mac_reg))
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struct _cmac_instance {
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u32 mac_base;
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u32 index;
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u32 version;
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u32 ticks;
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};
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static void disable_port(struct cmac *mac)
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{
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u32 val;
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t1_tpi_read(mac->adapter, REG_PORT_ENABLE, &val);
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val &= ~(1 << mac->instance->index);
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t1_tpi_write(mac->adapter, REG_PORT_ENABLE, val);
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}
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#define RMON_UPDATE(mac, name, stat_name) \
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t1_tpi_read((mac)->adapter, MACREG(mac, REG_##name), &val); \
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(mac)->stats.stat_name += val;
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/*
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* Read the current values of the RMON counters and add them to the cumulative
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* port statistics. The HW RMON counters are cleared by this operation.
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*/
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static void port_stats_update(struct cmac *mac)
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{
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u32 val;
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/* Rx stats */
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RMON_UPDATE(mac, RxOctetsTotalOK, RxOctetsOK);
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RMON_UPDATE(mac, RxOctetsBad, RxOctetsBad);
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RMON_UPDATE(mac, RxUCPkts, RxUnicastFramesOK);
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RMON_UPDATE(mac, RxMCPkts, RxMulticastFramesOK);
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RMON_UPDATE(mac, RxBCPkts, RxBroadcastFramesOK);
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RMON_UPDATE(mac, RxJumboPkts, RxJumboFramesOK);
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RMON_UPDATE(mac, RxFCSErrors, RxFCSErrors);
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RMON_UPDATE(mac, RxAlignErrors, RxAlignErrors);
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RMON_UPDATE(mac, RxLongErrors, RxFrameTooLongErrors);
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RMON_UPDATE(mac, RxVeryLongErrors, RxFrameTooLongErrors);
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RMON_UPDATE(mac, RxPauseMacControlCounter, RxPauseFrames);
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RMON_UPDATE(mac, RxDataErrors, RxDataErrors);
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RMON_UPDATE(mac, RxJabberErrors, RxJabberErrors);
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RMON_UPDATE(mac, RxRuntErrors, RxRuntErrors);
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RMON_UPDATE(mac, RxShortErrors, RxRuntErrors);
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RMON_UPDATE(mac, RxSequenceErrors, RxSequenceErrors);
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RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
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/* Tx stats (skip collision stats as we are full-duplex only) */
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RMON_UPDATE(mac, TxOctetsTotalOK, TxOctetsOK);
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RMON_UPDATE(mac, TxOctetsBad, TxOctetsBad);
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RMON_UPDATE(mac, TxUCPkts, TxUnicastFramesOK);
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RMON_UPDATE(mac, TxMCPkts, TxMulticastFramesOK);
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RMON_UPDATE(mac, TxBCPkts, TxBroadcastFramesOK);
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RMON_UPDATE(mac, TxJumboPkts, TxJumboFramesOK);
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RMON_UPDATE(mac, TxPauseFrames, TxPauseFrames);
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RMON_UPDATE(mac, TxExcessiveLengthDrop, TxLengthErrors);
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RMON_UPDATE(mac, TxUnderrun, TxUnderrun);
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RMON_UPDATE(mac, TxCRCErrors, TxFCSErrors);
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}
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/* No-op interrupt operation as this MAC does not support interrupts */
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static int mac_intr_op(struct cmac *mac)
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{
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return 0;
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}
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/* Expect MAC address to be in network byte order. */
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static int mac_set_address(struct cmac *mac, u8 addr[6])
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{
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u32 addr_lo, addr_hi;
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addr_lo = addr[2];
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addr_lo = (addr_lo << 8) | addr[3];
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addr_lo = (addr_lo << 8) | addr[4];
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addr_lo = (addr_lo << 8) | addr[5];
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addr_hi = addr[0];
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addr_hi = (addr_hi << 8) | addr[1];
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t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_LOW), addr_lo);
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t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), addr_hi);
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return 0;
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}
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static int mac_get_address(struct cmac *mac, u8 addr[6])
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{
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u32 addr_lo, addr_hi;
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t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_LOW), &addr_lo);
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t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), &addr_hi);
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addr[0] = (u8) (addr_hi >> 8);
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addr[1] = (u8) addr_hi;
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addr[2] = (u8) (addr_lo >> 24);
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addr[3] = (u8) (addr_lo >> 16);
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addr[4] = (u8) (addr_lo >> 8);
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addr[5] = (u8) addr_lo;
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return 0;
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}
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/* This is intended to reset a port, not the whole MAC */
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static int mac_reset(struct cmac *mac)
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{
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return 0;
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}
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static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
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{
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u32 val, new_mode;
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adapter_t *adapter = mac->adapter;
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u32 addr_lo, addr_hi;
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u8 *addr;
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t1_tpi_read(adapter, MACREG(mac, REG_RX_FILTER), &val);
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new_mode = val & ~7;
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if (!t1_rx_mode_promisc(rm) && mac->instance->version > 0)
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new_mode |= 1; /* only set if version > 0 due to erratum */
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if (!t1_rx_mode_promisc(rm) && !t1_rx_mode_allmulti(rm)
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&& t1_rx_mode_mc_cnt(rm) <= 1)
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new_mode |= 2;
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if (new_mode != val)
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t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), new_mode);
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switch (t1_rx_mode_mc_cnt(rm)) {
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case 0:
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t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), 0);
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t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), 0);
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break;
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case 1:
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addr = t1_get_next_mcaddr(rm);
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addr_lo = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
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addr[5];
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addr_hi = (addr[0] << 8) | addr[1];
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t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), addr_lo);
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t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), addr_hi);
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break;
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default:
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break;
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}
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return 0;
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}
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static int mac_set_mtu(struct cmac *mac, int mtu)
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{
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/* MAX_FRAME_SIZE inludes header + FCS, mtu doesn't */
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2006-12-05 16:38:00 -05:00
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if (mtu > (MAX_FRAME_SIZE - 14 - 4))
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return -EINVAL;
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2006-12-01 19:36:17 -05:00
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t1_tpi_write(mac->adapter, MACREG(mac, REG_MAX_FRAME_SIZE),
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mtu + 14 + 4);
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return 0;
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}
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static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
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int fc)
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{
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u32 val;
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if (speed >= 0 && speed != SPEED_100 && speed != SPEED_1000)
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return -1;
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if (duplex >= 0 && duplex != DUPLEX_FULL)
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return -1;
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if (speed >= 0) {
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val = speed == SPEED_100 ? 1 : 2;
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t1_tpi_write(mac->adapter, MACREG(mac, REG_RGMII_SPEED), val);
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}
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t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val);
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val &= ~3;
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if (fc & PAUSE_RX)
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val |= 1;
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if (fc & PAUSE_TX)
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val |= 2;
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t1_tpi_write(mac->adapter, MACREG(mac, REG_FC_ENABLE), val);
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return 0;
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}
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static int mac_get_speed_duplex_fc(struct cmac *mac, int *speed, int *duplex,
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int *fc)
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{
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u32 val;
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if (duplex)
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*duplex = DUPLEX_FULL;
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if (speed) {
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t1_tpi_read(mac->adapter, MACREG(mac, REG_RGMII_SPEED),
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&val);
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*speed = (val & 2) ? SPEED_1000 : SPEED_100;
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}
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if (fc) {
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t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val);
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*fc = 0;
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if (val & 1)
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*fc |= PAUSE_RX;
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if (val & 2)
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*fc |= PAUSE_TX;
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}
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return 0;
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}
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static void enable_port(struct cmac *mac)
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{
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u32 val;
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u32 index = mac->instance->index;
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adapter_t *adapter = mac->adapter;
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|
|
|
|
t1_tpi_read(adapter, MACREG(mac, REG_DIVERSE_CONFIG), &val);
|
|
|
|
val |= DIVERSE_CONFIG_CRC_ADD | DIVERSE_CONFIG_PAD_ENABLE;
|
|
|
|
t1_tpi_write(adapter, MACREG(mac, REG_DIVERSE_CONFIG), val);
|
|
|
|
if (mac->instance->version > 0)
|
|
|
|
t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 3);
|
|
|
|
else /* Don't enable unicast address filtering due to IXF1010 bug */
|
|
|
|
t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 2);
|
|
|
|
|
|
|
|
t1_tpi_read(adapter, REG_RX_ERR_DROP, &val);
|
|
|
|
val |= (1 << index);
|
|
|
|
t1_tpi_write(adapter, REG_RX_ERR_DROP, val);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the port RMON registers by adding their current values to the
|
|
|
|
* cumulatice port stats and then clearing the stats. Really.
|
|
|
|
*/
|
|
|
|
port_stats_update(mac);
|
|
|
|
memset(&mac->stats, 0, sizeof(struct cmac_statistics));
|
|
|
|
mac->instance->ticks = 0;
|
|
|
|
|
|
|
|
t1_tpi_read(adapter, REG_PORT_ENABLE, &val);
|
|
|
|
val |= (1 << index);
|
|
|
|
t1_tpi_write(adapter, REG_PORT_ENABLE, val);
|
|
|
|
|
2006-12-11 17:47:00 -05:00
|
|
|
index <<= 2;
|
|
|
|
if (is_T2(adapter)) {
|
2006-12-01 19:36:17 -05:00
|
|
|
/* T204: set the Fifo water level & threshold */
|
|
|
|
t1_tpi_write(adapter, RX_FIFO_HIGH_WATERMARK_BASE + index, 0x740);
|
|
|
|
t1_tpi_write(adapter, RX_FIFO_LOW_WATERMARK_BASE + index, 0x730);
|
|
|
|
t1_tpi_write(adapter, TX_FIFO_HIGH_WATERMARK_BASE + index, 0x600);
|
|
|
|
t1_tpi_write(adapter, TX_FIFO_LOW_WATERMARK_BASE + index, 0x1d0);
|
|
|
|
t1_tpi_write(adapter, TX_FIFO_XFER_THRES_BASE + index, 0x1100);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Set the TX Fifo Threshold to 0x400 instead of 0x100 to work around
|
|
|
|
* Underrun problem. Intel has blessed this solution.
|
|
|
|
*/
|
|
|
|
t1_tpi_write(adapter, TX_FIFO_XFER_THRES_BASE + index, 0x400);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* IXF1010 ports do not have separate enables for TX and RX */
|
|
|
|
static int mac_enable(struct cmac *mac, int which)
|
|
|
|
{
|
|
|
|
if (which & (MAC_DIRECTION_RX | MAC_DIRECTION_TX))
|
|
|
|
enable_port(mac);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mac_disable(struct cmac *mac, int which)
|
|
|
|
{
|
|
|
|
if (which & (MAC_DIRECTION_RX | MAC_DIRECTION_TX))
|
|
|
|
disable_port(mac);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is called periodically to accumulate the current values of the
|
|
|
|
* RMON counters into the port statistics. Since the counters are only 32 bits
|
|
|
|
* some of them can overflow in less than a minute at GigE speeds, so this
|
|
|
|
* function should be called every 30 seconds or so.
|
|
|
|
*
|
|
|
|
* To cut down on reading costs we update only the octet counters at each tick
|
|
|
|
* and do a full update at major ticks, which can be every 30 minutes or more.
|
|
|
|
*/
|
|
|
|
static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
|
|
|
|
int flag)
|
|
|
|
{
|
|
|
|
if (flag == MAC_STATS_UPDATE_FULL ||
|
|
|
|
MAJOR_UPDATE_TICKS <= mac->instance->ticks) {
|
|
|
|
port_stats_update(mac);
|
|
|
|
mac->instance->ticks = 0;
|
|
|
|
} else {
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
RMON_UPDATE(mac, RxOctetsTotalOK, RxOctetsOK);
|
|
|
|
RMON_UPDATE(mac, TxOctetsTotalOK, TxOctetsOK);
|
|
|
|
mac->instance->ticks++;
|
|
|
|
}
|
|
|
|
return &mac->stats;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mac_destroy(struct cmac *mac)
|
|
|
|
{
|
|
|
|
kfree(mac);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct cmac_ops ixf1010_ops = {
|
|
|
|
.destroy = mac_destroy,
|
|
|
|
.reset = mac_reset,
|
|
|
|
.interrupt_enable = mac_intr_op,
|
|
|
|
.interrupt_disable = mac_intr_op,
|
|
|
|
.interrupt_clear = mac_intr_op,
|
|
|
|
.enable = mac_enable,
|
|
|
|
.disable = mac_disable,
|
|
|
|
.set_mtu = mac_set_mtu,
|
|
|
|
.set_rx_mode = mac_set_rx_mode,
|
|
|
|
.set_speed_duplex_fc = mac_set_speed_duplex_fc,
|
|
|
|
.get_speed_duplex_fc = mac_get_speed_duplex_fc,
|
|
|
|
.statistics_update = mac_update_statistics,
|
|
|
|
.macaddress_get = mac_get_address,
|
|
|
|
.macaddress_set = mac_set_address,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int ixf1010_mac_reset(adapter_t *adapter)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
t1_tpi_read(adapter, A_ELMER0_GPO, &val);
|
|
|
|
if ((val & 1) != 0) {
|
|
|
|
val &= ~1;
|
|
|
|
t1_tpi_write(adapter, A_ELMER0_GPO, val);
|
|
|
|
udelay(2);
|
|
|
|
}
|
|
|
|
val |= 1;
|
|
|
|
t1_tpi_write(adapter, A_ELMER0_GPO, val);
|
|
|
|
udelay(2);
|
|
|
|
|
|
|
|
t1_tpi_write(adapter, REG_PORT_ENABLE, 0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct cmac *ixf1010_mac_create(adapter_t *adapter, int index)
|
|
|
|
{
|
|
|
|
struct cmac *mac;
|
|
|
|
u32 val;
|
|
|
|
|
2006-12-05 16:38:00 -05:00
|
|
|
if (index > 9)
|
|
|
|
return NULL;
|
2006-12-01 19:36:17 -05:00
|
|
|
|
|
|
|
mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL);
|
2006-12-05 16:38:00 -05:00
|
|
|
if (!mac)
|
|
|
|
return NULL;
|
2006-12-01 19:36:17 -05:00
|
|
|
|
|
|
|
mac->ops = &ixf1010_ops;
|
|
|
|
mac->instance = (cmac_instance *)(mac + 1);
|
|
|
|
|
|
|
|
mac->instance->mac_base = MACREG_BASE + (index * 0x200);
|
|
|
|
mac->instance->index = index;
|
|
|
|
mac->adapter = adapter;
|
|
|
|
mac->instance->ticks = 0;
|
|
|
|
|
|
|
|
t1_tpi_read(adapter, REG_JTAG_ID, &val);
|
|
|
|
mac->instance->version = val >> 28;
|
|
|
|
return mac;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct gmac t1_ixf1010_ops = {
|
|
|
|
STATS_TICK_SECS,
|
|
|
|
ixf1010_mac_create,
|
|
|
|
ixf1010_mac_reset
|
|
|
|
};
|