2005-10-10 08:36:14 -04:00
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains the system call entry code, context switch
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* code, and exception/interrupt return code for PowerPC.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <asm/unistd.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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2006-09-25 04:19:00 -04:00
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#include <asm/firmware.h>
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2005-10-10 08:36:14 -04:00
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/*
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* System calls.
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*/
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.section ".toc","aw"
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.SYS_CALL_TABLE:
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.tc .sys_call_table[TC],.sys_call_table
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/* This value is used to mark exception frames on the stack. */
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exception_marker:
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.tc ID_72656773_68657265[TC],0x7265677368657265
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.section ".text"
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.align 7
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#undef SHOW_SYSCALLS
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.globl system_call_common
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system_call_common:
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andi. r10,r12,MSR_PR
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mr r10,r1
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addi r1,r1,-INT_FRAME_SIZE
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beq- 1f
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ld r1,PACAKSAVE(r13)
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1: std r10,0(r1)
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2006-06-10 11:15:55 -04:00
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crclr so
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2005-10-10 08:36:14 -04:00
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std r11,_NIP(r1)
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std r12,_MSR(r1)
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std r0,GPR0(r1)
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std r10,GPR1(r1)
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powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 18:06:59 -05:00
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ACCOUNT_CPU_USER_ENTRY(r10, r11)
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2005-10-10 08:36:14 -04:00
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std r2,GPR2(r1)
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std r3,GPR3(r1)
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std r4,GPR4(r1)
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std r5,GPR5(r1)
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std r6,GPR6(r1)
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std r7,GPR7(r1)
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std r8,GPR8(r1)
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li r11,0
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std r11,GPR9(r1)
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std r11,GPR10(r1)
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std r11,GPR11(r1)
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std r11,GPR12(r1)
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std r9,GPR13(r1)
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mfcr r9
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mflr r10
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li r11,0xc01
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std r9,_CCR(r1)
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std r10,_LINK(r1)
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std r11,_TRAP(r1)
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mfxer r9
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mfctr r10
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std r9,_XER(r1)
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std r10,_CTR(r1)
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std r3,ORIG_GPR3(r1)
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ld r2,PACATOC(r13)
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addi r9,r1,STACK_FRAME_OVERHEAD
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ld r11,exception_marker@toc(r2)
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std r11,-16(r9) /* "regshere" marker */
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[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
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li r10,1
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stb r10,PACASOFTIRQEN(r13)
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stb r10,PACAHARDIRQEN(r13)
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std r10,SOFTE(r1)
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2005-10-10 08:36:14 -04:00
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#ifdef CONFIG_PPC_ISERIES
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2006-09-25 04:19:00 -04:00
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BEGIN_FW_FTR_SECTION
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2005-10-10 08:36:14 -04:00
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/* Hack for handling interrupts when soft-enabling on iSeries */
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cmpdi cr1,r0,0x5555 /* syscall 0x5555 */
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andi. r10,r12,MSR_PR /* from kernel */
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crand 4*cr0+eq,4*cr1+eq,4*cr0+eq
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2006-11-26 22:59:50 -05:00
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bne 2f
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b hardware_interrupt_entry
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2:
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2006-09-25 04:19:00 -04:00
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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2005-10-10 08:36:14 -04:00
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#endif
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mfmsr r11
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ori r11,r11,MSR_EE
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mtmsrd r11,1
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#ifdef SHOW_SYSCALLS
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bl .do_show_syscall
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REST_GPR(0,r1)
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REST_4GPRS(3,r1)
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REST_2GPRS(7,r1)
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addi r9,r1,STACK_FRAME_OVERHEAD
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#endif
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clrrdi r11,r1,THREAD_SHIFT
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ld r10,TI_FLAGS(r11)
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andi. r11,r10,_TIF_SYSCALL_T_OR_A
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bne- syscall_dotrace
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syscall_dotrace_cont:
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cmpldi 0,r0,NR_syscalls
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bge- syscall_enosys
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system_call: /* label this so stack traces look sane */
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/*
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* Need to vector to 32 Bit or default sys_call_table here,
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* based on caller's run-mode / personality.
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*/
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ld r11,.SYS_CALL_TABLE@toc(2)
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andi. r10,r10,_TIF_32BIT
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beq 15f
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addi r11,r11,8 /* use 32-bit syscall entries */
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clrldi r3,r3,32
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clrldi r4,r4,32
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clrldi r5,r5,32
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clrldi r6,r6,32
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clrldi r7,r7,32
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clrldi r8,r8,32
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15:
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slwi r0,r0,4
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ldx r10,r11,r0 /* Fetch system call handler [ptr] */
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mtctr r10
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bctrl /* Call handler */
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syscall_exit:
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[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
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std r3,RESULT(r1)
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2005-10-10 08:36:14 -04:00
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#ifdef SHOW_SYSCALLS
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bl .do_show_syscall_exit
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[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
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ld r3,RESULT(r1)
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2005-10-10 08:36:14 -04:00
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#endif
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clrrdi r12,r1,THREAD_SHIFT
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/* disable interrupts so current_thread_info()->flags can't change,
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and so that we don't get interrupted after loading SRR0/1. */
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ld r8,_MSR(r1)
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andi. r10,r8,MSR_RI
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beq- unrecov_restore
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mfmsr r10
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rldicl r10,r10,48,1
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rotldi r10,r10,16
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mtmsrd r10,1
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ld r9,TI_FLAGS(r12)
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[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
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li r11,-_LAST_ERRNO
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2006-03-07 21:24:22 -05:00
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andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
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2005-10-10 08:36:14 -04:00
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bne- syscall_exit_work
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[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
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|
cmpld r3,r11
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ld r5,_CCR(r1)
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bge- syscall_error
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syscall_error_cont:
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2005-10-10 08:36:14 -04:00
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ld r7,_NIP(r1)
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stdcx. r0,0,r1 /* to clear the reservation */
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andi. r6,r8,MSR_PR
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|
ld r4,_LINK(r1)
|
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 18:06:59 -05:00
|
|
|
beq- 1f
|
|
|
|
|
ACCOUNT_CPU_USER_EXIT(r11, r12)
|
|
|
|
|
ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
|
2005-10-10 08:36:14 -04:00
|
|
|
1: ld r2,GPR2(r1)
|
|
|
|
|
li r12,MSR_RI
|
2005-12-19 23:38:47 -05:00
|
|
|
andc r11,r10,r12
|
|
|
|
|
mtmsrd r11,1 /* clear MSR.RI */
|
2005-10-10 08:36:14 -04:00
|
|
|
ld r1,GPR1(r1)
|
|
|
|
|
mtlr r4
|
|
|
|
|
mtcr r5
|
|
|
|
|
mtspr SPRN_SRR0,r7
|
|
|
|
|
mtspr SPRN_SRR1,r8
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
syscall_error:
|
2005-10-10 08:36:14 -04:00
|
|
|
oris r5,r5,0x1000 /* Set SO bit in CR */
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
neg r3,r3
|
2005-10-10 08:36:14 -04:00
|
|
|
std r5,_CCR(r1)
|
|
|
|
|
b syscall_error_cont
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
|
2005-10-10 08:36:14 -04:00
|
|
|
/* Traced system call support */
|
|
|
|
|
syscall_dotrace:
|
|
|
|
|
bl .save_nvgprs
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
bl .do_syscall_trace_enter
|
|
|
|
|
ld r0,GPR0(r1) /* Restore original registers */
|
|
|
|
|
ld r3,GPR3(r1)
|
|
|
|
|
ld r4,GPR4(r1)
|
|
|
|
|
ld r5,GPR5(r1)
|
|
|
|
|
ld r6,GPR6(r1)
|
|
|
|
|
ld r7,GPR7(r1)
|
|
|
|
|
ld r8,GPR8(r1)
|
|
|
|
|
addi r9,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
clrrdi r10,r1,THREAD_SHIFT
|
|
|
|
|
ld r10,TI_FLAGS(r10)
|
|
|
|
|
b syscall_dotrace_cont
|
|
|
|
|
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
syscall_enosys:
|
|
|
|
|
li r3,-ENOSYS
|
|
|
|
|
b syscall_exit
|
|
|
|
|
|
|
|
|
|
syscall_exit_work:
|
|
|
|
|
/* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
|
|
|
|
|
If TIF_NOERROR is set, just save r3 as it is. */
|
|
|
|
|
|
|
|
|
|
andi. r0,r9,_TIF_RESTOREALL
|
2006-03-07 21:24:22 -05:00
|
|
|
beq+ 0f
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
b 2f
|
|
|
|
|
0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
blt+ 1f
|
|
|
|
|
andi. r0,r9,_TIF_NOERROR
|
|
|
|
|
bne- 1f
|
|
|
|
|
ld r5,_CCR(r1)
|
|
|
|
|
neg r3,r3
|
|
|
|
|
oris r5,r5,0x1000 /* Set SO bit in CR */
|
|
|
|
|
std r5,_CCR(r1)
|
|
|
|
|
1: std r3,GPR3(r1)
|
|
|
|
|
2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
|
|
|
|
|
beq 4f
|
|
|
|
|
|
2006-03-07 21:24:22 -05:00
|
|
|
/* Clear per-syscall TIF flags if any are set. */
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
|
|
|
|
|
li r11,_TIF_PERSYSCALL_MASK
|
|
|
|
|
addi r12,r12,TI_FLAGS
|
|
|
|
|
3: ldarx r10,0,r12
|
|
|
|
|
andc r10,r10,r11
|
|
|
|
|
stdcx. r10,0,r12
|
|
|
|
|
bne- 3b
|
|
|
|
|
subi r12,r12,TI_FLAGS
|
2006-03-07 21:24:22 -05:00
|
|
|
|
|
|
|
|
4: /* Anything else left to do? */
|
|
|
|
|
andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
beq .ret_from_except_lite
|
|
|
|
|
|
|
|
|
|
/* Re-enable interrupts */
|
|
|
|
|
mfmsr r10
|
|
|
|
|
ori r10,r10,MSR_EE
|
|
|
|
|
mtmsrd r10,1
|
|
|
|
|
|
2006-03-07 21:24:22 -05:00
|
|
|
bl .save_nvgprs
|
2005-10-10 08:36:14 -04:00
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
bl .do_syscall_trace_leave
|
2006-03-07 21:24:22 -05:00
|
|
|
b .ret_from_except
|
2005-10-10 08:36:14 -04:00
|
|
|
|
|
|
|
|
/* Save non-volatile GPRs, if not already saved. */
|
|
|
|
|
_GLOBAL(save_nvgprs)
|
|
|
|
|
ld r11,_TRAP(r1)
|
|
|
|
|
andi. r0,r11,1
|
|
|
|
|
beqlr-
|
|
|
|
|
SAVE_NVGPRS(r1)
|
|
|
|
|
clrrdi r0,r11,1
|
|
|
|
|
std r0,_TRAP(r1)
|
|
|
|
|
blr
|
|
|
|
|
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 13:52:18 -05:00
|
|
|
|
2005-10-10 08:36:14 -04:00
|
|
|
/*
|
|
|
|
|
* The sigsuspend and rt_sigsuspend system calls can call do_signal
|
|
|
|
|
* and thus put the process into the stopped state where we might
|
|
|
|
|
* want to examine its user state with ptrace. Therefore we need
|
|
|
|
|
* to save all the nonvolatile registers (r14 - r31) before calling
|
|
|
|
|
* the C code. Similarly, fork, vfork and clone need the full
|
|
|
|
|
* register state on the stack so that it can be copied to the child.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
_GLOBAL(ppc_fork)
|
|
|
|
|
bl .save_nvgprs
|
|
|
|
|
bl .sys_fork
|
|
|
|
|
b syscall_exit
|
|
|
|
|
|
|
|
|
|
_GLOBAL(ppc_vfork)
|
|
|
|
|
bl .save_nvgprs
|
|
|
|
|
bl .sys_vfork
|
|
|
|
|
b syscall_exit
|
|
|
|
|
|
|
|
|
|
_GLOBAL(ppc_clone)
|
|
|
|
|
bl .save_nvgprs
|
|
|
|
|
bl .sys_clone
|
|
|
|
|
b syscall_exit
|
|
|
|
|
|
2006-03-07 21:24:22 -05:00
|
|
|
_GLOBAL(ppc32_swapcontext)
|
|
|
|
|
bl .save_nvgprs
|
|
|
|
|
bl .compat_sys_swapcontext
|
|
|
|
|
b syscall_exit
|
|
|
|
|
|
|
|
|
|
_GLOBAL(ppc64_swapcontext)
|
|
|
|
|
bl .save_nvgprs
|
|
|
|
|
bl .sys_swapcontext
|
|
|
|
|
b syscall_exit
|
|
|
|
|
|
2005-10-10 08:36:14 -04:00
|
|
|
_GLOBAL(ret_from_fork)
|
|
|
|
|
bl .schedule_tail
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
li r3,0
|
|
|
|
|
b syscall_exit
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This routine switches between two different tasks. The process
|
|
|
|
|
* state of one is saved on its kernel stack. Then the state
|
|
|
|
|
* of the other is restored from its kernel stack. The memory
|
|
|
|
|
* management hardware is updated to the second process's state.
|
|
|
|
|
* Finally, we can return to the second process, via ret_from_except.
|
|
|
|
|
* On entry, r3 points to the THREAD for the current task, r4
|
|
|
|
|
* points to the THREAD for the new task.
|
|
|
|
|
*
|
|
|
|
|
* Note: there are two ways to get to the "going out" portion
|
|
|
|
|
* of this code; either by coming in via the entry (_switch)
|
|
|
|
|
* or via "fork" which must set up an environment equivalent
|
|
|
|
|
* to the "_switch" path. If you change this you'll have to change
|
|
|
|
|
* the fork code also.
|
|
|
|
|
*
|
|
|
|
|
* The code which creates the new task context is in 'copy_thread'
|
2006-01-23 11:58:20 -05:00
|
|
|
* in arch/powerpc/kernel/process.c
|
2005-10-10 08:36:14 -04:00
|
|
|
*/
|
|
|
|
|
.align 7
|
|
|
|
|
_GLOBAL(_switch)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
|
|
|
|
stdu r1,-SWITCH_FRAME_SIZE(r1)
|
|
|
|
|
/* r3-r13 are caller saved -- Cort */
|
|
|
|
|
SAVE_8GPRS(14, r1)
|
|
|
|
|
SAVE_10GPRS(22, r1)
|
|
|
|
|
mflr r20 /* Return to switch caller */
|
|
|
|
|
mfmsr r22
|
|
|
|
|
li r0, MSR_FP
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
oris r0,r0,MSR_VEC@h /* Disable altivec */
|
|
|
|
|
mfspr r24,SPRN_VRSAVE /* save vrsave register value */
|
|
|
|
|
std r24,THREAD_VRSAVE(r3)
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
|
and. r0,r0,r22
|
|
|
|
|
beq+ 1f
|
|
|
|
|
andc r22,r22,r0
|
|
|
|
|
mtmsrd r22
|
|
|
|
|
isync
|
|
|
|
|
1: std r20,_NIP(r1)
|
|
|
|
|
mfcr r23
|
|
|
|
|
std r23,_CCR(r1)
|
|
|
|
|
std r1,KSP(r3) /* Set old stack pointer */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
/* We need a sync somewhere here to make sure that if the
|
|
|
|
|
* previous task gets rescheduled on another CPU, it sees all
|
|
|
|
|
* stores it has performed on this one.
|
|
|
|
|
*/
|
|
|
|
|
sync
|
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
|
|
addi r6,r4,-THREAD /* Convert THREAD to 'current' */
|
|
|
|
|
std r6,PACACURRENT(r13) /* Set new 'current' */
|
|
|
|
|
|
|
|
|
|
ld r8,KSP(r4) /* new stack pointer */
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
clrrdi r6,r8,28 /* get its ESID */
|
|
|
|
|
clrrdi r9,r1,28 /* get current sp ESID */
|
|
|
|
|
clrldi. r0,r6,2 /* is new ESID c00000000? */
|
|
|
|
|
cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
|
|
|
|
|
cror eq,4*cr1+eq,eq
|
|
|
|
|
beq 2f /* if yes, don't slbie it */
|
|
|
|
|
|
|
|
|
|
/* Bolt in the new stack SLB entry */
|
|
|
|
|
ld r7,KSP_VSID(r4) /* Get new stack's VSID */
|
|
|
|
|
oris r0,r6,(SLB_ESID_V)@h
|
|
|
|
|
ori r0,r0,(SLB_NUM_BOLTED-1)@l
|
2006-08-07 02:19:19 -04:00
|
|
|
|
|
|
|
|
/* Update the last bolted SLB */
|
|
|
|
|
ld r9,PACA_SLBSHADOWPTR(r13)
|
2006-08-09 03:00:30 -04:00
|
|
|
li r12,0
|
|
|
|
|
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
|
|
|
|
|
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
|
|
|
|
|
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
|
2006-08-07 02:19:19 -04:00
|
|
|
|
2005-10-10 08:36:14 -04:00
|
|
|
slbie r6
|
|
|
|
|
slbie r6 /* Workaround POWER5 < DD2.1 issue */
|
|
|
|
|
slbmte r7,r0
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
2:
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_SLB)
|
|
|
|
|
clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
|
|
|
|
|
/* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
|
|
|
|
|
because we don't need to leave the 288-byte ABI gap at the
|
|
|
|
|
top of the kernel stack. */
|
|
|
|
|
addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
|
|
|
|
|
|
|
|
|
|
mr r1,r8 /* start using new stack pointer */
|
|
|
|
|
std r7,PACAKSAVE(r13)
|
|
|
|
|
|
|
|
|
|
ld r6,_CCR(r1)
|
|
|
|
|
mtcrf 0xFF,r6
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
ld r0,THREAD_VRSAVE(r4)
|
|
|
|
|
mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
|
|
|
|
|
|
/* r3-r13 are destroyed -- Cort */
|
|
|
|
|
REST_8GPRS(14, r1)
|
|
|
|
|
REST_10GPRS(22, r1)
|
|
|
|
|
|
|
|
|
|
/* convert old thread to its task_struct for return value */
|
|
|
|
|
addi r3,r3,-THREAD
|
|
|
|
|
ld r7,_NIP(r1) /* Return to _switch caller in new task */
|
|
|
|
|
mtlr r7
|
|
|
|
|
addi r1,r1,SWITCH_FRAME_SIZE
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.align 7
|
|
|
|
|
_GLOBAL(ret_from_except)
|
|
|
|
|
ld r11,_TRAP(r1)
|
|
|
|
|
andi. r0,r11,1
|
|
|
|
|
bne .ret_from_except_lite
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
|
|
|
|
|
_GLOBAL(ret_from_except_lite)
|
|
|
|
|
/*
|
|
|
|
|
* Disable interrupts so that current_thread_info()->flags
|
|
|
|
|
* can't change between when we test it and when we return
|
|
|
|
|
* from the interrupt.
|
|
|
|
|
*/
|
|
|
|
|
mfmsr r10 /* Get current interrupt state */
|
|
|
|
|
rldicl r9,r10,48,1 /* clear MSR_EE */
|
|
|
|
|
rotldi r9,r9,16
|
|
|
|
|
mtmsrd r9,1 /* Update machine state */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PREEMPT
|
|
|
|
|
clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
|
|
|
|
|
li r0,_TIF_NEED_RESCHED /* bits to check */
|
|
|
|
|
ld r3,_MSR(r1)
|
|
|
|
|
ld r4,TI_FLAGS(r9)
|
|
|
|
|
/* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
|
|
|
|
|
rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
|
|
|
|
|
and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
|
|
|
|
|
bne do_work
|
|
|
|
|
|
|
|
|
|
#else /* !CONFIG_PREEMPT */
|
|
|
|
|
ld r3,_MSR(r1) /* Returning to user mode? */
|
|
|
|
|
andi. r3,r3,MSR_PR
|
|
|
|
|
beq restore /* if not, just restore regs and return */
|
|
|
|
|
|
|
|
|
|
/* Check current_thread_info()->flags */
|
|
|
|
|
clrrdi r9,r1,THREAD_SHIFT
|
|
|
|
|
ld r4,TI_FLAGS(r9)
|
|
|
|
|
andi. r0,r4,_TIF_USER_WORK_MASK
|
|
|
|
|
bne do_work
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
restore:
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
|
|
|
ld r5,SOFTE(r1)
|
2005-10-10 08:36:14 -04:00
|
|
|
#ifdef CONFIG_PPC_ISERIES
|
2006-09-25 04:19:00 -04:00
|
|
|
BEGIN_FW_FTR_SECTION
|
2005-10-10 08:36:14 -04:00
|
|
|
cmpdi 0,r5,0
|
|
|
|
|
beq 4f
|
|
|
|
|
/* Check for pending interrupts (iSeries) */
|
2006-01-12 18:26:42 -05:00
|
|
|
ld r3,PACALPPACAPTR(r13)
|
|
|
|
|
ld r3,LPPACAANYINT(r3)
|
2005-10-10 08:36:14 -04:00
|
|
|
cmpdi r3,0
|
|
|
|
|
beq+ 4f /* skip do_IRQ if no interrupts */
|
|
|
|
|
|
|
|
|
|
li r3,0
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
|
|
|
stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */
|
2005-10-10 08:36:14 -04:00
|
|
|
ori r10,r10,MSR_EE
|
|
|
|
|
mtmsrd r10 /* hard-enable again */
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
bl .do_IRQ
|
|
|
|
|
b .ret_from_except_lite /* loop back and handle more */
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
|
|
|
4:
|
2006-09-25 04:19:00 -04:00
|
|
|
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
|
2005-10-10 08:36:14 -04:00
|
|
|
#endif
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
|
|
|
stb r5,PACASOFTIRQEN(r13)
|
2005-10-10 08:36:14 -04:00
|
|
|
|
|
|
|
|
ld r3,_MSR(r1)
|
|
|
|
|
andi. r0,r3,MSR_RI
|
|
|
|
|
beq- unrecov_restore
|
|
|
|
|
|
2006-10-17 20:11:22 -04:00
|
|
|
/* extract EE bit and use it to restore paca->hard_enabled */
|
|
|
|
|
rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
|
|
|
|
|
stb r4,PACAHARDIRQEN(r13)
|
|
|
|
|
|
2005-10-10 08:36:14 -04:00
|
|
|
andi. r0,r3,MSR_PR
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* r13 is our per cpu area, only restore it if we are returning to
|
|
|
|
|
* userspace
|
|
|
|
|
*/
|
|
|
|
|
beq 1f
|
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 18:06:59 -05:00
|
|
|
ACCOUNT_CPU_USER_EXIT(r3, r4)
|
2005-10-10 08:36:14 -04:00
|
|
|
REST_GPR(13, r1)
|
|
|
|
|
1:
|
|
|
|
|
ld r3,_CTR(r1)
|
|
|
|
|
ld r0,_LINK(r1)
|
|
|
|
|
mtctr r3
|
|
|
|
|
mtlr r0
|
|
|
|
|
ld r3,_XER(r1)
|
|
|
|
|
mtspr SPRN_XER,r3
|
|
|
|
|
|
|
|
|
|
REST_8GPRS(5, r1)
|
|
|
|
|
|
|
|
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
|
|
|
|
|
|
|
|
|
mfmsr r0
|
|
|
|
|
li r2, MSR_RI
|
|
|
|
|
andc r0,r0,r2
|
|
|
|
|
mtmsrd r0,1
|
|
|
|
|
|
|
|
|
|
ld r0,_MSR(r1)
|
|
|
|
|
mtspr SPRN_SRR1,r0
|
|
|
|
|
|
|
|
|
|
ld r2,_CCR(r1)
|
|
|
|
|
mtcrf 0xFF,r2
|
|
|
|
|
ld r2,_NIP(r1)
|
|
|
|
|
mtspr SPRN_SRR0,r2
|
|
|
|
|
|
|
|
|
|
ld r0,GPR0(r1)
|
|
|
|
|
ld r2,GPR2(r1)
|
|
|
|
|
ld r3,GPR3(r1)
|
|
|
|
|
ld r4,GPR4(r1)
|
|
|
|
|
ld r1,GPR1(r1)
|
|
|
|
|
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
|
|
|
|
/* Note: this must change if we start using the TIF_NOTIFY_RESUME bit */
|
|
|
|
|
do_work:
|
|
|
|
|
#ifdef CONFIG_PREEMPT
|
|
|
|
|
andi. r0,r3,MSR_PR /* Returning to user mode? */
|
|
|
|
|
bne user_work
|
|
|
|
|
/* Check that preempt_count() == 0 and interrupts are enabled */
|
|
|
|
|
lwz r8,TI_PREEMPT(r9)
|
|
|
|
|
cmpwi cr1,r8,0
|
|
|
|
|
ld r0,SOFTE(r1)
|
|
|
|
|
cmpdi r0,0
|
|
|
|
|
crandc eq,cr1*4+eq,eq
|
|
|
|
|
bne restore
|
|
|
|
|
/* here we are preempting the current task */
|
|
|
|
|
1:
|
|
|
|
|
li r0,1
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
|
|
|
stb r0,PACASOFTIRQEN(r13)
|
|
|
|
|
stb r0,PACAHARDIRQEN(r13)
|
2005-10-10 08:36:14 -04:00
|
|
|
ori r10,r10,MSR_EE
|
|
|
|
|
mtmsrd r10,1 /* reenable interrupts */
|
|
|
|
|
bl .preempt_schedule
|
|
|
|
|
mfmsr r10
|
|
|
|
|
clrrdi r9,r1,THREAD_SHIFT
|
|
|
|
|
rldicl r10,r10,48,1 /* disable interrupts again */
|
|
|
|
|
rotldi r10,r10,16
|
|
|
|
|
mtmsrd r10,1
|
|
|
|
|
ld r4,TI_FLAGS(r9)
|
|
|
|
|
andi. r0,r4,_TIF_NEED_RESCHED
|
|
|
|
|
bne 1b
|
|
|
|
|
b restore
|
|
|
|
|
|
|
|
|
|
user_work:
|
|
|
|
|
#endif
|
|
|
|
|
/* Enable interrupts */
|
|
|
|
|
ori r10,r10,MSR_EE
|
|
|
|
|
mtmsrd r10,1
|
|
|
|
|
|
|
|
|
|
andi. r0,r4,_TIF_NEED_RESCHED
|
|
|
|
|
beq 1f
|
|
|
|
|
bl .schedule
|
|
|
|
|
b .ret_from_except_lite
|
|
|
|
|
|
|
|
|
|
1: bl .save_nvgprs
|
|
|
|
|
li r3,0
|
|
|
|
|
addi r4,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
bl .do_signal
|
|
|
|
|
b .ret_from_except
|
|
|
|
|
|
|
|
|
|
unrecov_restore:
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
bl .unrecoverable_exception
|
|
|
|
|
b unrecov_restore
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_RTAS
|
|
|
|
|
/*
|
|
|
|
|
* On CHRP, the Run-Time Abstraction Services (RTAS) have to be
|
|
|
|
|
* called with the MMU off.
|
|
|
|
|
*
|
|
|
|
|
* In addition, we need to be in 32b mode, at least for now.
|
|
|
|
|
*
|
|
|
|
|
* Note: r3 is an input parameter to rtas, so don't trash it...
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(enter_rtas)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
|
|
|
|
stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
|
|
|
|
|
|
|
|
|
|
/* Because RTAS is running in 32b mode, it clobbers the high order half
|
|
|
|
|
* of all registers that it saves. We therefore save those registers
|
|
|
|
|
* RTAS might touch to the stack. (r0, r3-r13 are caller saved)
|
|
|
|
|
*/
|
|
|
|
|
SAVE_GPR(2, r1) /* Save the TOC */
|
|
|
|
|
SAVE_GPR(13, r1) /* Save paca */
|
|
|
|
|
SAVE_8GPRS(14, r1) /* Save the non-volatiles */
|
|
|
|
|
SAVE_10GPRS(22, r1) /* ditto */
|
|
|
|
|
|
|
|
|
|
mfcr r4
|
|
|
|
|
std r4,_CCR(r1)
|
|
|
|
|
mfctr r5
|
|
|
|
|
std r5,_CTR(r1)
|
|
|
|
|
mfspr r6,SPRN_XER
|
|
|
|
|
std r6,_XER(r1)
|
|
|
|
|
mfdar r7
|
|
|
|
|
std r7,_DAR(r1)
|
|
|
|
|
mfdsisr r8
|
|
|
|
|
std r8,_DSISR(r1)
|
|
|
|
|
mfsrr0 r9
|
|
|
|
|
std r9,_SRR0(r1)
|
|
|
|
|
mfsrr1 r10
|
|
|
|
|
std r10,_SRR1(r1)
|
|
|
|
|
|
2006-03-27 18:20:00 -05:00
|
|
|
/* Temporary workaround to clear CR until RTAS can be modified to
|
|
|
|
|
* ignore all bits.
|
|
|
|
|
*/
|
|
|
|
|
li r0,0
|
|
|
|
|
mtcr r0
|
|
|
|
|
|
2005-10-10 08:36:14 -04:00
|
|
|
/* There is no way it is acceptable to get here with interrupts enabled,
|
|
|
|
|
* check it with the asm equivalent of WARN_ON
|
|
|
|
|
*/
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
|
|
|
lbz r0,PACASOFTIRQEN(r13)
|
2005-10-10 08:36:14 -04:00
|
|
|
1: tdnei r0,0
|
|
|
|
|
.section __bug_table,"a"
|
|
|
|
|
.llong 1b,__LINE__ + 0x1000000, 1f, 2f
|
|
|
|
|
.previous
|
|
|
|
|
.section .rodata,"a"
|
|
|
|
|
1: .asciz __FILE__
|
|
|
|
|
2: .asciz "enter_rtas"
|
|
|
|
|
.previous
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 02:47:49 -04:00
|
|
|
|
|
|
|
|
/* Hard-disable interrupts */
|
|
|
|
|
mfmsr r6
|
|
|
|
|
rldicl r7,r6,48,1
|
|
|
|
|
rotldi r7,r7,16
|
|
|
|
|
mtmsrd r7,1
|
|
|
|
|
|
2005-10-10 08:36:14 -04:00
|
|
|
/* Unfortunately, the stack pointer and the MSR are also clobbered,
|
|
|
|
|
* so they are saved in the PACA which allows us to restore
|
|
|
|
|
* our original state after RTAS returns.
|
|
|
|
|
*/
|
|
|
|
|
std r1,PACAR1(r13)
|
|
|
|
|
std r6,PACASAVEDMSR(r13)
|
|
|
|
|
|
|
|
|
|
/* Setup our real return addr */
|
2006-01-12 22:56:25 -05:00
|
|
|
LOAD_REG_ADDR(r4,.rtas_return_loc)
|
|
|
|
|
clrldi r4,r4,2 /* convert to realmode address */
|
2005-10-10 08:36:14 -04:00
|
|
|
mtlr r4
|
|
|
|
|
|
|
|
|
|
li r0,0
|
|
|
|
|
ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
|
|
|
|
|
andc r0,r6,r0
|
|
|
|
|
|
|
|
|
|
li r9,1
|
|
|
|
|
rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
|
|
|
|
|
ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP
|
|
|
|
|
andc r6,r0,r9
|
|
|
|
|
ori r6,r6,MSR_RI
|
|
|
|
|
sync /* disable interrupts so SRR0/1 */
|
|
|
|
|
mtmsrd r0 /* don't get trashed */
|
|
|
|
|
|
2006-01-12 22:56:25 -05:00
|
|
|
LOAD_REG_ADDR(r4, rtas)
|
2005-10-10 08:36:14 -04:00
|
|
|
ld r5,RTASENTRY(r4) /* get the rtas->entry value */
|
|
|
|
|
ld r4,RTASBASE(r4) /* get the rtas->base value */
|
|
|
|
|
|
|
|
|
|
mtspr SPRN_SRR0,r5
|
|
|
|
|
mtspr SPRN_SRR1,r6
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
|
|
|
|
_STATIC(rtas_return_loc)
|
|
|
|
|
/* relocation is off at this point */
|
|
|
|
|
mfspr r4,SPRN_SPRG3 /* Get PACA */
|
2006-01-12 22:56:25 -05:00
|
|
|
clrldi r4,r4,2 /* convert to realmode address */
|
2005-10-10 08:36:14 -04:00
|
|
|
|
|
|
|
|
mfmsr r6
|
|
|
|
|
li r0,MSR_RI
|
|
|
|
|
andc r6,r6,r0
|
|
|
|
|
sync
|
|
|
|
|
mtmsrd r6
|
|
|
|
|
|
|
|
|
|
ld r1,PACAR1(r4) /* Restore our SP */
|
2006-01-12 22:56:25 -05:00
|
|
|
LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs)
|
2005-10-10 08:36:14 -04:00
|
|
|
ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
|
|
|
|
|
|
|
|
|
|
mtspr SPRN_SRR0,r3
|
|
|
|
|
mtspr SPRN_SRR1,r4
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
|
|
|
|
_STATIC(rtas_restore_regs)
|
|
|
|
|
/* relocation is on at this point */
|
|
|
|
|
REST_GPR(2, r1) /* Restore the TOC */
|
|
|
|
|
REST_GPR(13, r1) /* Restore paca */
|
|
|
|
|
REST_8GPRS(14, r1) /* Restore the non-volatiles */
|
|
|
|
|
REST_10GPRS(22, r1) /* ditto */
|
|
|
|
|
|
|
|
|
|
mfspr r13,SPRN_SPRG3
|
|
|
|
|
|
|
|
|
|
ld r4,_CCR(r1)
|
|
|
|
|
mtcr r4
|
|
|
|
|
ld r5,_CTR(r1)
|
|
|
|
|
mtctr r5
|
|
|
|
|
ld r6,_XER(r1)
|
|
|
|
|
mtspr SPRN_XER,r6
|
|
|
|
|
ld r7,_DAR(r1)
|
|
|
|
|
mtdar r7
|
|
|
|
|
ld r8,_DSISR(r1)
|
|
|
|
|
mtdsisr r8
|
|
|
|
|
ld r9,_SRR0(r1)
|
|
|
|
|
mtsrr0 r9
|
|
|
|
|
ld r10,_SRR1(r1)
|
|
|
|
|
mtsrr1 r10
|
|
|
|
|
|
|
|
|
|
addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
|
|
|
|
|
ld r0,16(r1) /* get return address */
|
|
|
|
|
|
|
|
|
|
mtlr r0
|
|
|
|
|
blr /* return to caller */
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_PPC_RTAS */
|
|
|
|
|
|
|
|
|
|
_GLOBAL(enter_prom)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
|
|
|
|
stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
|
|
|
|
|
|
|
|
|
|
/* Because PROM is running in 32b mode, it clobbers the high order half
|
|
|
|
|
* of all registers that it saves. We therefore save those registers
|
|
|
|
|
* PROM might touch to the stack. (r0, r3-r13 are caller saved)
|
|
|
|
|
*/
|
|
|
|
|
SAVE_8GPRS(2, r1)
|
|
|
|
|
SAVE_GPR(13, r1)
|
|
|
|
|
SAVE_8GPRS(14, r1)
|
|
|
|
|
SAVE_10GPRS(22, r1)
|
|
|
|
|
mfcr r4
|
|
|
|
|
std r4,_CCR(r1)
|
|
|
|
|
mfctr r5
|
|
|
|
|
std r5,_CTR(r1)
|
|
|
|
|
mfspr r6,SPRN_XER
|
|
|
|
|
std r6,_XER(r1)
|
|
|
|
|
mfdar r7
|
|
|
|
|
std r7,_DAR(r1)
|
|
|
|
|
mfdsisr r8
|
|
|
|
|
std r8,_DSISR(r1)
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mfsrr0 r9
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std r9,_SRR0(r1)
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mfsrr1 r10
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std r10,_SRR1(r1)
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mfmsr r11
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std r11,_MSR(r1)
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/* Get the PROM entrypoint */
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ld r0,GPR4(r1)
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mtlr r0
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/* Switch MSR to 32 bits mode
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*/
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mfmsr r11
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li r12,1
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rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
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andc r11,r11,r12
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li r12,1
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rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
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andc r11,r11,r12
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mtmsrd r11
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isync
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/* Restore arguments & enter PROM here... */
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ld r3,GPR3(r1)
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blrl
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/* Just make sure that r1 top 32 bits didn't get
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* corrupt by OF
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*/
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rldicl r1,r1,0,32
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/* Restore the MSR (back to 64 bits) */
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ld r0,_MSR(r1)
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mtmsrd r0
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isync
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/* Restore other registers */
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REST_GPR(2, r1)
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REST_GPR(13, r1)
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REST_8GPRS(14, r1)
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REST_10GPRS(22, r1)
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ld r4,_CCR(r1)
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mtcr r4
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ld r5,_CTR(r1)
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mtctr r5
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ld r6,_XER(r1)
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mtspr SPRN_XER,r6
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ld r7,_DAR(r1)
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mtdar r7
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ld r8,_DSISR(r1)
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mtdsisr r8
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ld r9,_SRR0(r1)
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mtsrr0 r9
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ld r10,_SRR1(r1)
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mtsrr1 r10
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addi r1,r1,PROM_FRAME_SIZE
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ld r0,16(r1)
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mtlr r0
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