[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
/*
|
2008-03-27 14:51:41 -04:00
|
|
|
* arch/arm/mach-orion5x/common.c
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
*
|
2008-03-27 14:51:41 -04:00
|
|
|
* Core functions for Marvell Orion 5x SoCs
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
*
|
|
|
|
* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
|
|
|
|
*
|
2008-03-27 14:51:41 -04:00
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
2007-10-23 15:14:42 -04:00
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/serial_8250.h>
|
2008-03-27 14:51:39 -04:00
|
|
|
#include <linux/mbus.h>
|
2007-10-31 06:42:41 -04:00
|
|
|
#include <linux/mv643xx_eth.h>
|
2007-11-12 02:51:36 -05:00
|
|
|
#include <linux/mv643xx_i2c.h>
|
2008-03-27 14:51:39 -04:00
|
|
|
#include <linux/ata_platform.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
#include <asm/page.h>
|
2008-02-29 15:12:57 -05:00
|
|
|
#include <asm/setup.h>
|
2007-10-23 15:14:42 -04:00
|
|
|
#include <asm/timex.h>
|
2008-02-29 15:12:57 -05:00
|
|
|
#include <asm/mach/arch.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
#include <asm/mach/map.h>
|
2008-03-27 14:51:40 -04:00
|
|
|
#include <asm/mach/time.h>
|
2008-01-29 17:33:32 -05:00
|
|
|
#include <asm/arch/hardware.h>
|
2008-03-27 14:51:41 -04:00
|
|
|
#include <asm/arch/orion5x.h>
|
2008-03-27 14:51:40 -04:00
|
|
|
#include <asm/plat-orion/ehci-orion.h>
|
2008-03-27 14:51:40 -04:00
|
|
|
#include <asm/plat-orion/orion_nand.h>
|
2008-03-27 14:51:40 -04:00
|
|
|
#include <asm/plat-orion/time.h>
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
#include "common.h"
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* I/O Address Mapping
|
|
|
|
****************************************************************************/
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct map_desc orion5x_io_desc[] __initdata = {
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
{
|
2008-03-27 14:51:41 -04:00
|
|
|
.virtual = ORION5X_REGS_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
|
|
|
|
.length = ORION5X_REGS_SIZE,
|
2008-05-10 10:30:01 -04:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 14:51:41 -04:00
|
|
|
.virtual = ORION5X_PCIE_IO_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCIE_IO_SIZE,
|
2008-05-10 10:30:01 -04:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 14:51:41 -04:00
|
|
|
.virtual = ORION5X_PCI_IO_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCI_IO_SIZE,
|
2008-05-10 10:30:01 -04:00
|
|
|
.type = MT_DEVICE,
|
|
|
|
}, {
|
2008-03-27 14:51:41 -04:00
|
|
|
.virtual = ORION5X_PCIE_WA_VIRT_BASE,
|
|
|
|
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
|
|
|
|
.length = ORION5X_PCIE_WA_SIZE,
|
2008-05-10 10:30:01 -04:00
|
|
|
.type = MT_DEVICE,
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
void __init orion5x_map_io(void)
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
{
|
2008-03-27 14:51:41 -04:00
|
|
|
iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
}
|
2007-10-23 15:14:42 -04:00
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
|
2007-10-23 15:14:42 -04:00
|
|
|
/*****************************************************************************
|
2008-04-21 23:37:12 -04:00
|
|
|
* EHCI
|
2007-10-23 15:14:42 -04:00
|
|
|
****************************************************************************/
|
2008-04-21 23:37:12 -04:00
|
|
|
static struct orion_ehci_data orion5x_ehci_data = {
|
|
|
|
.dram = &orion5x_mbus_dram_info,
|
2007-10-23 15:14:42 -04:00
|
|
|
};
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
static u64 ehci_dmamask = 0xffffffffUL;
|
2007-10-23 15:14:42 -04:00
|
|
|
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI0
|
|
|
|
****************************************************************************/
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct resource orion5x_ehci0_resources[] = {
|
2007-10-23 15:14:42 -04:00
|
|
|
{
|
2008-03-27 14:51:41 -04:00
|
|
|
.start = ORION5X_USB0_PHYS_BASE,
|
2008-04-25 16:30:21 -04:00
|
|
|
.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
|
2007-10-23 15:14:42 -04:00
|
|
|
.flags = IORESOURCE_MEM,
|
2008-05-10 10:30:01 -04:00
|
|
|
}, {
|
2008-03-27 14:51:41 -04:00
|
|
|
.start = IRQ_ORION5X_USB0_CTRL,
|
|
|
|
.end = IRQ_ORION5X_USB0_CTRL,
|
2007-10-23 15:14:42 -04:00
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct platform_device orion5x_ehci0 = {
|
2007-10-23 15:14:42 -04:00
|
|
|
.name = "orion-ehci",
|
|
|
|
.id = 0,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &ehci_dmamask,
|
|
|
|
.coherent_dma_mask = 0xffffffff,
|
2008-03-27 14:51:41 -04:00
|
|
|
.platform_data = &orion5x_ehci_data,
|
2007-10-23 15:14:42 -04:00
|
|
|
},
|
2008-03-27 14:51:41 -04:00
|
|
|
.resource = orion5x_ehci0_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
|
2007-10-23 15:14:42 -04:00
|
|
|
};
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
void __init orion5x_ehci0_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_ehci0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* EHCI1
|
|
|
|
****************************************************************************/
|
|
|
|
static struct resource orion5x_ehci1_resources[] = {
|
|
|
|
{
|
|
|
|
.start = ORION5X_USB1_PHYS_BASE,
|
|
|
|
.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_USB1_CTRL,
|
|
|
|
.end = IRQ_ORION5X_USB1_CTRL,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct platform_device orion5x_ehci1 = {
|
2007-10-23 15:14:42 -04:00
|
|
|
.name = "orion-ehci",
|
|
|
|
.id = 1,
|
|
|
|
.dev = {
|
|
|
|
.dma_mask = &ehci_dmamask,
|
|
|
|
.coherent_dma_mask = 0xffffffff,
|
2008-03-27 14:51:41 -04:00
|
|
|
.platform_data = &orion5x_ehci_data,
|
2007-10-23 15:14:42 -04:00
|
|
|
},
|
2008-03-27 14:51:41 -04:00
|
|
|
.resource = orion5x_ehci1_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
|
2007-10-23 15:14:42 -04:00
|
|
|
};
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
void __init orion5x_ehci1_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_ehci1);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-10-31 06:42:41 -04:00
|
|
|
/*****************************************************************************
|
2008-04-21 23:37:12 -04:00
|
|
|
* GigE
|
2007-10-31 06:42:41 -04:00
|
|
|
****************************************************************************/
|
2008-04-26 14:48:11 -04:00
|
|
|
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
|
|
|
|
.dram = &orion5x_mbus_dram_info,
|
2008-04-26 14:48:11 -04:00
|
|
|
.t_clk = ORION5X_TCLK,
|
2008-04-26 14:48:11 -04:00
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct resource orion5x_eth_shared_resources[] = {
|
2007-10-31 06:42:41 -04:00
|
|
|
{
|
2008-03-27 14:51:41 -04:00
|
|
|
.start = ORION5X_ETH_PHYS_BASE + 0x2000,
|
|
|
|
.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
|
2007-10-31 06:42:41 -04:00
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct platform_device orion5x_eth_shared = {
|
2007-10-31 06:42:41 -04:00
|
|
|
.name = MV643XX_ETH_SHARED_NAME,
|
|
|
|
.id = 0,
|
2008-04-26 14:48:11 -04:00
|
|
|
.dev = {
|
|
|
|
.platform_data = &orion5x_eth_shared_data,
|
|
|
|
},
|
2007-10-31 06:42:41 -04:00
|
|
|
.num_resources = 1,
|
2008-03-27 14:51:41 -04:00
|
|
|
.resource = orion5x_eth_shared_resources,
|
2007-10-31 06:42:41 -04:00
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct resource orion5x_eth_resources[] = {
|
2007-10-31 06:42:41 -04:00
|
|
|
{
|
|
|
|
.name = "eth irq",
|
2008-03-27 14:51:41 -04:00
|
|
|
.start = IRQ_ORION5X_ETH_SUM,
|
|
|
|
.end = IRQ_ORION5X_ETH_SUM,
|
2007-10-31 06:42:41 -04:00
|
|
|
.flags = IORESOURCE_IRQ,
|
2008-05-10 10:30:01 -04:00
|
|
|
},
|
2007-10-31 06:42:41 -04:00
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct platform_device orion5x_eth = {
|
2007-10-31 06:42:41 -04:00
|
|
|
.name = MV643XX_ETH_NAME,
|
|
|
|
.id = 0,
|
|
|
|
.num_resources = 1,
|
2008-03-27 14:51:41 -04:00
|
|
|
.resource = orion5x_eth_resources,
|
2007-10-31 06:42:41 -04:00
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
|
2007-10-31 06:42:41 -04:00
|
|
|
{
|
2008-04-23 19:27:02 -04:00
|
|
|
eth_data->shared = &orion5x_eth_shared;
|
2008-03-27 14:51:41 -04:00
|
|
|
orion5x_eth.dev.platform_data = eth_data;
|
2008-04-23 19:27:02 -04:00
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
platform_device_register(&orion5x_eth_shared);
|
|
|
|
platform_device_register(&orion5x_eth);
|
2007-10-31 06:42:41 -04:00
|
|
|
}
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
|
2007-11-12 02:51:36 -05:00
|
|
|
/*****************************************************************************
|
2008-04-21 23:37:12 -04:00
|
|
|
* I2C
|
2007-11-12 02:51:36 -05:00
|
|
|
****************************************************************************/
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
|
2007-11-12 02:51:36 -05:00
|
|
|
.freq_m = 8, /* assumes 166 MHz TCLK */
|
|
|
|
.freq_n = 3,
|
|
|
|
.timeout = 1000, /* Default timeout of 1 second */
|
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct resource orion5x_i2c_resources[] = {
|
2007-11-12 02:51:36 -05:00
|
|
|
{
|
2008-05-10 10:30:01 -04:00
|
|
|
.name = "i2c base",
|
|
|
|
.start = I2C_PHYS_BASE,
|
2008-04-21 23:37:12 -04:00
|
|
|
.end = I2C_PHYS_BASE + 0x1f,
|
2008-05-10 10:30:01 -04:00
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "i2c irq",
|
|
|
|
.start = IRQ_ORION5X_I2C,
|
|
|
|
.end = IRQ_ORION5X_I2C,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
2007-11-12 02:51:36 -05:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct platform_device orion5x_i2c = {
|
2007-11-12 02:51:36 -05:00
|
|
|
.name = MV64XXX_I2C_CTLR_NAME,
|
|
|
|
.id = 0,
|
2008-03-27 14:51:41 -04:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
|
|
|
|
.resource = orion5x_i2c_resources,
|
2007-11-12 02:51:36 -05:00
|
|
|
.dev = {
|
2008-05-10 10:30:01 -04:00
|
|
|
.platform_data = &orion5x_i2c_pdata,
|
2007-11-12 02:51:36 -05:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
void __init orion5x_i2c_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_i2c);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-01-29 17:33:32 -05:00
|
|
|
/*****************************************************************************
|
2008-04-21 23:37:12 -04:00
|
|
|
* SATA
|
2008-01-29 17:33:32 -05:00
|
|
|
****************************************************************************/
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct resource orion5x_sata_resources[] = {
|
2008-01-29 17:33:32 -05:00
|
|
|
{
|
2008-05-10 10:30:01 -04:00
|
|
|
.name = "sata base",
|
|
|
|
.start = ORION5X_SATA_PHYS_BASE,
|
|
|
|
.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.name = "sata irq",
|
|
|
|
.start = IRQ_ORION5X_SATA,
|
|
|
|
.end = IRQ_ORION5X_SATA,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
2008-01-29 17:33:32 -05:00
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
static struct platform_device orion5x_sata = {
|
2008-05-10 10:30:01 -04:00
|
|
|
.name = "sata_mv",
|
|
|
|
.id = 0,
|
2008-01-29 17:33:32 -05:00
|
|
|
.dev = {
|
|
|
|
.coherent_dma_mask = 0xffffffff,
|
|
|
|
},
|
2008-05-10 10:30:01 -04:00
|
|
|
.num_resources = ARRAY_SIZE(orion5x_sata_resources),
|
|
|
|
.resource = orion5x_sata_resources,
|
2008-01-29 17:33:32 -05:00
|
|
|
};
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
|
2008-01-29 17:33:32 -05:00
|
|
|
{
|
2008-03-27 14:51:41 -04:00
|
|
|
sata_data->dram = &orion5x_mbus_dram_info;
|
|
|
|
orion5x_sata.dev.platform_data = sata_data;
|
|
|
|
platform_device_register(&orion5x_sata);
|
2008-01-29 17:33:32 -05:00
|
|
|
}
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
|
2008-03-27 14:51:40 -04:00
|
|
|
/*****************************************************************************
|
2008-04-21 23:37:12 -04:00
|
|
|
* UART0
|
|
|
|
****************************************************************************/
|
|
|
|
static struct plat_serial8250_port orion5x_uart0_data[] = {
|
|
|
|
{
|
|
|
|
.mapbase = UART0_PHYS_BASE,
|
|
|
|
.membase = (char *)UART0_VIRT_BASE,
|
|
|
|
.irq = IRQ_ORION5X_UART0,
|
|
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
|
|
.iotype = UPIO_MEM,
|
|
|
|
.regshift = 2,
|
|
|
|
.uartclk = ORION5X_TCLK,
|
|
|
|
}, {
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource orion5x_uart0_resources[] = {
|
|
|
|
{
|
|
|
|
.start = UART0_PHYS_BASE,
|
|
|
|
.end = UART0_PHYS_BASE + 0xff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_UART0,
|
|
|
|
.end = IRQ_ORION5X_UART0,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_uart0 = {
|
|
|
|
.name = "serial8250",
|
|
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
|
|
.dev = {
|
|
|
|
.platform_data = orion5x_uart0_data,
|
|
|
|
},
|
|
|
|
.resource = orion5x_uart0_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_uart0_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_uart0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* UART1
|
2008-03-27 14:51:40 -04:00
|
|
|
****************************************************************************/
|
2008-04-21 23:37:12 -04:00
|
|
|
static struct plat_serial8250_port orion5x_uart1_data[] = {
|
|
|
|
{
|
|
|
|
.mapbase = UART1_PHYS_BASE,
|
|
|
|
.membase = (char *)UART1_VIRT_BASE,
|
|
|
|
.irq = IRQ_ORION5X_UART1,
|
|
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
|
|
.iotype = UPIO_MEM,
|
|
|
|
.regshift = 2,
|
|
|
|
.uartclk = ORION5X_TCLK,
|
|
|
|
}, {
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct resource orion5x_uart1_resources[] = {
|
|
|
|
{
|
|
|
|
.start = UART1_PHYS_BASE,
|
|
|
|
.end = UART1_PHYS_BASE + 0xff,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
}, {
|
|
|
|
.start = IRQ_ORION5X_UART1,
|
|
|
|
.end = IRQ_ORION5X_UART1,
|
|
|
|
.flags = IORESOURCE_IRQ,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device orion5x_uart1 = {
|
|
|
|
.name = "serial8250",
|
|
|
|
.id = PLAT8250_DEV_PLATFORM1,
|
|
|
|
.dev = {
|
|
|
|
.platform_data = orion5x_uart1_data,
|
|
|
|
},
|
|
|
|
.resource = orion5x_uart1_resources,
|
|
|
|
.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init orion5x_uart1_init(void)
|
|
|
|
{
|
|
|
|
platform_device_register(&orion5x_uart1);
|
|
|
|
}
|
2008-03-27 14:51:40 -04:00
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* Time handling
|
|
|
|
****************************************************************************/
|
2008-03-27 14:51:41 -04:00
|
|
|
static void orion5x_timer_init(void)
|
2008-03-27 14:51:40 -04:00
|
|
|
{
|
2008-03-27 14:51:41 -04:00
|
|
|
orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
|
2008-03-27 14:51:40 -04:00
|
|
|
}
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
struct sys_timer orion5x_timer = {
|
2008-05-10 10:30:01 -04:00
|
|
|
.init = orion5x_timer_init,
|
2008-03-27 14:51:40 -04:00
|
|
|
};
|
|
|
|
|
2008-04-21 23:37:12 -04:00
|
|
|
|
2007-10-23 15:14:42 -04:00
|
|
|
/*****************************************************************************
|
|
|
|
* General
|
|
|
|
****************************************************************************/
|
|
|
|
/*
|
2008-04-25 16:31:32 -04:00
|
|
|
* Identify device ID and rev from PCIe configuration header space '0'.
|
2007-10-23 15:14:42 -04:00
|
|
|
*/
|
2008-03-27 14:51:41 -04:00
|
|
|
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
|
2007-10-23 15:14:42 -04:00
|
|
|
{
|
2008-03-27 14:51:41 -04:00
|
|
|
orion5x_pcie_id(dev, rev);
|
2007-10-23 15:14:42 -04:00
|
|
|
|
|
|
|
if (*dev == MV88F5281_DEV_ID) {
|
|
|
|
if (*rev == MV88F5281_REV_D2) {
|
|
|
|
*dev_name = "MV88F5281-D2";
|
|
|
|
} else if (*rev == MV88F5281_REV_D1) {
|
|
|
|
*dev_name = "MV88F5281-D1";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5281-Rev-Unsupported";
|
|
|
|
}
|
|
|
|
} else if (*dev == MV88F5182_DEV_ID) {
|
|
|
|
if (*rev == MV88F5182_REV_A2) {
|
|
|
|
*dev_name = "MV88F5182-A2";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5182-Rev-Unsupported";
|
|
|
|
}
|
2007-11-11 06:05:11 -05:00
|
|
|
} else if (*dev == MV88F5181_DEV_ID) {
|
|
|
|
if (*rev == MV88F5181_REV_B1) {
|
|
|
|
*dev_name = "MV88F5181-Rev-B1";
|
|
|
|
} else {
|
|
|
|
*dev_name = "MV88F5181-Rev-Unsupported";
|
|
|
|
}
|
2007-10-23 15:14:42 -04:00
|
|
|
} else {
|
|
|
|
*dev_name = "Device-Unknown";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
void __init orion5x_init(void)
|
2007-10-23 15:14:42 -04:00
|
|
|
{
|
|
|
|
char *dev_name;
|
|
|
|
u32 dev, rev;
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
orion5x_id(&dev, &rev, &dev_name);
|
|
|
|
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
|
2007-10-23 15:14:42 -04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup Orion address map
|
|
|
|
*/
|
2008-03-27 14:51:41 -04:00
|
|
|
orion5x_setup_cpu_mbus_bridge();
|
2007-10-23 15:14:42 -04:00
|
|
|
}
|
2008-02-29 15:12:57 -05:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Many orion-based systems have buggy bootloader implementations.
|
|
|
|
* This is a common fixup for bogus memory tags.
|
|
|
|
*/
|
|
|
|
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
|
|
|
|
char **from, struct meminfo *meminfo)
|
|
|
|
{
|
|
|
|
for (; t->hdr.size; t = tag_next(t))
|
|
|
|
if (t->hdr.tag == ATAG_MEM &&
|
|
|
|
(!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
|
|
|
|
t->u.mem.start & ~PAGE_MASK)) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"Clearing invalid memory bank %dKB@0x%08x\n",
|
|
|
|
t->u.mem.size / 1024, t->u.mem.start);
|
|
|
|
t->hdr.tag = 0;
|
|
|
|
}
|
|
|
|
}
|