android_kernel_xiaomi_sm8350/arch/arm/mach-mmp/include/mach/irqs.h

#ifndef __ASM_MACH_IRQS_H
#define __ASM_MACH_IRQS_H

/*
 * Interrupt numbers for PXA168
 */
#define IRQ_PXA168_NONE			(-1)
#define IRQ_PXA168_SSP3			0
#define IRQ_PXA168_SSP2			1
#define IRQ_PXA168_SSP1			2
#define IRQ_PXA168_SSP0			3
#define IRQ_PXA168_PMIC_INT		4
#define IRQ_PXA168_RTC_INT		5
#define IRQ_PXA168_RTC_ALARM		6
#define IRQ_PXA168_TWSI0		7
#define IRQ_PXA168_GPU			8
#define IRQ_PXA168_KEYPAD		9
#define IRQ_PXA168_ONEWIRE		12
#define IRQ_PXA168_TIMER1		13
#define IRQ_PXA168_TIMER2		14
#define IRQ_PXA168_TIMER3		15
#define IRQ_PXA168_CMU			16
#define IRQ_PXA168_SSP4			17
#define IRQ_PXA168_MSP_WAKEUP		19
#define IRQ_PXA168_CF_WAKEUP		20
#define IRQ_PXA168_XD_WAKEUP		21
#define IRQ_PXA168_MFU			22
#define IRQ_PXA168_MSP			23
#define IRQ_PXA168_CF			24
#define IRQ_PXA168_XD			25
#define IRQ_PXA168_DDR_INT		26
#define IRQ_PXA168_UART1		27
#define IRQ_PXA168_UART2		28
#define IRQ_PXA168_WDT			35
#define IRQ_PXA168_FRQ_CHANGE		38
#define IRQ_PXA168_SDH1			39
#define IRQ_PXA168_SDH2			40
#define IRQ_PXA168_LCD			41
#define IRQ_PXA168_CI			42
#define IRQ_PXA168_USB1			44
#define IRQ_PXA168_NAND			45
#define IRQ_PXA168_HIFI_DMA		46
#define IRQ_PXA168_DMA_INT0		47
#define IRQ_PXA168_DMA_INT1		48
#define IRQ_PXA168_GPIOX		49
#define IRQ_PXA168_USB2			51
#define IRQ_PXA168_AC97			57
#define IRQ_PXA168_TWSI1		58
#define IRQ_PXA168_PMU			60
#define IRQ_PXA168_SM_INT		63

#define IRQ_GPIO_START			64
#define IRQ_GPIO_NUM			128
#define IRQ_GPIO(x)			(IRQ_GPIO_START + (x))

#define NR_IRQS		(IRQ_GPIO_START + IRQ_GPIO_NUM)

#endif /* __ASM_MACH_IRQS_H */
[ARM] pxa: add base support for Marvell's PXA168 processor line """The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com> 2009-01-20 01:15:18 -05:00			`#ifndef __ASM_MACH_IRQS_H`
			`#define __ASM_MACH_IRQS_H`

			`/*`
			`* Interrupt numbers for PXA168`
			`*/`
			`#define IRQ_PXA168_NONE (-1)`
			`#define IRQ_PXA168_SSP3 0`
			`#define IRQ_PXA168_SSP2 1`
			`#define IRQ_PXA168_SSP1 2`
			`#define IRQ_PXA168_SSP0 3`
			`#define IRQ_PXA168_PMIC_INT 4`
			`#define IRQ_PXA168_RTC_INT 5`
			`#define IRQ_PXA168_RTC_ALARM 6`
			`#define IRQ_PXA168_TWSI0 7`
			`#define IRQ_PXA168_GPU 8`
			`#define IRQ_PXA168_KEYPAD 9`
			`#define IRQ_PXA168_ONEWIRE 12`
			`#define IRQ_PXA168_TIMER1 13`
			`#define IRQ_PXA168_TIMER2 14`
			`#define IRQ_PXA168_TIMER3 15`
			`#define IRQ_PXA168_CMU 16`
			`#define IRQ_PXA168_SSP4 17`
			`#define IRQ_PXA168_MSP_WAKEUP 19`
			`#define IRQ_PXA168_CF_WAKEUP 20`
			`#define IRQ_PXA168_XD_WAKEUP 21`
			`#define IRQ_PXA168_MFU 22`
			`#define IRQ_PXA168_MSP 23`
			`#define IRQ_PXA168_CF 24`
			`#define IRQ_PXA168_XD 25`
			`#define IRQ_PXA168_DDR_INT 26`
			`#define IRQ_PXA168_UART1 27`
			`#define IRQ_PXA168_UART2 28`
			`#define IRQ_PXA168_WDT 35`
			`#define IRQ_PXA168_FRQ_CHANGE 38`
			`#define IRQ_PXA168_SDH1 39`
			`#define IRQ_PXA168_SDH2 40`
			`#define IRQ_PXA168_LCD 41`
			`#define IRQ_PXA168_CI 42`
			`#define IRQ_PXA168_USB1 44`
			`#define IRQ_PXA168_NAND 45`
			`#define IRQ_PXA168_HIFI_DMA 46`
			`#define IRQ_PXA168_DMA_INT0 47`
			`#define IRQ_PXA168_DMA_INT1 48`
			`#define IRQ_PXA168_GPIOX 49`
			`#define IRQ_PXA168_USB2 51`
			`#define IRQ_PXA168_AC97 57`
			`#define IRQ_PXA168_TWSI1 58`
			`#define IRQ_PXA168_PMU 60`
			`#define IRQ_PXA168_SM_INT 63`

			`#define IRQ_GPIO_START 64`
			`#define IRQ_GPIO_NUM 128`
			`#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))`

			`#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM)`

			`#endif /* __ASM_MACH_IRQS_H */`