2005-04-16 18:20:36 -04:00
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/*
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* FEC instantatiation file for NETTA
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <asm/8xx_immap.h>
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#include <asm/pgtable.h>
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#include <asm/mpc8xx.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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2008-01-25 09:31:42 -05:00
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#include <asm/cpm1.h>
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2005-04-16 18:20:36 -04:00
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#include "fec_8xx.h"
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/*************************************************/
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static struct fec_platform_info fec1_info = {
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.fec_no = 0,
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.use_mdio = 1,
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.phy_addr = 8,
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.fec_irq = SIU_LEVEL1,
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.phy_irq = CPM_IRQ_OFFSET + CPMVEC_PIO_PC6,
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.rx_ring = 128,
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.tx_ring = 16,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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};
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static struct fec_platform_info fec2_info = {
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.fec_no = 1,
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.use_mdio = 1,
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.phy_addr = 2,
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.fec_irq = SIU_LEVEL3,
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.phy_irq = CPM_IRQ_OFFSET + CPMVEC_PIO_PC7,
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.rx_ring = 128,
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.tx_ring = 16,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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};
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static struct net_device *fec1_dev;
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static struct net_device *fec2_dev;
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/* XXX custom u-boot & Linux startup needed */
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extern const char *__fw_getenv(const char *var);
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/* access ports */
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#define setbits32(_addr, _v) __fec_out32(&(_addr), __fec_in32(&(_addr)) | (_v))
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#define clrbits32(_addr, _v) __fec_out32(&(_addr), __fec_in32(&(_addr)) & ~(_v))
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#define setbits16(_addr, _v) __fec_out16(&(_addr), __fec_in16(&(_addr)) | (_v))
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#define clrbits16(_addr, _v) __fec_out16(&(_addr), __fec_in16(&(_addr)) & ~(_v))
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int fec_8xx_platform_init(void)
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{
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immap_t *immap = (immap_t *)IMAP_ADDR;
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bd_t *bd = (bd_t *) __res;
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const char *s;
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char *e;
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int i;
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/* use MDC for MII */
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setbits16(immap->im_ioport.iop_pdpar, 0x0080);
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clrbits16(immap->im_ioport.iop_pddir, 0x0080);
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/* configure FEC1 pins */
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setbits16(immap->im_ioport.iop_papar, 0xe810);
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setbits16(immap->im_ioport.iop_padir, 0x0810);
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clrbits16(immap->im_ioport.iop_padir, 0xe000);
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setbits32(immap->im_cpm.cp_pbpar, 0x00000001);
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clrbits32(immap->im_cpm.cp_pbdir, 0x00000001);
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setbits32(immap->im_cpm.cp_cptr, 0x00000100);
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clrbits32(immap->im_cpm.cp_cptr, 0x00000050);
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clrbits16(immap->im_ioport.iop_pcpar, 0x0200);
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clrbits16(immap->im_ioport.iop_pcdir, 0x0200);
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clrbits16(immap->im_ioport.iop_pcso, 0x0200);
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setbits16(immap->im_ioport.iop_pcint, 0x0200);
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/* configure FEC2 pins */
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setbits32(immap->im_cpm.cp_pepar, 0x00039620);
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setbits32(immap->im_cpm.cp_pedir, 0x00039620);
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setbits32(immap->im_cpm.cp_peso, 0x00031000);
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clrbits32(immap->im_cpm.cp_peso, 0x00008620);
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setbits32(immap->im_cpm.cp_cptr, 0x00000080);
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clrbits32(immap->im_cpm.cp_cptr, 0x00000028);
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clrbits16(immap->im_ioport.iop_pcpar, 0x0200);
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clrbits16(immap->im_ioport.iop_pcdir, 0x0200);
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clrbits16(immap->im_ioport.iop_pcso, 0x0200);
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setbits16(immap->im_ioport.iop_pcint, 0x0200);
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/* fill up */
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fec1_info.sys_clk = bd->bi_intfreq;
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fec2_info.sys_clk = bd->bi_intfreq;
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s = __fw_getenv("ethaddr");
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if (s != NULL) {
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for (i = 0; i < 6; i++) {
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fec1_info.macaddr[i] = simple_strtoul(s, &e, 16);
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if (*e)
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s = e + 1;
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}
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}
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s = __fw_getenv("eth1addr");
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if (s != NULL) {
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for (i = 0; i < 6; i++) {
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fec2_info.macaddr[i] = simple_strtoul(s, &e, 16);
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if (*e)
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s = e + 1;
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}
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}
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fec_8xx_init_one(&fec1_info, &fec1_dev);
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fec_8xx_init_one(&fec2_info, &fec2_dev);
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return fec1_dev != NULL && fec2_dev != NULL ? 0 : -1;
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}
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void fec_8xx_platform_cleanup(void)
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{
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if (fec2_dev != NULL)
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fec_8xx_cleanup_one(fec2_dev);
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if (fec1_dev != NULL)
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fec_8xx_cleanup_one(fec1_dev);
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}
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