114 lines
4.0 KiB
ArmAsm
114 lines
4.0 KiB
ArmAsm
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/* $Id: dtlb_base.S,v 1.17 2001/10/11 22:33:52 davem Exp $
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* dtlb_base.S: Front end to DTLB miss replacement strategy.
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* This is included directly into the trap table.
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*
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* Copyright (C) 1996,1998 David S. Miller (davem@redhat.com)
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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/* %g1 TLB_SFSR (%g1 + %g1 == TLB_TAG_ACCESS)
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* %g2 (KERN_HIGHBITS | KERN_LOWBITS)
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* %g3 VPTE base (0xfffffffe00000000) Spitfire/Blackbird (44-bit VA space)
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* (0xffe0000000000000) Cheetah (64-bit VA space)
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* %g7 __pa(current->mm->pgd)
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*
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* The VPTE base value is completely magic, but note that
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* few places in the kernel other than these TLB miss
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* handlers know anything about the VPTE mechanism or
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* how it works (see VPTE_SIZE, TASK_SIZE and PTRS_PER_PGD).
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* Consider the 44-bit VADDR Ultra-I/II case as an example:
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*
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* VA[0 : (1<<43)] produce VPTE index [%g3 : 0]
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* VA[0 : -(1<<43)] produce VPTE index [%g3-(1<<(43-PAGE_SHIFT+3)) : %g3]
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*
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* For Cheetah's 64-bit VADDR space this is:
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*
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* VA[0 : (1<<63)] produce VPTE index [%g3 : 0]
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* VA[0 : -(1<<63)] produce VPTE index [%g3-(1<<(63-PAGE_SHIFT+3)) : %g3]
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*
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* If you're paying attention you'll notice that this means half of
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* the VPTE table is above %g3 and half is below, low VA addresses
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* map progressively upwards from %g3, and high VA addresses map
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* progressively upwards towards %g3. This trick was needed to make
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* the same 8 instruction handler work both for Spitfire/Blackbird's
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* peculiar VA space hole configuration and the full 64-bit VA space
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* one of Cheetah at the same time.
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*/
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/* Ways we can get here:
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*
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* 1) Nucleus loads and stores to/from PA-->VA direct mappings.
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* 2) Nucleus loads and stores to/from vmalloc() areas.
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* 3) User loads and stores.
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* 4) User space accesses by nucleus at tl0
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*/
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#if PAGE_SHIFT == 13
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/*
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* To compute vpte offset, we need to do ((addr >> 13) << 3),
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* which can be optimized to (addr >> 10) if bits 10/11/12 can
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* be guaranteed to be 0 ... mmu_context.h does guarantee this
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* by only using 10 bits in the hwcontext value.
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*/
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#define CREATE_VPTE_OFFSET1(r1, r2)
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#define CREATE_VPTE_OFFSET2(r1, r2) \
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srax r1, 10, r2
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#define CREATE_VPTE_NOP nop
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#else
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#define CREATE_VPTE_OFFSET1(r1, r2) \
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srax r1, PAGE_SHIFT, r2
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#define CREATE_VPTE_OFFSET2(r1, r2) \
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sllx r2, 3, r2
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#define CREATE_VPTE_NOP
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#endif
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/* DTLB ** ICACHE line 1: Quick user TLB misses */
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ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS
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andcc %g4, TAG_CONTEXT_BITS, %g0 ! From Nucleus?
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from_tl1_trap:
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rdpr %tl, %g5 ! For TL==3 test
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CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset
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be,pn %xcc, 3f ! Yep, special processing
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CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset
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cmp %g5, 4 ! Last trap level?
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be,pn %xcc, longpath ! Yep, cannot risk VPTE miss
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nop ! delay slot
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/* DTLB ** ICACHE line 2: User finish + quick kernel TLB misses */
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ldxa [%g3 + %g6] ASI_S, %g5 ! Load VPTE
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1: brgez,pn %g5, longpath ! Invalid, branch out
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nop ! Delay-slot
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9: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
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retry ! Trap return
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3: brlz,pt %g4, 9b ! Kernel virtual map?
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xor %g2, %g4, %g5 ! Finish bit twiddles
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ba,a,pt %xcc, kvmap ! Yep, go check for obp/vmalloc
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/* DTLB ** ICACHE line 3: winfixups+real_faults */
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longpath:
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rdpr %pstate, %g5 ! Move into alternate globals
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wrpr %g5, PSTATE_AG|PSTATE_MG, %pstate
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rdpr %tl, %g4 ! See where we came from.
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cmp %g4, 1 ! Is etrap/rtrap window fault?
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mov TLB_TAG_ACCESS, %g4 ! Prepare for fault processing
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ldxa [%g4] ASI_DMMU, %g5 ! Load faulting VA page
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be,pt %xcc, sparc64_realfault_common ! Jump to normal fault handling
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mov FAULT_CODE_DTLB, %g4 ! It was read from DTLB
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/* DTLB ** ICACHE line 4: Unused... */
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ba,a,pt %xcc, winfix_trampoline ! Call window fixup code
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nop
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nop
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nop
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nop
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nop
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nop
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CREATE_VPTE_NOP
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#undef CREATE_VPTE_OFFSET1
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#undef CREATE_VPTE_OFFSET2
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#undef CREATE_VPTE_NOP
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