android_kernel_xiaomi_sm8350/include/asm-arm/arch-iop13xx/iq81340.h

#ifndef _IQ81340_H_
#define _IQ81340_H_

#define IQ81340_PCE_BAR0    IOP13XX_PBI_LOWER_MEM_RA
#define IQ81340_PCE_BAR1    (IQ81340_PCE_BAR0 + 0x02000000)

#define IQ81340_FLASHBASE   IQ81340_PCE_BAR0	/* Flash */

#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))

#define IQ81340_PRD_CODE    IQ81340_PCE_BAR1_OFFSET(0)
#define IQ81340_BRD_STEP    IQ81340_PCE_BAR1_OFFSET(0x10000)
#define IQ81340_CPLD_REV    IQ81340_PCE_BAR1_OFFSET(0x20000)
#define IQ81340_LED	     IQ81340_PCE_BAR1_OFFSET(0x30000)
#define IQ81340_LHEX	     IQ81340_PCE_BAR1_OFFSET(0x40000)
#define IQ81340_RHEX	     IQ81340_PCE_BAR1_OFFSET(0x50000)
#define IQ81340_BUZZER	     IQ81340_PCE_BAR1_OFFSET(0x60000)
#define IQ81340_32K_NVRAM   IQ81340_PCE_BAR1_OFFSET(0x70000)
#define IQ81340_256K_NVRAM  IQ81340_PCE_BAR1_OFFSET(0x80000)
#define IQ81340_ROTARY_SW   IQ81340_PCE_BAR1_OFFSET(0xd0000)
#define IQ81340_BATT_STAT   IQ81340_PCE_BAR1_OFFSET(0xf0000)
#define IQ81340_CMP_FLSH    IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */

#define PBI_CF_IDE_BASE     (IQ81340_CMP_FLSH)
#define PBI_CF_BAR_ADDR     (IOP13XX_PBI_BAR1)


#endif	/* _IQ81340_H_ */
[ARM] 3995/1: iop13xx: add iop13xx support The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2006-12-06 20:59:39 -05:00			`#ifndef _IQ81340_H_`
			`#define _IQ81340_H_`

			`#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA`
			`#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)`

			`#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */`

			`#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))`

			`#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)`
			`#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)`
			`#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)`
			`#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)`
			`#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)`
			`#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)`
			`#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)`
			`#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)`
			`#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)`
			`#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)`
			`#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)`
			`#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */`

			`#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)`
			`#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)`

[ARM] 4055/1: iop13xx: fix phys_io/io_pg_offst for iq81340mc/sc The phys_io/io_pg_offst machine record variables were being set to bogus values, causing problems when enabling DEBUG_LL. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2006-12-17 19:01:08 -05:00
[ARM] 3995/1: iop13xx: add iop13xx support The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2006-12-06 20:59:39 -05:00			`#endif /* _IQ81340_H_ */`