174 lines
7.0 KiB
C
174 lines
7.0 KiB
C
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/*
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*
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* Copyright (C) 2002 Intersil Americas Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef _ISL_38XX_H
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#define _ISL_38XX_H
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#include <linux/version.h>
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#include <asm/io.h>
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#include <asm/byteorder.h>
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#define ISL38XX_CB_RX_QSIZE 8
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#define ISL38XX_CB_TX_QSIZE 32
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/* ISL38XX Access Point Specific definitions */
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#define ISL38XX_MAX_WDS_LINKS 8
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/* ISL38xx Client Specific definitions */
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#define ISL38XX_PSM_ACTIVE_STATE 0
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#define ISL38XX_PSM_POWERSAVE_STATE 1
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/* ISL38XX Host Interface Definitions */
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#define ISL38XX_PCI_MEM_SIZE 0x02000
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#define ISL38XX_MEMORY_WINDOW_SIZE 0x01000
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#define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000
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#define ISL38XX_WRITEIO_DELAY 10 /* in us */
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#define ISL38XX_RESET_DELAY 50 /* in ms */
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#define ISL38XX_WAIT_CYCLE 10 /* in 10ms */
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#define ISL38XX_MAX_WAIT_CYCLES 10
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/* PCI Memory Area */
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#define ISL38XX_HARDWARE_REG 0x0000
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#define ISL38XX_CARDBUS_CIS 0x0800
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#define ISL38XX_DIRECT_MEM_WIN 0x1000
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/* Hardware registers */
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#define ISL38XX_DEV_INT_REG 0x0000
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#define ISL38XX_INT_IDENT_REG 0x0010
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#define ISL38XX_INT_ACK_REG 0x0014
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#define ISL38XX_INT_EN_REG 0x0018
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#define ISL38XX_GEN_PURP_COM_REG_1 0x0020
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#define ISL38XX_GEN_PURP_COM_REG_2 0x0024
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#define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1
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#define ISL38XX_DIR_MEM_BASE_REG 0x0030
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#define ISL38XX_CTRL_STAT_REG 0x0078
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/* High end mobos queue up pci writes, the following
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* is used to "read" from after a write to force flush */
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#define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG
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/**
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* isl38xx_w32_flush - PCI iomem write helper
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* @base: (host) memory base address of the device
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* @val: 32bit value (host order) to write
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* @offset: byte offset into @base to write value to
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*
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* This helper takes care of writing a 32bit datum to the
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* specified offset into the device's pci memory space, and making sure
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* the pci memory buffers get flushed by performing one harmless read
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* from the %ISL38XX_PCI_POSTING_FLUSH offset.
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*/
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static inline void
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isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset)
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{
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writel(val, base + offset);
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(void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
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}
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/* Device Interrupt register bits */
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#define ISL38XX_DEV_INT_RESET 0x0001
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#define ISL38XX_DEV_INT_UPDATE 0x0002
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#define ISL38XX_DEV_INT_WAKEUP 0x0008
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#define ISL38XX_DEV_INT_SLEEP 0x0010
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/* Interrupt Identification/Acknowledge/Enable register bits */
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#define ISL38XX_INT_IDENT_UPDATE 0x0002
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#define ISL38XX_INT_IDENT_INIT 0x0004
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#define ISL38XX_INT_IDENT_WAKEUP 0x0008
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#define ISL38XX_INT_IDENT_SLEEP 0x0010
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#define ISL38XX_INT_SOURCES 0x001E
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/* Control/Status register bits */
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/* Looks like there are other meaningful bits
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0x20004400 seen in normal operation,
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0x200044db at 'timeout waiting for mgmt response'
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*/
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#define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200
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#define ISL38XX_CTRL_STAT_CLKRUN 0x00800000
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#define ISL38XX_CTRL_STAT_RESET 0x10000000
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#define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000
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#define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000
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#define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000
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/* Control Block definitions */
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#define ISL38XX_CB_RX_DATA_LQ 0
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#define ISL38XX_CB_TX_DATA_LQ 1
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#define ISL38XX_CB_RX_DATA_HQ 2
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#define ISL38XX_CB_TX_DATA_HQ 3
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#define ISL38XX_CB_RX_MGMTQ 4
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#define ISL38XX_CB_TX_MGMTQ 5
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#define ISL38XX_CB_QCOUNT 6
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#define ISL38XX_CB_MGMT_QSIZE 4
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#define ISL38XX_MIN_QTHRESHOLD 4 /* fragments */
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/* Memory Manager definitions */
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#define MGMT_FRAME_SIZE 1500 /* >= size struct obj_bsslist */
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#define MGMT_TX_FRAME_COUNT 24 /* max 4 + spare 4 + 8 init */
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#define MGMT_RX_FRAME_COUNT 24 /* 4*4 + spare 8 */
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#define MGMT_FRAME_COUNT (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
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#define CONTROL_BLOCK_SIZE 1024 /* should be enough */
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#define PSM_FRAME_SIZE 1536
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#define PSM_MINIMAL_STATION_COUNT 64
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#define PSM_FRAME_COUNT PSM_MINIMAL_STATION_COUNT
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#define PSM_BUFFER_SIZE PSM_FRAME_SIZE * PSM_FRAME_COUNT
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#define MAX_TRAP_RX_QUEUE 4
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#define HOST_MEM_BLOCK CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
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/* Fragment package definitions */
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#define FRAGMENT_FLAG_MF 0x0001
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#define MAX_FRAGMENT_SIZE 1536
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/* In monitor mode frames have a header. I don't know exactly how big those
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* frame can be but I've never seen any frame bigger than 1584... :
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*/
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#define MAX_FRAGMENT_SIZE_RX 1600
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typedef struct {
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u32 address; /* physical address on host */
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u16 size; /* packet size */
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u16 flags; /* set of bit-wise flags */
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} isl38xx_fragment;
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struct isl38xx_cb {
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u32 driver_curr_frag[ISL38XX_CB_QCOUNT];
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u32 device_curr_frag[ISL38XX_CB_QCOUNT];
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isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
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isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
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isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
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isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
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isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
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isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
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};
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typedef struct isl38xx_cb isl38xx_control_block;
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/* determine number of entries currently in queue */
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int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
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void isl38xx_disable_interrupts(void __iomem *);
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void isl38xx_enable_common_interrupts(void __iomem *);
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void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
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void __iomem *);
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void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void __iomem *);
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void isl38xx_trigger_device(int, void __iomem *);
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void isl38xx_interface_reset(void __iomem *, dma_addr_t);
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#endif /* _ISL_38XX_H */
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