301 lines
8.7 KiB
C
301 lines
8.7 KiB
C
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/*
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* Motorola MCG Harrier northbridge/memory controller support
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*
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* Author: Dale Farnsworth
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* dale.farnsworth@mvista.com
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/harrier_defs.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/pci-bridge.h>
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#include <asm/open_pic.h>
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#include <asm/harrier.h>
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/* define defaults for inbound windows */
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#define HARRIER_ITAT_DEFAULT (HARRIER_ITAT_ENA | \
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HARRIER_ITAT_MEM | \
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HARRIER_ITAT_WPE | \
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HARRIER_ITAT_GBL)
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#define HARRIER_MPAT_DEFAULT (HARRIER_ITAT_ENA | \
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HARRIER_ITAT_MEM | \
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HARRIER_ITAT_WPE | \
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HARRIER_ITAT_GBL)
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/*
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* Initialize the inbound window size on a non-monarch harrier.
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*/
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void __init harrier_setup_nonmonarch(uint ppc_reg_base, uint in0_size)
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{
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u16 temps;
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u32 temp;
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if (in0_size > HARRIER_ITSZ_2GB) {
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printk
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("harrier_setup_nonmonarch: Invalid window size code %d\n",
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in0_size);
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return;
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}
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/* Clear the PCI memory enable bit. If we don't, then when the
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* inbound windows are enabled below, the corresponding BARs will be
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* "live" and start answering to PCI memory reads from their default
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* addresses (0x0), which overlap with system RAM.
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*/
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temps = in_le16((u16 *) (ppc_reg_base +
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HARRIER_XCSR_CONFIG(PCI_COMMAND)));
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temps &= ~(PCI_COMMAND_MEMORY);
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out_le16((u16 *) (ppc_reg_base + HARRIER_XCSR_CONFIG(PCI_COMMAND)),
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temps);
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/* Setup a non-prefetchable inbound window */
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out_le32((u32 *) (ppc_reg_base +
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HARRIER_XCSR_CONFIG(HARRIER_ITSZ0_OFF)), in0_size);
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temp = in_le32((u32 *) (ppc_reg_base +
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HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)));
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temp &= ~HARRIER_ITAT_PRE;
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temp |= HARRIER_ITAT_DEFAULT;
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out_le32((u32 *) (ppc_reg_base +
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HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)), temp);
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/* Enable the message passing block */
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temp = in_le32((u32 *) (ppc_reg_base +
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HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)));
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temp |= HARRIER_MPAT_DEFAULT;
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out_le32((u32 *) (ppc_reg_base +
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HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)), temp);
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}
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void __init harrier_release_eready(uint ppc_reg_base)
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{
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ulong temp;
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/*
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* Set EREADY to allow the line to be pulled up after everyone is
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* ready.
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*/
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temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
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temp |= HARRIER_EREADY;
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out_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF), temp);
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}
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void __init harrier_wait_eready(uint ppc_reg_base)
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{
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ulong temp;
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/*
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* Poll the ERDYS line until it goes high to indicate that all
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* non-monarch PrPMCs are ready for bus enumeration (or that there are
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* no PrPMCs present).
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*/
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/* FIXME: Add a timeout of some kind to prevent endless waits. */
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do {
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temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
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} while (!(temp & HARRIER_ERDYS));
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}
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/*
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* Initialize the Motorola MCG Harrier host bridge.
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*
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* This means setting up the PPC bus to PCI memory and I/O space mappings,
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* setting the PCI memory space address of the MPIC (mapped straight
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* through), and ioremap'ing the mpic registers.
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* 'OpenPIC_Addr' will be set correctly by this routine.
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* This routine will not change the PCI_CONFIG_ADDR or PCI_CONFIG_DATA
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* addresses and assumes that the mapping of PCI memory space back to system
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* memory is set up correctly by PPCBug.
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*/
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int __init
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harrier_init(struct pci_controller *hose,
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uint ppc_reg_base,
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ulong processor_pci_mem_start,
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ulong processor_pci_mem_end,
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ulong processor_pci_io_start,
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ulong processor_pci_io_end, ulong processor_mpic_base)
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{
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uint addr, offset;
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/*
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* Some sanity checks...
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*/
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if (((processor_pci_mem_start & 0xffff0000) != processor_pci_mem_start)
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|| ((processor_pci_io_start & 0xffff0000) !=
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processor_pci_io_start)) {
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printk("harrier_init: %s\n",
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"PPC to PCI mappings must start on 64 KB boundaries");
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return -1;
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}
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if (((processor_pci_mem_end & 0x0000ffff) != 0x0000ffff) ||
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((processor_pci_io_end & 0x0000ffff) != 0x0000ffff)) {
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printk("harrier_init: PPC to PCI mappings %s\n",
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"must end just before a 64 KB boundaries");
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return -1;
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}
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if (((processor_pci_mem_end - processor_pci_mem_start) !=
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(hose->mem_space.end - hose->mem_space.start)) ||
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((processor_pci_io_end - processor_pci_io_start) !=
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(hose->io_space.end - hose->io_space.start))) {
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printk("harrier_init: %s\n",
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"PPC and PCI memory or I/O space sizes don't match");
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return -1;
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}
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if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
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printk("harrier_init: %s\n",
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"MPIC address must start on 256 KB boundary");
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return -1;
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}
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if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
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printk("harrier_init: %s\n",
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"pci_dram_offset must be multiple of 64 KB");
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return -1;
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}
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/*
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* Program the OTAD/OTOF registers to set up the PCI Mem & I/O
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* space mappings. These are the mappings going from the processor to
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* the PCI bus.
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*
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* Note: Don't need to 'AND' start/end addresses with 0xffff0000
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* because sanity check above ensures that they are properly
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* aligned.
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*/
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/* Set up PPC->PCI Mem mapping */
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addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
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#ifdef CONFIG_HARRIER_STORE_GATHERING
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offset = (hose->mem_space.start - processor_pci_mem_start) | 0x9a;
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#else
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offset = (hose->mem_space.start - processor_pci_mem_start) | 0x92;
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#endif
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out_be32((uint *) (ppc_reg_base + HARRIER_OTAD0_OFF), addr);
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out_be32((uint *) (ppc_reg_base + HARRIER_OTOF0_OFF), offset);
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/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
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addr = processor_pci_io_start | (processor_pci_io_end >> 16);
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offset = (hose->io_space.start - processor_pci_io_start) | 0x80;
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out_be32((uint *) (ppc_reg_base + HARRIER_OTAD1_OFF), addr);
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out_be32((uint *) (ppc_reg_base + HARRIER_OTOF1_OFF), offset);
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/* Enable MPIC */
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OpenPIC_Addr = (void *)processor_mpic_base;
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addr = (processor_mpic_base >> 16) | 1;
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out_be16((ushort *) (ppc_reg_base + HARRIER_MBAR_OFF), addr);
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out_8((u_char *) (ppc_reg_base + HARRIER_MPIC_CSR_OFF),
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HARRIER_MPIC_OPI_ENABLE);
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return 0;
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}
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/*
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* Find the amount of RAM present.
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* This assumes that PPCBug has initialized the memory controller (SMC)
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* on the Harrier correctly (i.e., it does no sanity checking).
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* It also assumes that the memory base registers are set to configure the
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* memory as contigous starting with "RAM A BASE", "RAM B BASE", etc.
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* however, RAM base registers can be skipped (e.g. A, B, C are set,
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* D is skipped but E is set is okay).
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*/
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#define MB (1024*1024UL)
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static uint harrier_size_table[] __initdata = {
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0 * MB, /* 0 ==> 0 MB */
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32 * MB, /* 1 ==> 32 MB */
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64 * MB, /* 2 ==> 64 MB */
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64 * MB, /* 3 ==> 64 MB */
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128 * MB, /* 4 ==> 128 MB */
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128 * MB, /* 5 ==> 128 MB */
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128 * MB, /* 6 ==> 128 MB */
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256 * MB, /* 7 ==> 256 MB */
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256 * MB, /* 8 ==> 256 MB */
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256 * MB, /* 9 ==> 256 MB */
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512 * MB, /* a ==> 512 MB */
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512 * MB, /* b ==> 512 MB */
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512 * MB, /* c ==> 512 MB */
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1024 * MB, /* d ==> 1024 MB */
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1024 * MB, /* e ==> 1024 MB */
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2048 * MB, /* f ==> 2048 MB */
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};
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/*
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* *** WARNING: You MUST have a BAT set up to map in the XCSR regs ***
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*
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* Read the memory controller's registers to determine the amount of system
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* memory. Assumes that the memory controller registers are already mapped
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* into virtual memory--too early to use ioremap().
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*/
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unsigned long __init harrier_get_mem_size(uint xcsr_base)
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{
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ulong last_addr;
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int i;
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uint vend_dev_id;
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uint *size_table;
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uint val;
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uint *csrp;
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uint size;
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int size_table_entries;
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vend_dev_id = in_be32((uint *) xcsr_base + PCI_VENDOR_ID);
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if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
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printk("harrier_get_mem_size: %s (0x%x)\n",
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"Not a Motorola Memory Controller", vend_dev_id);
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return 0;
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}
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vend_dev_id &= 0x0000ffff;
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if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HARRIER) {
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size_table = harrier_size_table;
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size_table_entries = sizeof(harrier_size_table) /
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sizeof(harrier_size_table[0]);
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} else {
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printk("harrier_get_mem_size: %s (0x%x)\n",
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"Not a Harrier", vend_dev_id);
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return 0;
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}
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last_addr = 0;
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csrp = (uint *) (xcsr_base + HARRIER_SDBA_OFF);
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for (i = 0; i < 8; i++) {
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val = in_be32(csrp++);
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if (val & 0x100) { /* If enabled */
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size = val >> HARRIER_SDB_SIZE_SHIFT;
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size &= HARRIER_SDB_SIZE_MASK;
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if (size >= size_table_entries) {
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break; /* Register not set correctly */
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}
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size = size_table[size];
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val &= ~(size - 1);
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val += size;
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if (val > last_addr) {
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last_addr = val;
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}
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}
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}
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return last_addr;
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}
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