81 lines
1.7 KiB
ArmAsm
81 lines
1.7 KiB
ArmAsm
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/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* Maintained by: Olof Johansson <olof@lixom.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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/* Power savings opcodes since not all binutils have them at this time */
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#define DOZE .long 0x4c000324
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#define NAP .long 0x4c000364
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#define SLEEP .long 0x4c0003a4
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#define RVW .long 0x4c0003e4
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/* Common sequence to do before going to any of the
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* powersavings modes.
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*/
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#define PRE_SLEEP_SEQUENCE \
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std r3,8(r1); \
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ptesync ; \
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ld r3,8(r1); \
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1: cmpd r3,r3; \
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bne 1b
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_doze:
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PRE_SLEEP_SEQUENCE
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DOZE
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b .
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_GLOBAL(idle_spin)
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blr
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_GLOBAL(idle_doze)
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LOAD_REG_ADDR(r3, _doze)
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b sleep_common
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/* Add more modes here later */
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sleep_common:
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mflr r0
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std r0, 16(r1)
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stdu r1,-64(r1)
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LOAD_REG_IMMEDIATE(r6,MSR_DR|MSR_IR|MSR_ME|MSR_EE)
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mfmsr r4
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andc r5,r4,r6
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mtmsrd r5,0
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mtctr r3
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bctrl
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mtmsrd r4,0
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addi r1,r1,64
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ld r0,16(r1)
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mtlr r0
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blr
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