110 lines
5.0 KiB
C
110 lines
5.0 KiB
C
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/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License as published by the Free Software Foundation;
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* either version 2, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
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* the implied warranty of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE.See the GNU General Public License
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* for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "global.h"
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/* For VT3324: */
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struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[] = {
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/* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
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{LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
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{LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
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{LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
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{LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
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{LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
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{LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
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{LCD_PANEL_ID6_1600X1200, 0x0B, 0x03} /* For 1600x1200 */
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};
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struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
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/* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
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DVP1Driving, DFPHigh, DFPLow */
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/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
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SR65, CR97, CR99 */
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/* LCK/VCK < 30000000 will use this value */
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{DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
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0x00},
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/* 30000000 < LCK/VCK < 50000000 will use this value */
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{DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
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0x00},
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/* 50000000 < LCK/VCK < 70000000 will use this value */
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{DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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0x00},
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/* 70000000 < LCK/VCK < 100000000 will use this value */
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{DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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0x00},
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/* 100000000 < LCK/VCK < 15000000 will use this value */
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{DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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0x00},
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/* 15000000 < LCK/VCK will use this value */
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{DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00,
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0x00},
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};
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/* For VT3327: */
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struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[] = {
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/* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */
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{LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */
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{LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */
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{LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */
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{LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */
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{LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */
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{LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */
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{LCD_PANEL_ID6_1600X1200, 0x00, 0x00} /* For 1600x1200 */
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};
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struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
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/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
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DVP1Driving, DFPHigh, DFPLow */
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/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
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SR65, CR97, CR99 */
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/* LCK/VCK < 30000000 will use this value */
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{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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/* 30000000 < LCK/VCK < 50000000 will use this value */
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{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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/* 50000000 < LCK/VCK < 70000000 will use this value */
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{DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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/* 70000000 < LCK/VCK < 100000000 will use this value */
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{DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03},
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/* 100000000 < LCK/VCK < 15000000 will use this value */
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{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02},
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/* 15000000 < LCK/VCK will use this value */
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{DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03},
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};
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/* For VT3364: */
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struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = {
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/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
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DVP1Driving, DFPHigh, DFPLow */
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/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
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SR65, CR97, CR99 */
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/* LCK/VCK < 30000000 will use this value */
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{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 30000000 < LCK/VCK < 50000000 will use this value */
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{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 50000000 < LCK/VCK < 70000000 will use this value */
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{DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 70000000 < LCK/VCK < 100000000 will use this value */
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{DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 100000000 < LCK/VCK < 15000000 will use this value */
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{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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/* 15000000 < LCK/VCK will use this value */
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{DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08},
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};
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