405 lines
8.0 KiB
C
405 lines
8.0 KiB
C
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/*
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* Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
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*
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* Copyright (c) 2003 Intracom S.A.
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* by Pantelis Antoniou <panto@intracom.gr>
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*
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* 2005 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include "fs_enet.h"
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#ifdef CONFIG_8xx
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static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
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{
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immap_t *im = (immap_t *)fs_enet_immap;
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void *dir, *dat, *ppar;
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int adv;
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u8 msk;
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switch (port) {
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case fsiop_porta:
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dir = &im->im_ioport.iop_padir;
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dat = &im->im_ioport.iop_padat;
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ppar = &im->im_ioport.iop_papar;
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break;
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case fsiop_portb:
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dir = &im->im_cpm.cp_pbdir;
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dat = &im->im_cpm.cp_pbdat;
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ppar = &im->im_cpm.cp_pbpar;
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break;
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case fsiop_portc:
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dir = &im->im_ioport.iop_pcdir;
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dat = &im->im_ioport.iop_pcdat;
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ppar = &im->im_ioport.iop_pcpar;
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break;
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case fsiop_portd:
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dir = &im->im_ioport.iop_pddir;
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dat = &im->im_ioport.iop_pddat;
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ppar = &im->im_ioport.iop_pdpar;
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break;
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case fsiop_porte:
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dir = &im->im_cpm.cp_pedir;
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dat = &im->im_cpm.cp_pedat;
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ppar = &im->im_cpm.cp_pepar;
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break;
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default:
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printk(KERN_ERR DRV_MODULE_NAME
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"Illegal port value %d!\n", port);
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return -EINVAL;
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}
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adv = bit >> 3;
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dir = (char *)dir + adv;
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dat = (char *)dat + adv;
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ppar = (char *)ppar + adv;
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msk = 1 << (7 - (bit & 7));
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if ((in_8(ppar) & msk) != 0) {
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printk(KERN_ERR DRV_MODULE_NAME
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"pin %d on port %d is not general purpose!\n", bit, port);
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return -EINVAL;
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}
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*dirp = dir;
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*datp = dat;
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*mskp = msk;
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return 0;
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}
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#endif
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#ifdef CONFIG_8260
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static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
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{
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iop_cpm2_t *io = &((cpm2_map_t *)fs_enet_immap)->im_ioport;
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void *dir, *dat, *ppar;
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int adv;
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u8 msk;
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switch (port) {
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case fsiop_porta:
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dir = &io->iop_pdira;
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dat = &io->iop_pdata;
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ppar = &io->iop_ppara;
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break;
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case fsiop_portb:
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dir = &io->iop_pdirb;
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dat = &io->iop_pdatb;
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ppar = &io->iop_pparb;
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break;
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case fsiop_portc:
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dir = &io->iop_pdirc;
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dat = &io->iop_pdatc;
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ppar = &io->iop_pparc;
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break;
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case fsiop_portd:
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dir = &io->iop_pdird;
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dat = &io->iop_pdatd;
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ppar = &io->iop_ppard;
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break;
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default:
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printk(KERN_ERR DRV_MODULE_NAME
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"Illegal port value %d!\n", port);
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return -EINVAL;
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}
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adv = bit >> 3;
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dir = (char *)dir + adv;
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dat = (char *)dat + adv;
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ppar = (char *)ppar + adv;
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msk = 1 << (7 - (bit & 7));
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if ((in_8(ppar) & msk) != 0) {
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printk(KERN_ERR DRV_MODULE_NAME
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"pin %d on port %d is not general purpose!\n", bit, port);
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return -EINVAL;
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}
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*dirp = dir;
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*datp = dat;
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*mskp = msk;
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return 0;
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}
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#endif
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static inline void bb_set(u8 *p, u8 m)
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{
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out_8(p, in_8(p) | m);
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}
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static inline void bb_clr(u8 *p, u8 m)
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{
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out_8(p, in_8(p) & ~m);
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}
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static inline int bb_read(u8 *p, u8 m)
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{
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return (in_8(p) & m) != 0;
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}
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static inline void mdio_active(struct fs_enet_mii_bus *bus)
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{
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bb_set(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
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}
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static inline void mdio_tristate(struct fs_enet_mii_bus *bus)
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{
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bb_clr(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
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}
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static inline int mdio_read(struct fs_enet_mii_bus *bus)
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{
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return bb_read(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
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}
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static inline void mdio(struct fs_enet_mii_bus *bus, int what)
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{
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if (what)
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bb_set(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
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else
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bb_clr(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
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}
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static inline void mdc(struct fs_enet_mii_bus *bus, int what)
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{
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if (what)
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bb_set(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
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else
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bb_clr(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
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}
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static inline void mii_delay(struct fs_enet_mii_bus *bus)
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{
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udelay(bus->bus_info->i.bitbang.delay);
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}
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/* Utility to send the preamble, address, and register (common to read and write). */
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static void bitbang_pre(struct fs_enet_mii_bus *bus, int read, u8 addr, u8 reg)
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{
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int j;
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/*
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* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
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* The IEEE spec says this is a PHY optional requirement. The AMD
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* 79C874 requires one after power up and one after a MII communications
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* error. This means that we are doing more preambles than we need,
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* but it is safer and will be much more robust.
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*/
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mdio_active(bus);
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mdio(bus, 1);
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for (j = 0; j < 32; j++) {
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mdc(bus, 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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}
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/* send the start bit (01) and the read opcode (10) or write (10) */
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mdc(bus, 0);
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mdio(bus, 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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mdc(bus, 0);
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mdio(bus, 1);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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mdc(bus, 0);
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mdio(bus, read);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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mdc(bus, 0);
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mdio(bus, !read);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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/* send the PHY address */
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for (j = 0; j < 5; j++) {
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mdc(bus, 0);
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mdio(bus, (addr & 0x10) != 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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addr <<= 1;
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}
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/* send the register address */
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for (j = 0; j < 5; j++) {
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mdc(bus, 0);
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mdio(bus, (reg & 0x10) != 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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reg <<= 1;
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}
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}
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static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
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{
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u16 rdreg;
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int ret, j;
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u8 addr = phy_id & 0xff;
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u8 reg = location & 0xff;
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bitbang_pre(bus, 1, addr, reg);
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/* tri-state our MDIO I/O pin so we can read */
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mdc(bus, 0);
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mdio_tristate(bus);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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/* check the turnaround bit: the PHY should be driving it to zero */
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if (mdio_read(bus) != 0) {
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/* PHY didn't drive TA low */
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for (j = 0; j < 32; j++) {
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mdc(bus, 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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}
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ret = -1;
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goto out;
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}
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mdc(bus, 0);
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mii_delay(bus);
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/* read 16 bits of register data, MSB first */
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rdreg = 0;
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for (j = 0; j < 16; j++) {
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mdc(bus, 1);
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mii_delay(bus);
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rdreg <<= 1;
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rdreg |= mdio_read(bus);
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mdc(bus, 0);
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mii_delay(bus);
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}
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mdc(bus, 1);
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mii_delay(bus);
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mdc(bus, 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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ret = rdreg;
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out:
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return ret;
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}
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static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int val)
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{
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int j;
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u8 addr = phy_id & 0xff;
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u8 reg = location & 0xff;
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u16 value = val & 0xffff;
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bitbang_pre(bus, 0, addr, reg);
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/* send the turnaround (10) */
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mdc(bus, 0);
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mdio(bus, 1);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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mdc(bus, 0);
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mdio(bus, 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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/* write 16 bits of register data, MSB first */
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for (j = 0; j < 16; j++) {
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mdc(bus, 0);
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mdio(bus, (value & 0x8000) != 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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value <<= 1;
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}
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/*
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* Tri-state the MDIO line.
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*/
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mdio_tristate(bus);
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mdc(bus, 0);
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mii_delay(bus);
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mdc(bus, 1);
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mii_delay(bus);
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}
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int fs_mii_bitbang_init(struct fs_enet_mii_bus *bus)
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{
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const struct fs_mii_bus_info *bi = bus->bus_info;
|
||
|
|
int r;
|
||
|
|
|
||
|
|
r = bitbang_prep_bit(&bus->bitbang.mdio_dir,
|
||
|
|
&bus->bitbang.mdio_dat,
|
||
|
|
&bus->bitbang.mdio_msk,
|
||
|
|
bi->i.bitbang.mdio_port,
|
||
|
|
bi->i.bitbang.mdio_bit);
|
||
|
|
if (r != 0)
|
||
|
|
return r;
|
||
|
|
|
||
|
|
r = bitbang_prep_bit(&bus->bitbang.mdc_dir,
|
||
|
|
&bus->bitbang.mdc_dat,
|
||
|
|
&bus->bitbang.mdc_msk,
|
||
|
|
bi->i.bitbang.mdc_port,
|
||
|
|
bi->i.bitbang.mdc_bit);
|
||
|
|
if (r != 0)
|
||
|
|
return r;
|
||
|
|
|
||
|
|
bus->mii_read = mii_read;
|
||
|
|
bus->mii_write = mii_write;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|