2005-08-07 01:43:54 -04:00
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/* savage_bci.c -- BCI support for Savage
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*
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* Copyright 2004 Felix Kuehling
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "savage_drm.h"
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#include "savage_drv.h"
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/* Need a long timeout for shadow status updates can take a while
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* and so can waiting for events when the queue is full. */
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2005-09-25 00:28:13 -04:00
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#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
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#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
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2005-08-07 01:43:54 -04:00
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#define SAVAGE_FREELIST_DEBUG 0
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2007-07-11 02:09:54 -04:00
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static int savage_do_cleanup_bci(struct drm_device *dev);
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2006-02-02 03:21:38 -05:00
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2005-08-07 01:43:54 -04:00
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static int
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2005-09-25 00:28:13 -04:00
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savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
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2005-08-07 01:43:54 -04:00
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{
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uint32_t mask = dev_priv->status_used_mask;
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uint32_t threshold = dev_priv->bci_threshold_hi;
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uint32_t status;
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int i;
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#if SAVAGE_BCI_DEBUG
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if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
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DRM_ERROR("Trying to emit %d words "
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"(more than guaranteed space in COB)\n", n);
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#endif
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for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
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DRM_MEMORYBARRIER();
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status = dev_priv->status_ptr[0];
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if ((status & mask) < threshold)
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return 0;
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DRM_UDELAY(1);
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}
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#if SAVAGE_BCI_DEBUG
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DRM_ERROR("failed!\n");
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DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
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#endif
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return DRM_ERR(EBUSY);
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}
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static int
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2005-09-25 00:28:13 -04:00
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savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n)
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2005-08-07 01:43:54 -04:00
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{
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uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
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uint32_t status;
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int i;
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for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
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status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
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if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
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return 0;
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DRM_UDELAY(1);
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}
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#if SAVAGE_BCI_DEBUG
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DRM_ERROR("failed!\n");
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DRM_INFO(" status=0x%08x\n", status);
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#endif
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return DRM_ERR(EBUSY);
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}
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static int
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2005-09-25 00:28:13 -04:00
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savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n)
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2005-08-07 01:43:54 -04:00
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{
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uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
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uint32_t status;
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int i;
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for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
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status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
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if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
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return 0;
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DRM_UDELAY(1);
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}
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#if SAVAGE_BCI_DEBUG
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DRM_ERROR("failed!\n");
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DRM_INFO(" status=0x%08x\n", status);
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#endif
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return DRM_ERR(EBUSY);
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}
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/*
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* Waiting for events.
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*
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* The BIOSresets the event tag to 0 on mode changes. Therefore we
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* never emit 0 to the event tag. If we find a 0 event tag we know the
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* BIOS stomped on it and return success assuming that the BIOS waited
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* for engine idle.
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*
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* Note: if the Xserver uses the event tag it has to follow the same
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* rule. Otherwise there may be glitches every 2^16 events.
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*/
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static int
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2005-09-25 00:28:13 -04:00
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savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
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2005-08-07 01:43:54 -04:00
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{
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uint32_t status;
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int i;
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for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
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DRM_MEMORYBARRIER();
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status = dev_priv->status_ptr[1];
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if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
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(status & 0xffff) == 0)
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return 0;
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DRM_UDELAY(1);
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}
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#if SAVAGE_BCI_DEBUG
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DRM_ERROR("failed!\n");
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DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
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#endif
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return DRM_ERR(EBUSY);
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}
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static int
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2005-09-25 00:28:13 -04:00
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savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e)
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2005-08-07 01:43:54 -04:00
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{
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uint32_t status;
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int i;
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for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
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status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
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if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
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(status & 0xffff) == 0)
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return 0;
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DRM_UDELAY(1);
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}
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#if SAVAGE_BCI_DEBUG
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DRM_ERROR("failed!\n");
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DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
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#endif
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return DRM_ERR(EBUSY);
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}
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2005-09-25 00:28:13 -04:00
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uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
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2005-08-07 01:43:54 -04:00
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unsigned int flags)
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{
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uint16_t count;
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BCI_LOCALS;
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if (dev_priv->status_ptr) {
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/* coordinate with Xserver */
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count = dev_priv->status_ptr[1023];
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if (count < dev_priv->event_counter)
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dev_priv->event_wrap++;
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} else {
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count = dev_priv->event_counter;
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}
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count = (count + 1) & 0xffff;
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if (count == 0) {
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2005-09-25 00:28:13 -04:00
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count++; /* See the comment above savage_wait_event_*. */
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2005-08-07 01:43:54 -04:00
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dev_priv->event_wrap++;
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}
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dev_priv->event_counter = count;
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if (dev_priv->status_ptr)
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2005-09-25 00:28:13 -04:00
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dev_priv->status_ptr[1023] = (uint32_t) count;
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2005-08-07 01:43:54 -04:00
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if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
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unsigned int wait_cmd = BCI_CMD_WAIT;
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if ((flags & SAVAGE_WAIT_2D))
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wait_cmd |= BCI_CMD_WAIT_2D;
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if ((flags & SAVAGE_WAIT_3D))
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wait_cmd |= BCI_CMD_WAIT_3D;
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BEGIN_BCI(2);
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BCI_WRITE(wait_cmd);
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} else {
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BEGIN_BCI(1);
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}
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2005-09-25 00:28:13 -04:00
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BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count);
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2005-08-07 01:43:54 -04:00
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return count;
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}
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/*
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* Freelist management
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*/
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2007-07-11 02:09:54 -04:00
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static int savage_freelist_init(struct drm_device * dev)
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2005-08-07 01:43:54 -04:00
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{
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drm_savage_private_t *dev_priv = dev->dev_private;
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drm_device_dma_t *dma = dev->dma;
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2007-07-11 02:17:42 -04:00
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struct drm_buf *buf;
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2005-08-07 01:43:54 -04:00
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drm_savage_buf_priv_t *entry;
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int i;
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DRM_DEBUG("count=%d\n", dma->buf_count);
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dev_priv->head.next = &dev_priv->tail;
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dev_priv->head.prev = NULL;
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dev_priv->head.buf = NULL;
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dev_priv->tail.next = NULL;
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dev_priv->tail.prev = &dev_priv->head;
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dev_priv->tail.buf = NULL;
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for (i = 0; i < dma->buf_count; i++) {
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buf = dma->buflist[i];
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entry = buf->dev_private;
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SET_AGE(&entry->age, 0, 0);
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entry->buf = buf;
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entry->next = dev_priv->head.next;
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entry->prev = &dev_priv->head;
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dev_priv->head.next->prev = entry;
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dev_priv->head.next = entry;
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}
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return 0;
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}
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2007-07-11 02:17:42 -04:00
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static struct drm_buf *savage_freelist_get(struct drm_device * dev)
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2005-08-07 01:43:54 -04:00
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{
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drm_savage_private_t *dev_priv = dev->dev_private;
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drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
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uint16_t event;
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unsigned int wrap;
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DRM_DEBUG("\n");
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UPDATE_EVENT_COUNTER();
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if (dev_priv->status_ptr)
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event = dev_priv->status_ptr[1] & 0xffff;
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else
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event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
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wrap = dev_priv->event_wrap;
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if (event > dev_priv->event_counter)
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2005-09-25 00:28:13 -04:00
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wrap--; /* hardware hasn't passed the last wrap yet */
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2005-08-07 01:43:54 -04:00
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DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
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DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
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if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
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drm_savage_buf_priv_t *next = tail->next;
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drm_savage_buf_priv_t *prev = tail->prev;
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prev->next = next;
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next->prev = prev;
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tail->next = tail->prev = NULL;
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return tail->buf;
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}
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DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
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return NULL;
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}
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2007-07-11 02:17:42 -04:00
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void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf)
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2005-08-07 01:43:54 -04:00
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{
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drm_savage_private_t *dev_priv = dev->dev_private;
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drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
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DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
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if (entry->next != NULL || entry->prev != NULL) {
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DRM_ERROR("entry already on freelist.\n");
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return;
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}
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prev = &dev_priv->head;
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next = prev->next;
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prev->next = entry;
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next->prev = entry;
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entry->prev = prev;
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entry->next = next;
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}
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/*
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* Command DMA
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*/
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2005-09-25 00:28:13 -04:00
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static int savage_dma_init(drm_savage_private_t * dev_priv)
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2005-08-07 01:43:54 -04:00
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{
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unsigned int i;
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dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
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2005-09-25 00:28:13 -04:00
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(SAVAGE_DMA_PAGE_SIZE * 4);
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2005-08-07 01:43:54 -04:00
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dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
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2005-09-25 00:28:13 -04:00
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dev_priv->nr_dma_pages, DRM_MEM_DRIVER);
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2005-08-07 01:43:54 -04:00
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if (dev_priv->dma_pages == NULL)
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return DRM_ERR(ENOMEM);
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for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
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SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
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dev_priv->dma_pages[i].used = 0;
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dev_priv->dma_pages[i].flushed = 0;
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}
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SET_AGE(&dev_priv->last_dma_age, 0, 0);
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dev_priv->first_dma_page = 0;
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dev_priv->current_dma_page = 0;
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return 0;
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}
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2005-09-25 00:28:13 -04:00
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void savage_dma_reset(drm_savage_private_t * dev_priv)
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2005-08-07 01:43:54 -04:00
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{
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uint16_t event;
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unsigned int wrap, i;
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event = savage_bci_emit_event(dev_priv, 0);
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wrap = dev_priv->event_wrap;
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for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
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SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
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dev_priv->dma_pages[i].used = 0;
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dev_priv->dma_pages[i].flushed = 0;
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}
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|
|
SET_AGE(&dev_priv->last_dma_age, event, wrap);
|
|
|
|
dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
|
|
|
|
}
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
|
|
|
uint16_t event;
|
|
|
|
unsigned int wrap;
|
|
|
|
|
|
|
|
/* Faked DMA buffer pages don't age. */
|
|
|
|
if (dev_priv->cmd_dma == &dev_priv->fake_dma)
|
|
|
|
return;
|
|
|
|
|
|
|
|
UPDATE_EVENT_COUNTER();
|
|
|
|
if (dev_priv->status_ptr)
|
|
|
|
event = dev_priv->status_ptr[1] & 0xffff;
|
|
|
|
else
|
|
|
|
event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
|
|
|
|
wrap = dev_priv->event_wrap;
|
|
|
|
if (event > dev_priv->event_counter)
|
2005-09-25 00:28:13 -04:00
|
|
|
wrap--; /* hardware hasn't passed the last wrap yet */
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
if (dev_priv->dma_pages[page].age.wrap > wrap ||
|
|
|
|
(dev_priv->dma_pages[page].age.wrap == wrap &&
|
|
|
|
dev_priv->dma_pages[page].age.event > event)) {
|
|
|
|
if (dev_priv->wait_evnt(dev_priv,
|
|
|
|
dev_priv->dma_pages[page].age.event)
|
|
|
|
< 0)
|
|
|
|
DRM_ERROR("wait_evnt failed!\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
|
|
|
unsigned int cur = dev_priv->current_dma_page;
|
|
|
|
unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->dma_pages[cur].used;
|
|
|
|
unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
|
|
|
|
SAVAGE_DMA_PAGE_SIZE;
|
2005-08-07 01:43:54 -04:00
|
|
|
uint32_t *dma_ptr;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
|
|
|
|
cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
|
|
|
|
|
|
|
|
if (cur + nr_pages < dev_priv->nr_dma_pages) {
|
2005-09-25 00:28:13 -04:00
|
|
|
dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
|
|
|
|
cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
|
2005-08-07 01:43:54 -04:00
|
|
|
if (n < rest)
|
|
|
|
rest = n;
|
|
|
|
dev_priv->dma_pages[cur].used += rest;
|
|
|
|
n -= rest;
|
|
|
|
cur++;
|
|
|
|
} else {
|
|
|
|
dev_priv->dma_flush(dev_priv);
|
2005-09-25 00:28:13 -04:00
|
|
|
nr_pages =
|
|
|
|
(n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
|
2005-08-07 01:43:54 -04:00
|
|
|
for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
|
|
|
|
dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
|
|
|
|
dev_priv->dma_pages[i].used = 0;
|
|
|
|
dev_priv->dma_pages[i].flushed = 0;
|
|
|
|
}
|
2005-09-25 00:28:13 -04:00
|
|
|
dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle;
|
2005-08-07 01:43:54 -04:00
|
|
|
dev_priv->first_dma_page = cur = 0;
|
|
|
|
}
|
|
|
|
for (i = cur; nr_pages > 0; ++i, --nr_pages) {
|
|
|
|
#if SAVAGE_DMA_DEBUG
|
|
|
|
if (dev_priv->dma_pages[i].used) {
|
|
|
|
DRM_ERROR("unflushed page %u: used=%u\n",
|
|
|
|
i, dev_priv->dma_pages[i].used);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
if (n > SAVAGE_DMA_PAGE_SIZE)
|
|
|
|
dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
|
|
|
|
else
|
|
|
|
dev_priv->dma_pages[i].used = n;
|
|
|
|
n -= SAVAGE_DMA_PAGE_SIZE;
|
|
|
|
}
|
|
|
|
dev_priv->current_dma_page = --i;
|
|
|
|
|
|
|
|
DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
|
|
|
|
i, dev_priv->dma_pages[i].used, n);
|
|
|
|
|
|
|
|
savage_dma_wait(dev_priv, dev_priv->current_dma_page);
|
|
|
|
|
|
|
|
return dma_ptr;
|
|
|
|
}
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
static void savage_dma_flush(drm_savage_private_t * dev_priv)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
|
|
|
unsigned int first = dev_priv->first_dma_page;
|
|
|
|
unsigned int cur = dev_priv->current_dma_page;
|
|
|
|
uint16_t event;
|
|
|
|
unsigned int wrap, pad, align, len, i;
|
|
|
|
unsigned long phys_addr;
|
|
|
|
BCI_LOCALS;
|
|
|
|
|
|
|
|
if (first == cur &&
|
|
|
|
dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* pad length to multiples of 2 entries
|
|
|
|
* align start of next DMA block to multiles of 8 entries */
|
|
|
|
pad = -dev_priv->dma_pages[cur].used & 1;
|
|
|
|
align = -(dev_priv->dma_pages[cur].used + pad) & 7;
|
|
|
|
|
|
|
|
DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
|
|
|
|
"pad=%u, align=%u\n",
|
|
|
|
first, cur, dev_priv->dma_pages[first].flushed,
|
|
|
|
dev_priv->dma_pages[cur].used, pad, align);
|
|
|
|
|
|
|
|
/* pad with noops */
|
|
|
|
if (pad) {
|
2005-09-25 00:28:13 -04:00
|
|
|
uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
|
|
|
|
cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
|
2005-08-07 01:43:54 -04:00
|
|
|
dev_priv->dma_pages[cur].used += pad;
|
2005-09-25 00:28:13 -04:00
|
|
|
while (pad != 0) {
|
2005-08-07 01:43:54 -04:00
|
|
|
*dma_ptr++ = BCI_CMD_WAIT;
|
|
|
|
pad--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_MEMORYBARRIER();
|
|
|
|
|
|
|
|
/* do flush ... */
|
|
|
|
phys_addr = dev_priv->cmd_dma->offset +
|
2005-09-25 00:28:13 -04:00
|
|
|
(first * SAVAGE_DMA_PAGE_SIZE +
|
|
|
|
dev_priv->dma_pages[first].flushed) * 4;
|
2005-08-07 01:43:54 -04:00
|
|
|
len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
DRM_DEBUG("phys_addr=%lx, len=%u\n",
|
|
|
|
phys_addr | dev_priv->dma_type, len);
|
|
|
|
|
|
|
|
BEGIN_BCI(3);
|
|
|
|
BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
|
|
|
|
BCI_WRITE(phys_addr | dev_priv->dma_type);
|
|
|
|
BCI_DMA(len);
|
|
|
|
|
|
|
|
/* fix alignment of the start of the next block */
|
|
|
|
dev_priv->dma_pages[cur].used += align;
|
|
|
|
|
|
|
|
/* age DMA pages */
|
|
|
|
event = savage_bci_emit_event(dev_priv, 0);
|
|
|
|
wrap = dev_priv->event_wrap;
|
|
|
|
for (i = first; i < cur; ++i) {
|
|
|
|
SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
|
|
|
|
dev_priv->dma_pages[i].used = 0;
|
|
|
|
dev_priv->dma_pages[i].flushed = 0;
|
|
|
|
}
|
|
|
|
/* age the current page only when it's full */
|
|
|
|
if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
|
|
|
|
SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
|
|
|
|
dev_priv->dma_pages[cur].used = 0;
|
|
|
|
dev_priv->dma_pages[cur].flushed = 0;
|
|
|
|
/* advance to next page */
|
|
|
|
cur++;
|
|
|
|
if (cur == dev_priv->nr_dma_pages)
|
|
|
|
cur = 0;
|
|
|
|
dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
|
|
|
|
} else {
|
|
|
|
dev_priv->first_dma_page = cur;
|
|
|
|
dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
|
|
|
|
}
|
|
|
|
SET_AGE(&dev_priv->last_dma_age, event, wrap);
|
|
|
|
|
|
|
|
DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
|
|
|
|
dev_priv->dma_pages[cur].used,
|
|
|
|
dev_priv->dma_pages[cur].flushed);
|
|
|
|
}
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
static void savage_fake_dma_flush(drm_savage_private_t * dev_priv)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
|
|
|
unsigned int i, j;
|
|
|
|
BCI_LOCALS;
|
|
|
|
|
|
|
|
if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
|
|
|
|
dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
|
|
|
|
dev_priv->first_dma_page, dev_priv->current_dma_page,
|
|
|
|
dev_priv->dma_pages[dev_priv->current_dma_page].used);
|
|
|
|
|
|
|
|
for (i = dev_priv->first_dma_page;
|
|
|
|
i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
|
|
|
|
++i) {
|
2005-09-25 00:28:13 -04:00
|
|
|
uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
|
|
|
|
i * SAVAGE_DMA_PAGE_SIZE;
|
2005-08-07 01:43:54 -04:00
|
|
|
#if SAVAGE_DMA_DEBUG
|
|
|
|
/* Sanity check: all pages except the last one must be full. */
|
|
|
|
if (i < dev_priv->current_dma_page &&
|
|
|
|
dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
|
|
|
|
DRM_ERROR("partial DMA page %u: used=%u",
|
|
|
|
i, dev_priv->dma_pages[i].used);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
BEGIN_BCI(dev_priv->dma_pages[i].used);
|
|
|
|
for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
|
|
|
|
BCI_WRITE(dma_ptr[j]);
|
|
|
|
}
|
|
|
|
dev_priv->dma_pages[i].used = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* reset to first page */
|
|
|
|
dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
|
|
|
|
}
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
int savage_driver_load(struct drm_device *dev, unsigned long chipset)
|
2005-11-10 06:16:34 -05:00
|
|
|
{
|
|
|
|
drm_savage_private_t *dev_priv;
|
|
|
|
|
|
|
|
dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
|
|
|
|
if (dev_priv == NULL)
|
|
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
|
|
|
|
memset(dev_priv, 0, sizeof(drm_savage_private_t));
|
|
|
|
dev->dev_private = (void *)dev_priv;
|
|
|
|
|
|
|
|
dev_priv->chipset = (enum savage_family)chipset;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-08-07 01:43:54 -04:00
|
|
|
/*
|
|
|
|
* Initalize mappings. On Savage4 and SavageIX the alignment
|
|
|
|
* and size of the aperture is not suitable for automatic MTRR setup
|
2005-11-10 06:16:34 -05:00
|
|
|
* in drm_addmap. Therefore we add them manually before the maps are
|
|
|
|
* initialized, and tear them down on last close.
|
2005-08-07 01:43:54 -04:00
|
|
|
*/
|
2007-07-11 02:09:54 -04:00
|
|
|
int savage_driver_firstopen(struct drm_device *dev)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
2005-11-10 06:16:34 -05:00
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
2005-08-07 01:43:54 -04:00
|
|
|
unsigned long mmio_base, fb_base, fb_size, aperture_base;
|
|
|
|
/* fb_rsrc and aper_rsrc aren't really used currently, but still exist
|
|
|
|
* in case we decide we need information on the BAR for BSD in the
|
|
|
|
* future.
|
|
|
|
*/
|
|
|
|
unsigned int fb_rsrc, aper_rsrc;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
dev_priv->mtrr[0].handle = -1;
|
|
|
|
dev_priv->mtrr[1].handle = -1;
|
|
|
|
dev_priv->mtrr[2].handle = -1;
|
|
|
|
if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
|
|
|
|
fb_rsrc = 0;
|
|
|
|
fb_base = drm_get_resource_start(dev, 0);
|
|
|
|
fb_size = SAVAGE_FB_SIZE_S3;
|
|
|
|
mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
|
|
|
|
aper_rsrc = 0;
|
|
|
|
aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
|
|
|
|
/* this should always be true */
|
|
|
|
if (drm_get_resource_len(dev, 0) == 0x08000000) {
|
|
|
|
/* Don't make MMIO write-cobining! We need 3
|
|
|
|
* MTRRs. */
|
|
|
|
dev_priv->mtrr[0].base = fb_base;
|
|
|
|
dev_priv->mtrr[0].size = 0x01000000;
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->mtrr[0].handle =
|
2006-01-02 00:23:01 -05:00
|
|
|
drm_mtrr_add(dev_priv->mtrr[0].base,
|
|
|
|
dev_priv->mtrr[0].size, DRM_MTRR_WC);
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->mtrr[1].base = fb_base + 0x02000000;
|
2005-08-07 01:43:54 -04:00
|
|
|
dev_priv->mtrr[1].size = 0x02000000;
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->mtrr[1].handle =
|
2006-01-02 00:23:01 -05:00
|
|
|
drm_mtrr_add(dev_priv->mtrr[1].base,
|
|
|
|
dev_priv->mtrr[1].size, DRM_MTRR_WC);
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->mtrr[2].base = fb_base + 0x04000000;
|
2005-08-07 01:43:54 -04:00
|
|
|
dev_priv->mtrr[2].size = 0x04000000;
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->mtrr[2].handle =
|
2006-01-02 00:23:01 -05:00
|
|
|
drm_mtrr_add(dev_priv->mtrr[2].base,
|
|
|
|
dev_priv->mtrr[2].size, DRM_MTRR_WC);
|
2005-08-07 01:43:54 -04:00
|
|
|
} else {
|
|
|
|
DRM_ERROR("strange pci_resource_len %08lx\n",
|
|
|
|
drm_get_resource_len(dev, 0));
|
|
|
|
}
|
2005-11-10 06:16:34 -05:00
|
|
|
} else if (dev_priv->chipset != S3_SUPERSAVAGE &&
|
|
|
|
dev_priv->chipset != S3_SAVAGE2000) {
|
2005-08-07 01:43:54 -04:00
|
|
|
mmio_base = drm_get_resource_start(dev, 0);
|
|
|
|
fb_rsrc = 1;
|
|
|
|
fb_base = drm_get_resource_start(dev, 1);
|
|
|
|
fb_size = SAVAGE_FB_SIZE_S4;
|
|
|
|
aper_rsrc = 1;
|
|
|
|
aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
|
|
|
|
/* this should always be true */
|
|
|
|
if (drm_get_resource_len(dev, 1) == 0x08000000) {
|
|
|
|
/* Can use one MTRR to cover both fb and
|
|
|
|
* aperture. */
|
|
|
|
dev_priv->mtrr[0].base = fb_base;
|
|
|
|
dev_priv->mtrr[0].size = 0x08000000;
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->mtrr[0].handle =
|
2006-01-02 00:23:01 -05:00
|
|
|
drm_mtrr_add(dev_priv->mtrr[0].base,
|
|
|
|
dev_priv->mtrr[0].size, DRM_MTRR_WC);
|
2005-08-07 01:43:54 -04:00
|
|
|
} else {
|
|
|
|
DRM_ERROR("strange pci_resource_len %08lx\n",
|
|
|
|
drm_get_resource_len(dev, 1));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
mmio_base = drm_get_resource_start(dev, 0);
|
|
|
|
fb_rsrc = 1;
|
|
|
|
fb_base = drm_get_resource_start(dev, 1);
|
|
|
|
fb_size = drm_get_resource_len(dev, 1);
|
|
|
|
aper_rsrc = 2;
|
|
|
|
aperture_base = drm_get_resource_start(dev, 2);
|
|
|
|
/* Automatic MTRR setup will do the right thing. */
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
|
|
|
|
_DRM_READ_ONLY, &dev_priv->mmio);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
|
|
|
|
_DRM_WRITE_COMBINING, &dev_priv->fb);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
|
|
|
|
_DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
|
|
|
|
&dev_priv->aperture);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Delete MTRRs and free device-private data.
|
|
|
|
*/
|
2007-07-11 02:09:54 -04:00
|
|
|
void savage_driver_lastclose(struct drm_device *dev)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; ++i)
|
|
|
|
if (dev_priv->mtrr[i].handle >= 0)
|
2006-01-02 00:23:01 -05:00
|
|
|
drm_mtrr_del(dev_priv->mtrr[i].handle,
|
2005-08-07 01:43:54 -04:00
|
|
|
dev_priv->mtrr[i].base,
|
2006-01-02 00:23:01 -05:00
|
|
|
dev_priv->mtrr[i].size, DRM_MTRR_WC);
|
2005-11-10 06:16:34 -05:00
|
|
|
}
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
int savage_driver_unload(struct drm_device *dev)
|
2005-11-10 06:16:34 -05:00
|
|
|
{
|
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
static int savage_do_init_bci(struct drm_device * dev, drm_savage_init_t * init)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (init->fb_bpp != 16 && init->fb_bpp != 32) {
|
|
|
|
DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
if (init->depth_bpp != 16 && init->depth_bpp != 32) {
|
|
|
|
DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
if (init->dma_type != SAVAGE_DMA_AGP &&
|
|
|
|
init->dma_type != SAVAGE_DMA_PCI) {
|
|
|
|
DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_priv->cob_size = init->cob_size;
|
|
|
|
dev_priv->bci_threshold_lo = init->bci_threshold_lo;
|
|
|
|
dev_priv->bci_threshold_hi = init->bci_threshold_hi;
|
|
|
|
dev_priv->dma_type = init->dma_type;
|
|
|
|
|
|
|
|
dev_priv->fb_bpp = init->fb_bpp;
|
|
|
|
dev_priv->front_offset = init->front_offset;
|
|
|
|
dev_priv->front_pitch = init->front_pitch;
|
|
|
|
dev_priv->back_offset = init->back_offset;
|
|
|
|
dev_priv->back_pitch = init->back_pitch;
|
|
|
|
dev_priv->depth_bpp = init->depth_bpp;
|
|
|
|
dev_priv->depth_offset = init->depth_offset;
|
|
|
|
dev_priv->depth_pitch = init->depth_pitch;
|
|
|
|
|
|
|
|
dev_priv->texture_offset = init->texture_offset;
|
|
|
|
dev_priv->texture_size = init->texture_size;
|
|
|
|
|
2007-05-25 15:04:51 -04:00
|
|
|
dev_priv->sarea = drm_getsarea(dev);
|
2005-08-07 01:43:54 -04:00
|
|
|
if (!dev_priv->sarea) {
|
|
|
|
DRM_ERROR("could not find sarea!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
if (init->status_offset != 0) {
|
|
|
|
dev_priv->status = drm_core_findmap(dev, init->status_offset);
|
|
|
|
if (!dev_priv->status) {
|
|
|
|
DRM_ERROR("could not find shadow status region!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
dev_priv->status = NULL;
|
|
|
|
}
|
|
|
|
if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
|
2006-10-24 07:46:55 -04:00
|
|
|
dev->agp_buffer_token = init->buffers_offset;
|
2005-08-07 01:43:54 -04:00
|
|
|
dev->agp_buffer_map = drm_core_findmap(dev,
|
|
|
|
init->buffers_offset);
|
|
|
|
if (!dev->agp_buffer_map) {
|
|
|
|
DRM_ERROR("could not find DMA buffer region!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
drm_core_ioremap(dev->agp_buffer_map, dev);
|
|
|
|
if (!dev->agp_buffer_map) {
|
|
|
|
DRM_ERROR("failed to ioremap DMA buffer region!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (init->agp_textures_offset) {
|
|
|
|
dev_priv->agp_textures =
|
2005-09-25 00:28:13 -04:00
|
|
|
drm_core_findmap(dev, init->agp_textures_offset);
|
2005-08-07 01:43:54 -04:00
|
|
|
if (!dev_priv->agp_textures) {
|
|
|
|
DRM_ERROR("could not find agp texture region!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
dev_priv->agp_textures = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (init->cmd_dma_offset) {
|
|
|
|
if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
|
|
|
|
DRM_ERROR("command DMA not supported on "
|
|
|
|
"Savage3D/MX/IX.\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
if (dev->dma && dev->dma->buflist) {
|
|
|
|
DRM_ERROR("command and vertex DMA not supported "
|
|
|
|
"at the same time.\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset);
|
|
|
|
if (!dev_priv->cmd_dma) {
|
|
|
|
DRM_ERROR("could not find command DMA region!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
|
|
|
|
if (dev_priv->cmd_dma->type != _DRM_AGP) {
|
|
|
|
DRM_ERROR("AGP command DMA region is not a "
|
|
|
|
"_DRM_AGP map!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
drm_core_ioremap(dev_priv->cmd_dma, dev);
|
|
|
|
if (!dev_priv->cmd_dma->handle) {
|
|
|
|
DRM_ERROR("failed to ioremap command "
|
|
|
|
"DMA region!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
}
|
|
|
|
} else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
|
|
|
|
DRM_ERROR("PCI command DMA region is not a "
|
|
|
|
"_DRM_CONSISTENT map!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
dev_priv->cmd_dma = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_priv->dma_flush = savage_dma_flush;
|
|
|
|
if (!dev_priv->cmd_dma) {
|
|
|
|
DRM_DEBUG("falling back to faked command DMA.\n");
|
|
|
|
dev_priv->fake_dma.offset = 0;
|
|
|
|
dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
|
|
|
|
dev_priv->fake_dma.type = _DRM_SHM;
|
|
|
|
dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE,
|
|
|
|
DRM_MEM_DRIVER);
|
|
|
|
if (!dev_priv->fake_dma.handle) {
|
|
|
|
DRM_ERROR("could not allocate faked DMA buffer!\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
}
|
|
|
|
dev_priv->cmd_dma = &dev_priv->fake_dma;
|
|
|
|
dev_priv->dma_flush = savage_fake_dma_flush;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_priv->sarea_priv =
|
2005-09-25 00:28:13 -04:00
|
|
|
(drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle +
|
|
|
|
init->sarea_priv_offset);
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
/* setup bitmap descriptors */
|
|
|
|
{
|
|
|
|
unsigned int color_tile_format;
|
|
|
|
unsigned int depth_tile_format;
|
|
|
|
unsigned int front_stride, back_stride, depth_stride;
|
|
|
|
if (dev_priv->chipset <= S3_SAVAGE4) {
|
|
|
|
color_tile_format = dev_priv->fb_bpp == 16 ?
|
2005-09-25 00:28:13 -04:00
|
|
|
SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
|
2005-08-07 01:43:54 -04:00
|
|
|
depth_tile_format = dev_priv->depth_bpp == 16 ?
|
2005-09-25 00:28:13 -04:00
|
|
|
SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
|
2005-08-07 01:43:54 -04:00
|
|
|
} else {
|
|
|
|
color_tile_format = SAVAGE_BD_TILE_DEST;
|
|
|
|
depth_tile_format = SAVAGE_BD_TILE_DEST;
|
|
|
|
}
|
2005-09-25 00:28:13 -04:00
|
|
|
front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
|
|
|
|
back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
|
|
|
|
depth_stride =
|
|
|
|
dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
|
2005-09-25 00:28:13 -04:00
|
|
|
(dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
|
|
|
|
(color_tile_format << SAVAGE_BD_TILE_SHIFT);
|
2005-08-07 01:43:54 -04:00
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
|
|
|
|
(dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
|
|
|
|
(color_tile_format << SAVAGE_BD_TILE_SHIFT);
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
|
2005-09-25 00:28:13 -04:00
|
|
|
(dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
|
|
|
|
(depth_tile_format << SAVAGE_BD_TILE_SHIFT);
|
2005-08-07 01:43:54 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* setup status and bci ptr */
|
|
|
|
dev_priv->event_counter = 0;
|
|
|
|
dev_priv->event_wrap = 0;
|
|
|
|
dev_priv->bci_ptr = (volatile uint32_t *)
|
2005-09-25 00:28:13 -04:00
|
|
|
((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
|
2005-08-07 01:43:54 -04:00
|
|
|
if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
|
|
|
|
dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
|
|
|
|
} else {
|
|
|
|
dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
|
|
|
|
}
|
|
|
|
if (dev_priv->status != NULL) {
|
|
|
|
dev_priv->status_ptr =
|
2005-09-25 00:28:13 -04:00
|
|
|
(volatile uint32_t *)dev_priv->status->handle;
|
2005-08-07 01:43:54 -04:00
|
|
|
dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
|
|
|
|
dev_priv->wait_evnt = savage_bci_wait_event_shadow;
|
|
|
|
dev_priv->status_ptr[1023] = dev_priv->event_counter;
|
|
|
|
} else {
|
|
|
|
dev_priv->status_ptr = NULL;
|
|
|
|
if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
|
|
|
|
dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
|
|
|
|
} else {
|
|
|
|
dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
|
|
|
|
}
|
|
|
|
dev_priv->wait_evnt = savage_bci_wait_event_reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* cliprect functions */
|
|
|
|
if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
|
|
|
|
dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
|
|
|
|
else
|
|
|
|
dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
|
|
|
|
|
|
|
|
if (savage_freelist_init(dev) < 0) {
|
|
|
|
DRM_ERROR("could not initialize freelist\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
}
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
if (savage_dma_init(dev_priv) < 0) {
|
2005-08-07 01:43:54 -04:00
|
|
|
DRM_ERROR("could not initialize command DMA\n");
|
|
|
|
savage_do_cleanup_bci(dev);
|
|
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
static int savage_do_cleanup_bci(struct drm_device * dev)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
|
|
|
|
if (dev_priv->fake_dma.handle)
|
|
|
|
drm_free(dev_priv->fake_dma.handle,
|
|
|
|
SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER);
|
|
|
|
} else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
|
|
|
|
dev_priv->cmd_dma->type == _DRM_AGP &&
|
|
|
|
dev_priv->dma_type == SAVAGE_DMA_AGP)
|
|
|
|
drm_core_ioremapfree(dev_priv->cmd_dma, dev);
|
|
|
|
|
|
|
|
if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
|
|
|
|
dev->agp_buffer_map && dev->agp_buffer_map->handle) {
|
|
|
|
drm_core_ioremapfree(dev->agp_buffer_map, dev);
|
|
|
|
/* make sure the next instance (which may be running
|
|
|
|
* in PCI mode) doesn't try to use an old
|
|
|
|
* agp_buffer_map. */
|
|
|
|
dev->agp_buffer_map = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->dma_pages)
|
|
|
|
drm_free(dev_priv->dma_pages,
|
2005-09-25 00:28:13 -04:00
|
|
|
sizeof(drm_savage_dma_page_t) * dev_priv->nr_dma_pages,
|
2005-08-07 01:43:54 -04:00
|
|
|
DRM_MEM_DRIVER);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int savage_bci_init(DRM_IOCTL_ARGS)
|
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_savage_init_t init;
|
|
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *) data,
|
2005-08-07 01:43:54 -04:00
|
|
|
sizeof(init));
|
|
|
|
|
|
|
|
switch (init.func) {
|
|
|
|
case SAVAGE_INIT_BCI:
|
|
|
|
return savage_do_init_bci(dev, &init);
|
|
|
|
case SAVAGE_CLEANUP_BCI:
|
|
|
|
return savage_do_cleanup_bci(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int savage_bci_event_emit(DRM_IOCTL_ARGS)
|
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_savage_event_emit_t event;
|
|
|
|
|
|
|
|
DRM_DEBUG("\n");
|
|
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *) data,
|
2005-08-07 01:43:54 -04:00
|
|
|
sizeof(event));
|
|
|
|
|
|
|
|
event.count = savage_bci_emit_event(dev_priv, event.flags);
|
|
|
|
event.count |= dev_priv->event_wrap << 16;
|
2006-12-19 01:20:02 -05:00
|
|
|
DRM_COPY_TO_USER_IOCTL((drm_savage_event_emit_t __user *) data,
|
|
|
|
event, sizeof(event));
|
2005-08-07 01:43:54 -04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int savage_bci_event_wait(DRM_IOCTL_ARGS)
|
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
|
|
|
drm_savage_event_wait_t event;
|
|
|
|
unsigned int event_e, hw_e;
|
|
|
|
unsigned int event_w, hw_w;
|
|
|
|
|
|
|
|
DRM_DEBUG("\n");
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *) data,
|
2005-08-07 01:43:54 -04:00
|
|
|
sizeof(event));
|
|
|
|
|
|
|
|
UPDATE_EVENT_COUNTER();
|
|
|
|
if (dev_priv->status_ptr)
|
|
|
|
hw_e = dev_priv->status_ptr[1] & 0xffff;
|
|
|
|
else
|
|
|
|
hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
|
|
|
|
hw_w = dev_priv->event_wrap;
|
|
|
|
if (hw_e > dev_priv->event_counter)
|
2005-09-25 00:28:13 -04:00
|
|
|
hw_w--; /* hardware hasn't passed the last wrap yet */
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
event_e = event.count & 0xffff;
|
|
|
|
event_w = event.count >> 16;
|
|
|
|
|
|
|
|
/* Don't need to wait if
|
|
|
|
* - event counter wrapped since the event was emitted or
|
|
|
|
* - the hardware has advanced up to or over the event to wait for.
|
|
|
|
*/
|
2005-09-25 00:28:13 -04:00
|
|
|
if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
|
2005-08-07 01:43:54 -04:00
|
|
|
return 0;
|
|
|
|
else
|
|
|
|
return dev_priv->wait_evnt(dev_priv, event_e);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DMA buffer management
|
|
|
|
*/
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
static int savage_bci_get_buffers(DRMFILE filp, struct drm_device *dev, struct drm_dma *d)
|
2005-08-07 01:43:54 -04:00
|
|
|
{
|
2007-07-11 02:17:42 -04:00
|
|
|
struct drm_buf *buf;
|
2005-08-07 01:43:54 -04:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = d->granted_count; i < d->request_count; i++) {
|
|
|
|
buf = savage_freelist_get(dev);
|
|
|
|
if (!buf)
|
|
|
|
return DRM_ERR(EAGAIN);
|
|
|
|
|
|
|
|
buf->filp = filp;
|
|
|
|
|
|
|
|
if (DRM_COPY_TO_USER(&d->request_indices[i],
|
|
|
|
&buf->idx, sizeof(buf->idx)))
|
|
|
|
return DRM_ERR(EFAULT);
|
|
|
|
if (DRM_COPY_TO_USER(&d->request_sizes[i],
|
|
|
|
&buf->total, sizeof(buf->total)))
|
|
|
|
return DRM_ERR(EFAULT);
|
|
|
|
|
|
|
|
d->granted_count++;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int savage_bci_buffers(DRM_IOCTL_ARGS)
|
|
|
|
{
|
|
|
|
DRM_DEVICE;
|
|
|
|
drm_device_dma_t *dma = dev->dma;
|
2007-07-11 02:09:54 -04:00
|
|
|
struct drm_dma d;
|
2005-08-07 01:43:54 -04:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
DRM_COPY_FROM_USER_IOCTL(d, (struct drm_dma __user *) data, sizeof(d));
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
/* Please don't send us buffers.
|
|
|
|
*/
|
|
|
|
if (d.send_count != 0) {
|
|
|
|
DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
|
|
|
|
DRM_CURRENTPID, d.send_count);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We'll send you buffers.
|
|
|
|
*/
|
|
|
|
if (d.request_count < 0 || d.request_count > dma->buf_count) {
|
|
|
|
DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
|
|
|
|
DRM_CURRENTPID, d.request_count, dma->buf_count);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
d.granted_count = 0;
|
|
|
|
|
|
|
|
if (d.request_count) {
|
|
|
|
ret = savage_bci_get_buffers(filp, dev, &d);
|
|
|
|
}
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
DRM_COPY_TO_USER_IOCTL((struct drm_dma __user *) data, d, sizeof(d));
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2007-07-11 02:09:54 -04:00
|
|
|
void savage_reclaim_buffers(struct drm_device *dev, DRMFILE filp)
|
2005-09-25 00:28:13 -04:00
|
|
|
{
|
2005-08-07 01:43:54 -04:00
|
|
|
drm_device_dma_t *dma = dev->dma;
|
|
|
|
drm_savage_private_t *dev_priv = dev->dev_private;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!dma)
|
|
|
|
return;
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
if (!dma->buflist)
|
|
|
|
return;
|
|
|
|
|
2005-09-25 00:28:13 -04:00
|
|
|
/*i830_flush_queue(dev); */
|
2005-08-07 01:43:54 -04:00
|
|
|
|
|
|
|
for (i = 0; i < dma->buf_count; i++) {
|
2007-07-11 02:17:42 -04:00
|
|
|
struct drm_buf *buf = dma->buflist[i];
|
2005-08-07 01:43:54 -04:00
|
|
|
drm_savage_buf_priv_t *buf_priv = buf->dev_private;
|
|
|
|
|
|
|
|
if (buf->filp == filp && buf_priv &&
|
|
|
|
buf_priv->next == NULL && buf_priv->prev == NULL) {
|
|
|
|
uint16_t event;
|
|
|
|
DRM_DEBUG("reclaimed from client\n");
|
|
|
|
event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
|
|
|
|
SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
|
|
|
|
savage_freelist_put(dev, buf);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
drm_core_reclaim_buffers(dev, filp);
|
|
|
|
}
|
|
|
|
|
|
|
|
drm_ioctl_desc_t savage_ioctls[] = {
|
2006-01-01 21:54:04 -05:00
|
|
|
[DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
|
|
|
|
[DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, DRM_AUTH},
|
|
|
|
[DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, DRM_AUTH},
|
|
|
|
[DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, DRM_AUTH},
|
2005-08-07 01:43:54 -04:00
|
|
|
};
|
|
|
|
|
|
|
|
int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
|