[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 16:45:02 -04:00
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/*
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* arch/arm/mach-loki/common.c
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*
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* Core functions for Marvell Loki (88RC8480) SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/mbus.h>
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#include <linux/mv643xx_eth.h>
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#include <asm/page.h>
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#include <asm/timex.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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2008-08-05 11:14:15 -04:00
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#include <mach/loki.h>
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2008-08-09 07:44:58 -04:00
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#include <plat/orion_nand.h>
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#include <plat/time.h>
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[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 16:45:02 -04:00
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc loki_io_desc[] __initdata = {
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{
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.virtual = LOKI_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
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.length = LOKI_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init loki_map_io(void)
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{
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iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
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}
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/*****************************************************************************
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* GE0
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
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.t_clk = LOKI_TCLK,
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.dram = &loki_mbus_dram_info,
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};
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static struct resource loki_ge0_shared_resources[] = {
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{
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.name = "ge0 base",
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.start = GE0_PHYS_BASE + 0x2000,
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.end = GE0_PHYS_BASE + 0x3fff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device loki_ge0_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 0,
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.dev = {
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.platform_data = &loki_ge0_shared_data,
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},
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.num_resources = 1,
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.resource = loki_ge0_shared_resources,
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};
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static struct resource loki_ge0_resources[] = {
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{
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.name = "ge0 irq",
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.start = IRQ_LOKI_GBE_A_INT,
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.end = IRQ_LOKI_GBE_A_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device loki_ge0 = {
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.name = MV643XX_ETH_NAME,
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.id = 0,
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.num_resources = 1,
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.resource = loki_ge0_resources,
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2009-05-22 16:53:40 -04:00
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 16:45:02 -04:00
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};
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void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
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{
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eth_data->shared = &loki_ge0_shared;
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loki_ge0.dev.platform_data = eth_data;
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writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
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platform_device_register(&loki_ge0_shared);
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platform_device_register(&loki_ge0);
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}
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/*****************************************************************************
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* GE1
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
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.t_clk = LOKI_TCLK,
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.dram = &loki_mbus_dram_info,
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};
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static struct resource loki_ge1_shared_resources[] = {
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{
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.name = "ge1 base",
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.start = GE1_PHYS_BASE + 0x2000,
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.end = GE1_PHYS_BASE + 0x3fff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device loki_ge1_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 1,
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.dev = {
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.platform_data = &loki_ge1_shared_data,
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},
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.num_resources = 1,
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.resource = loki_ge1_shared_resources,
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};
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static struct resource loki_ge1_resources[] = {
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{
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.name = "ge1 irq",
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.start = IRQ_LOKI_GBE_B_INT,
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.end = IRQ_LOKI_GBE_B_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device loki_ge1 = {
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.name = MV643XX_ETH_NAME,
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.id = 1,
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.num_resources = 1,
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.resource = loki_ge1_resources,
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2009-05-22 16:53:40 -04:00
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 16:45:02 -04:00
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};
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void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
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{
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eth_data->shared = &loki_ge1_shared;
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loki_ge1.dev.platform_data = eth_data;
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writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
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platform_device_register(&loki_ge1_shared);
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platform_device_register(&loki_ge1);
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}
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/*****************************************************************************
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* SAS/SATA
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****************************************************************************/
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static struct resource loki_sas_resources[] = {
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{
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.name = "mvsas0 mem",
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.start = SAS0_PHYS_BASE,
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.end = SAS0_PHYS_BASE + 0x01ff,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "mvsas0 irq",
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.start = IRQ_LOKI_SAS_A,
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.end = IRQ_LOKI_SAS_A,
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.flags = IORESOURCE_IRQ,
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}, {
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.name = "mvsas1 mem",
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.start = SAS1_PHYS_BASE,
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.end = SAS1_PHYS_BASE + 0x01ff,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "mvsas1 irq",
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.start = IRQ_LOKI_SAS_B,
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.end = IRQ_LOKI_SAS_B,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device loki_sas = {
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.name = "mvsas",
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.id = 0,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(loki_sas_resources),
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.resource = loki_sas_resources,
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};
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void __init loki_sas_init(void)
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{
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writel(0x8300f707, DDR_REG(0x1424));
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platform_device_register(&loki_sas);
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}
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/*****************************************************************************
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* UART0
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****************************************************************************/
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static struct plat_serial8250_port loki_uart0_data[] = {
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{
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.mapbase = UART0_PHYS_BASE,
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.membase = (char *)UART0_VIRT_BASE,
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.irq = IRQ_LOKI_UART0,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = LOKI_TCLK,
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}, {
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},
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};
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static struct resource loki_uart0_resources[] = {
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{
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.start = UART0_PHYS_BASE,
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.end = UART0_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_LOKI_UART0,
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.end = IRQ_LOKI_UART0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device loki_uart0 = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = loki_uart0_data,
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},
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.resource = loki_uart0_resources,
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.num_resources = ARRAY_SIZE(loki_uart0_resources),
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};
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void __init loki_uart0_init(void)
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{
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platform_device_register(&loki_uart0);
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}
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/*****************************************************************************
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* UART1
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****************************************************************************/
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static struct plat_serial8250_port loki_uart1_data[] = {
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{
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.mapbase = UART1_PHYS_BASE,
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.membase = (char *)UART1_VIRT_BASE,
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.irq = IRQ_LOKI_UART1,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = LOKI_TCLK,
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}, {
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},
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};
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static struct resource loki_uart1_resources[] = {
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{
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.start = UART1_PHYS_BASE,
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.end = UART1_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_LOKI_UART1,
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.end = IRQ_LOKI_UART1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device loki_uart1 = {
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.name = "serial8250",
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.id = 1,
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.dev = {
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.platform_data = loki_uart1_data,
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},
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.resource = loki_uart1_resources,
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.num_resources = ARRAY_SIZE(loki_uart1_resources),
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};
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void __init loki_uart1_init(void)
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{
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platform_device_register(&loki_uart1);
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}
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/*****************************************************************************
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* Time handling
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****************************************************************************/
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static void loki_timer_init(void)
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{
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orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
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}
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struct sys_timer loki_timer = {
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.init = loki_timer_init,
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};
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/*****************************************************************************
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* General
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****************************************************************************/
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void __init loki_init(void)
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{
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printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
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loki_setup_cpu_mbus();
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}
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