83 lines
3.0 KiB
C
83 lines
3.0 KiB
C
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/*
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* arch/ppc/platforms/hdpu.h
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*
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* Definitions for Sky Computers HDPU board.
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*
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* Brian Waite <waite@skycomputers.com>
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*
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* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
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* Based on code done by Mark A. Greer <mgreer@mvista.com>
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* Based on code done by Tim Montgomery <timm@artesyncp.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
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* PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
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* We'll only use one PCI MEM window on each PCI bus.
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*
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* This is the CPU physical memory map (windows must be at least 64K and start
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* on a boundary that is a multiple of the window size):
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*
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* 0x80000000-0x8fffffff - PCI 0 MEM
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* 0xa0000000-0xafffffff - PCI 1 MEM
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* 0xc0000000-0xc0ffffff - PCI 0 I/O
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* 0xc1000000-0xc1ffffff - PCI 1 I/O
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* 0xf1000000-0xf100ffff - MV64360 Registers
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* 0xf1010000-0xfb9fffff - HOLE
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* 0xfbfa0000-0xfbfaffff - TBEN
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* 0xfbf00000-0xfbfbffff - NEXUS
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* 0xfbfc0000-0xfbffffff - Internal SRAM
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* 0xfc000000-0xffffffff - Boot window
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*/
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#ifndef __PPC_PLATFORMS_HDPU_H
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#define __PPC_PLATFORMS_HDPU_H
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/* CPU Physical Memory Map setup. */
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#define HDPU_BRIDGE_REG_BASE 0xf1000000
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#define HDPU_TBEN_BASE 0xfbfa0000
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#define HDPU_TBEN_SIZE 0x00010000
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#define HDPU_NEXUS_ID_BASE 0xfbfb0000
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#define HDPU_NEXUS_ID_SIZE 0x00010000
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#define HDPU_INTERNAL_SRAM_BASE 0xfbfc0000
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#define HDPU_INTERNAL_SRAM_SIZE 0x00040000
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#define HDPU_EMB_FLASH_BASE 0xfc000000
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#define HDPU_EMB_FLASH_SIZE 0x04000000
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/* PCI Mappings */
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#define HDPU_PCI0_MEM_START_PROC_ADDR 0x80000000
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#define HDPU_PCI0_MEM_START_PCI_HI_ADDR 0x00000000
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#define HDPU_PCI0_MEM_START_PCI_LO_ADDR HDPU_PCI0_MEM_START_PROC_ADDR
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#define HDPU_PCI0_MEM_SIZE 0x10000000
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#define HDPU_PCI1_MEM_START_PROC_ADDR 0xc0000000
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#define HDPU_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
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#define HDPU_PCI1_MEM_START_PCI_LO_ADDR HDPU_PCI1_MEM_START_PROC_ADDR
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#define HDPU_PCI1_MEM_SIZE 0x20000000
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#define HDPU_PCI0_IO_START_PROC_ADDR 0xc0000000
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#define HDPU_PCI0_IO_START_PCI_ADDR 0x00000000
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#define HDPU_PCI0_IO_SIZE 0x01000000
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#define HDPU_PCI1_IO_START_PROC_ADDR 0xc1000000
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#define HDPU_PCI1_IO_START_PCI_ADDR 0x01000000
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#define HDPU_PCI1_IO_SIZE 0x01000000
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#define HDPU_DEFAULT_BAUD 115200
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#define HDPU_MPSC_CLK_SRC 8 /* TCLK */
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#define HDPU_MPSC_CLK_FREQ 133000000 /* 133 Mhz */
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#define HDPU_PCI_0_IRQ (8+64)
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#define HDPU_PCI_1_IRQ (13+64)
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#endif /* __PPC_PLATFORMS_HDPU_H */
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