84 lines
2.5 KiB
ArmAsm
84 lines
2.5 KiB
ArmAsm
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/* $Id: itlb_base.S,v 1.12 2002/02/09 19:49:30 davem Exp $
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* itlb_base.S: Front end to ITLB miss replacement strategy.
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* This is included directly into the trap table.
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*
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* Copyright (C) 1996,1998 David S. Miller (davem@redhat.com)
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#if PAGE_SHIFT == 13
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/*
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* To compute vpte offset, we need to do ((addr >> 13) << 3),
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* which can be optimized to (addr >> 10) if bits 10/11/12 can
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* be guaranteed to be 0 ... mmu_context.h does guarantee this
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* by only using 10 bits in the hwcontext value.
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*/
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#define CREATE_VPTE_OFFSET1(r1, r2) \
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srax r1, 10, r2
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#define CREATE_VPTE_OFFSET2(r1, r2)
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#define CREATE_VPTE_NOP nop
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#else /* PAGE_SHIFT */
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#define CREATE_VPTE_OFFSET1(r1, r2) \
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srax r1, PAGE_SHIFT, r2
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#define CREATE_VPTE_OFFSET2(r1, r2) \
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sllx r2, 3, r2
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#define CREATE_VPTE_NOP
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#endif /* PAGE_SHIFT */
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/* Ways we can get here:
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*
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* 1) Nucleus instruction misses from module code.
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* 2) All user instruction misses.
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*
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* All real page faults merge their code paths to the
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* sparc64_realfault_common label below.
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*/
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/* ITLB ** ICACHE line 1: Quick user TLB misses */
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ldxa [%g1 + %g1] ASI_IMMU, %g4 ! Get TAG_ACCESS
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CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset
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CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset
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ldxa [%g3 + %g6] ASI_P, %g5 ! Load VPTE
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1: brgez,pn %g5, 3f ! Not valid, branch out
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sethi %hi(_PAGE_EXEC), %g4 ! Delay-slot
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andcc %g5, %g4, %g0 ! Executable?
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be,pn %xcc, 3f ! Nope, branch.
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nop ! Delay-slot
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2: stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load PTE into TLB
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retry ! Trap return
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3: rdpr %pstate, %g4 ! Move into alternate globals
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/* ITLB ** ICACHE line 2: Real faults */
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wrpr %g4, PSTATE_AG|PSTATE_MG, %pstate
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rdpr %tpc, %g5 ! And load faulting VA
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mov FAULT_CODE_ITLB, %g4 ! It was read from ITLB
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sparc64_realfault_common: ! Called by TL0 dtlb_miss too
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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ba,pt %xcc, etrap ! Save state
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1: rd %pc, %g7 ! ...
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nop
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/* ITLB ** ICACHE line 3: Finish faults + window fixups */
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call do_sparc64_fault ! Call fault handler
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add %sp, PTREGS_OFF, %o0! Compute pt_regs arg
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ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
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nop
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winfix_trampoline:
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rdpr %tpc, %g3 ! Prepare winfixup TNPC
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or %g3, 0x7c, %g3 ! Compute offset to branch
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wrpr %g3, %tnpc ! Write it into TNPC
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done ! Do it to it
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/* ITLB ** ICACHE line 4: Unused... */
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nop
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nop
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nop
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nop
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CREATE_VPTE_NOP
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#undef CREATE_VPTE_OFFSET1
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#undef CREATE_VPTE_OFFSET2
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#undef CREATE_VPTE_NOP
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