463 lines
13 KiB
C
463 lines
13 KiB
C
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/*
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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* The Inventra Controller Driver for Linux is distributed in
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* the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with The Inventra Controller Driver for Linux ; if not,
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* write to the Free Software Foundation, Inc., 59 Temple Place,
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* Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/memory.h>
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#include <asm/arch/gpio.h>
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#include <asm/mach-types.h>
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#include "musb_core.h"
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#ifdef CONFIG_MACH_DAVINCI_EVM
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#include <asm/arch/i2c-client.h>
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#endif
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#include "davinci.h"
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#include "cppi_dma.h"
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/* REVISIT (PM) we should be able to keep the PHY in low power mode most
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* of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
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* and, when in host mode, autosuspending idle root ports... PHYPLLON
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* (overriding SUSPENDM?) then likely needs to stay off.
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*/
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static inline void phy_on(void)
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{
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/* start the on-chip PHY and its PLL */
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__raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
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(void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
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while ((__raw_readl((void __force __iomem *)
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IO_ADDRESS(USBPHY_CTL_PADDR))
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& USBPHY_PHYCLKGD) == 0)
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cpu_relax();
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}
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static inline void phy_off(void)
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{
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/* powerdown the on-chip PHY and its oscillator */
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__raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
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IO_ADDRESS(USBPHY_CTL_PADDR));
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}
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static int dma_off = 1;
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void musb_platform_enable(struct musb *musb)
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{
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u32 tmp, old, val;
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/* workaround: setup irqs through both register sets */
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tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
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<< DAVINCI_USB_TXINT_SHIFT;
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
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old = tmp;
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tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
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<< DAVINCI_USB_RXINT_SHIFT;
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
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tmp |= old;
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val = ~MUSB_INTR_SOF;
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tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
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if (is_dma_capable() && !dma_off)
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printk(KERN_WARNING "%s %s: dma not reactivated\n",
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__FILE__, __func__);
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else
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dma_off = 0;
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/* force a DRVVBUS irq so we can start polling for ID change */
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if (is_otg_enabled(musb))
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
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DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
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}
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/*
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* Disable the HDRC and flush interrupts
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*/
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void musb_platform_disable(struct musb *musb)
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{
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/* because we don't set CTRLR.UINT, "important" to:
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* - not read/write INTRUSB/INTRUSBE
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* - (except during initial setup, as workaround)
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* - use INTSETR/INTCLRR instead
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*/
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
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DAVINCI_USB_USBINT_MASK
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| DAVINCI_USB_TXINT_MASK
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| DAVINCI_USB_RXINT_MASK);
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musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
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musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
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if (is_dma_capable() && !dma_off)
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WARNING("dma still active\n");
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}
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/* REVISIT it's not clear whether DaVinci can support full OTG. */
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static int vbus_state = -1;
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#ifdef CONFIG_USB_MUSB_HDRC_HCD
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#define portstate(stmt) stmt
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#else
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#define portstate(stmt)
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#endif
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/* VBUS SWITCHING IS BOARD-SPECIFIC */
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#ifdef CONFIG_MACH_DAVINCI_EVM
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#ifndef CONFIG_MACH_DAVINCI_EVM_OTG
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/* I2C operations are always synchronous, and require a task context.
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* With unloaded systems, using the shared workqueue seems to suffice
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* to satisfy the 100msec A_WAIT_VRISE timeout...
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*/
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static void evm_deferred_drvvbus(struct work_struct *ignored)
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{
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davinci_i2c_expander_op(0x3a, USB_DRVVBUS, vbus_state);
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vbus_state = !vbus_state;
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}
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static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
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#endif /* modified board */
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#endif /* EVM */
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static void davinci_source_power(struct musb *musb, int is_on, int immediate)
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{
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if (is_on)
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is_on = 1;
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if (vbus_state == is_on)
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return;
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vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
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#ifdef CONFIG_MACH_DAVINCI_EVM
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if (machine_is_davinci_evm()) {
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#ifdef CONFIG_MACH_DAVINCI_EVM_OTG
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/* modified EVM board switching VBUS with GPIO(6) not I2C
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* NOTE: PINMUX0.RGB888 (bit23) must be clear
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*/
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if (is_on)
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gpio_set(GPIO(6));
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else
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gpio_clear(GPIO(6));
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immediate = 1;
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#else
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if (immediate)
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davinci_i2c_expander_op(0x3a, USB_DRVVBUS, !is_on);
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else
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schedule_work(&evm_vbus_work);
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#endif
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}
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#endif
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if (immediate)
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vbus_state = is_on;
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}
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static void davinci_set_vbus(struct musb *musb, int is_on)
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{
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WARN_ON(is_on && is_peripheral_active(musb));
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davinci_source_power(musb, is_on, 0);
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}
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#define POLL_SECONDS 2
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static struct timer_list otg_workaround;
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static void otg_timer(unsigned long _musb)
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{
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struct musb *musb = (void *)_musb;
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void __iomem *mregs = musb->mregs;
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u8 devctl;
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unsigned long flags;
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/* We poll because DaVinci's won't expose several OTG-critical
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* status change events (from the transceiver) otherwise.
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*/
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
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spin_lock_irqsave(&musb->lock, flags);
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switch (musb->xceiv.state) {
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case OTG_STATE_A_WAIT_VFALL:
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/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
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* seems to mis-handle session "start" otherwise (or in our
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* case "recover"), in routine "VBUS was valid by the time
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* VBUSERR got reported during enumeration" cases.
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*/
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if (devctl & MUSB_DEVCTL_VBUS) {
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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break;
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}
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musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
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musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
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MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
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break;
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case OTG_STATE_B_IDLE:
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if (!is_peripheral_enabled(musb))
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break;
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/* There's no ID-changed IRQ, so we have no good way to tell
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* when to switch to the A-Default state machine (by setting
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* the DEVCTL.SESSION flag).
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*
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* Workaround: whenever we're in B_IDLE, try setting the
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* session flag every few seconds. If it works, ID was
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* grounded and we're now in the A-Default state machine.
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*
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* NOTE setting the session flag is _supposed_ to trigger
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* SRP, but clearly it doesn't.
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*/
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musb_writeb(mregs, MUSB_DEVCTL,
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devctl | MUSB_DEVCTL_SESSION);
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devctl = musb_readb(mregs, MUSB_DEVCTL);
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if (devctl & MUSB_DEVCTL_BDEVICE)
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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else
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musb->xceiv.state = OTG_STATE_A_IDLE;
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break;
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default:
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break;
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static irqreturn_t davinci_interrupt(int irq, void *__hci)
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{
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unsigned long flags;
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irqreturn_t retval = IRQ_NONE;
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struct musb *musb = __hci;
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void __iomem *tibase = musb->ctrl_base;
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u32 tmp;
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spin_lock_irqsave(&musb->lock, flags);
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/* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
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* the Mentor registers (except for setup), use the TI ones and EOI.
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*
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* Docs describe irq "vector" registers asociated with the CPPI and
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* USB EOI registers. These hold a bitmask corresponding to the
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* current IRQ, not an irq handler address. Would using those bits
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* resolve some of the races observed in this dispatch code??
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*/
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/* CPPI interrupts share the same IRQ line, but have their own
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* mask, state, "vector", and EOI registers.
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*/
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if (is_cppi_enabled()) {
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u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
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u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
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if (cppi_tx || cppi_rx) {
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DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
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cppi_completion(musb, cppi_rx, cppi_tx);
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retval = IRQ_HANDLED;
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}
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}
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/* ack and handle non-CPPI interrupts */
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tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
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musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
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DBG(4, "IRQ %08x\n", tmp);
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musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
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>> DAVINCI_USB_RXINT_SHIFT;
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musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
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>> DAVINCI_USB_TXINT_SHIFT;
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musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
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>> DAVINCI_USB_USBINT_SHIFT;
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/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
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* DaVinci's missing ID change IRQ. We need an ID change IRQ to
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* switch appropriately between halves of the OTG state machine.
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* Managing DEVCTL.SESSION per Mentor docs requires we know its
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* value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
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* Also, DRVVBUS pulses for SRP (but not at 5V) ...
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*/
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if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
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int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
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void __iomem *mregs = musb->mregs;
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u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
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int err = musb->int_usb & MUSB_INTR_VBUSERROR;
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err = is_host_enabled(musb)
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&& (musb->int_usb & MUSB_INTR_VBUSERROR);
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if (err) {
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/* The Mentor core doesn't debounce VBUS as needed
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* to cope with device connect current spikes. This
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* means it's not uncommon for bus-powered devices
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* to get VBUS errors during enumeration.
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*
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* This is a workaround, but newer RTL from Mentor
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* seems to allow a better one: "re"starting sessions
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* without waiting (on EVM, a **long** time) for VBUS
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* to stop registering in devctl.
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*/
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musb->int_usb &= ~MUSB_INTR_VBUSERROR;
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musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
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mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
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WARNING("VBUS error workaround (delay coming)\n");
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} else if (is_host_enabled(musb) && drvvbus) {
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musb->is_active = 1;
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MUSB_HST_MODE(musb);
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musb->xceiv.default_a = 1;
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musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
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portstate(musb->port1_status |= USB_PORT_STAT_POWER);
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del_timer(&otg_workaround);
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} else {
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musb->is_active = 0;
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MUSB_DEV_MODE(musb);
|
||
|
|
musb->xceiv.default_a = 0;
|
||
|
|
musb->xceiv.state = OTG_STATE_B_IDLE;
|
||
|
|
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* NOTE: this must complete poweron within 100 msec */
|
||
|
|
davinci_source_power(musb, drvvbus, 0);
|
||
|
|
DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
|
||
|
|
drvvbus ? "on" : "off",
|
||
|
|
otg_state_string(musb),
|
||
|
|
err ? " ERROR" : "",
|
||
|
|
devctl);
|
||
|
|
retval = IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (musb->int_tx || musb->int_rx || musb->int_usb)
|
||
|
|
retval |= musb_interrupt(musb);
|
||
|
|
|
||
|
|
/* irq stays asserted until EOI is written */
|
||
|
|
musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
|
||
|
|
|
||
|
|
/* poll for ID change */
|
||
|
|
if (is_otg_enabled(musb)
|
||
|
|
&& musb->xceiv.state == OTG_STATE_B_IDLE)
|
||
|
|
mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
|
||
|
|
|
||
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
||
|
|
|
||
|
|
/* REVISIT we sometimes get unhandled IRQs
|
||
|
|
* (e.g. ep0). not clear why...
|
||
|
|
*/
|
||
|
|
if (retval != IRQ_HANDLED)
|
||
|
|
DBG(5, "unhandled? %08x\n", tmp);
|
||
|
|
return IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
int __init musb_platform_init(struct musb *musb)
|
||
|
|
{
|
||
|
|
void __iomem *tibase = musb->ctrl_base;
|
||
|
|
u32 revision;
|
||
|
|
|
||
|
|
musb->mregs += DAVINCI_BASE_OFFSET;
|
||
|
|
#if 0
|
||
|
|
/* REVISIT there's something odd about clocking, this
|
||
|
|
* didn't appear do the job ...
|
||
|
|
*/
|
||
|
|
musb->clock = clk_get(pDevice, "usb");
|
||
|
|
if (IS_ERR(musb->clock))
|
||
|
|
return PTR_ERR(musb->clock);
|
||
|
|
|
||
|
|
status = clk_enable(musb->clock);
|
||
|
|
if (status < 0)
|
||
|
|
return -ENODEV;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* returns zero if e.g. not clocked */
|
||
|
|
revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
|
||
|
|
if (revision == 0)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
if (is_host_enabled(musb))
|
||
|
|
setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
|
||
|
|
|
||
|
|
musb->board_set_vbus = davinci_set_vbus;
|
||
|
|
davinci_source_power(musb, 0, 1);
|
||
|
|
|
||
|
|
/* reset the controller */
|
||
|
|
musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
|
||
|
|
|
||
|
|
/* start the on-chip PHY and its PLL */
|
||
|
|
phy_on();
|
||
|
|
|
||
|
|
msleep(5);
|
||
|
|
|
||
|
|
/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
|
||
|
|
pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
|
||
|
|
revision, __raw_readl((void __force __iomem *)
|
||
|
|
IO_ADDRESS(USBPHY_CTL_PADDR)),
|
||
|
|
musb_readb(tibase, DAVINCI_USB_CTRL_REG));
|
||
|
|
|
||
|
|
musb->isr = davinci_interrupt;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int musb_platform_exit(struct musb *musb)
|
||
|
|
{
|
||
|
|
if (is_host_enabled(musb))
|
||
|
|
del_timer_sync(&otg_workaround);
|
||
|
|
|
||
|
|
davinci_source_power(musb, 0 /*off*/, 1);
|
||
|
|
|
||
|
|
/* delay, to avoid problems with module reload */
|
||
|
|
if (is_host_enabled(musb) && musb->xceiv.default_a) {
|
||
|
|
int maxdelay = 30;
|
||
|
|
u8 devctl, warn = 0;
|
||
|
|
|
||
|
|
/* if there's no peripheral connected, this can take a
|
||
|
|
* long time to fall, especially on EVM with huge C133.
|
||
|
|
*/
|
||
|
|
do {
|
||
|
|
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
|
||
|
|
if (!(devctl & MUSB_DEVCTL_VBUS))
|
||
|
|
break;
|
||
|
|
if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
|
||
|
|
warn = devctl & MUSB_DEVCTL_VBUS;
|
||
|
|
DBG(1, "VBUS %d\n",
|
||
|
|
warn >> MUSB_DEVCTL_VBUS_SHIFT);
|
||
|
|
}
|
||
|
|
msleep(1000);
|
||
|
|
maxdelay--;
|
||
|
|
} while (maxdelay > 0);
|
||
|
|
|
||
|
|
/* in OTG mode, another host might be connected */
|
||
|
|
if (devctl & MUSB_DEVCTL_VBUS)
|
||
|
|
DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
|
||
|
|
}
|
||
|
|
|
||
|
|
phy_off();
|
||
|
|
return 0;
|
||
|
|
}
|