2008-01-28 11:42:17 -05:00
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/*
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2005-07-27 14:44:44 -04:00
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* DMA C definitions and help macros
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*
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*/
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#ifndef dma_h
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#define dma_h
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/* registers */ /* Really needed, since both are listed in sw.list? */
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#include "dma_defs.h"
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/* descriptors */
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// ------------------------------------------------------------ dma_descr_group
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typedef struct dma_descr_group {
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struct dma_descr_group *next;
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unsigned eol : 1;
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unsigned tol : 1;
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unsigned bol : 1;
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unsigned : 1;
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unsigned intr : 1;
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unsigned : 2;
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unsigned en : 1;
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unsigned : 7;
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unsigned dis : 1;
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unsigned md : 16;
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struct dma_descr_group *up;
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union {
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struct dma_descr_context *context;
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struct dma_descr_group *group;
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} down;
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} dma_descr_group;
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// ---------------------------------------------------------- dma_descr_context
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typedef struct dma_descr_context {
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struct dma_descr_context *next;
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unsigned eol : 1;
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unsigned : 3;
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unsigned intr : 1;
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unsigned : 1;
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unsigned store_mode : 1;
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unsigned en : 1;
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unsigned : 7;
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unsigned dis : 1;
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unsigned md0 : 16;
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unsigned md1;
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unsigned md2;
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unsigned md3;
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unsigned md4;
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struct dma_descr_data *saved_data;
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char *saved_data_buf;
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} dma_descr_context;
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// ------------------------------------------------------------- dma_descr_data
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typedef struct dma_descr_data {
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struct dma_descr_data *next;
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char *buf;
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unsigned eol : 1;
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unsigned : 2;
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unsigned out_eop : 1;
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unsigned intr : 1;
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unsigned wait : 1;
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unsigned : 2;
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unsigned : 3;
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unsigned in_eop : 1;
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unsigned : 4;
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unsigned md : 16;
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char *after;
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} dma_descr_data;
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// --------------------------------------------------------------------- macros
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// enable DMA channel
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#define DMA_ENABLE( inst ) \
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do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
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e.en = regk_dma_yes; \
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REG_WR( dma, inst, rw_cfg, e); } while( 0 )
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// reset DMA channel
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#define DMA_RESET( inst ) \
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do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
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r.en = regk_dma_no; \
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REG_WR( dma, inst, rw_cfg, r); } while( 0 )
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// stop DMA channel
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#define DMA_STOP( inst ) \
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do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
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s.stop = regk_dma_yes; \
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REG_WR( dma, inst, rw_cfg, s); } while( 0 )
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// continue DMA channel operation
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#define DMA_CONTINUE( inst ) \
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do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
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c.stop = regk_dma_no; \
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REG_WR( dma, inst, rw_cfg, c); } while( 0 )
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// give stream command
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#define DMA_WR_CMD( inst, cmd_par ) \
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2008-01-28 11:42:17 -05:00
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do { reg_dma_rw_stream_cmd __x = {0}; \
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do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
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__x.cmd = (cmd_par); \
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REG_WR(dma, inst, rw_stream_cmd, __x); \
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} while (0)
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2005-07-27 14:44:44 -04:00
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// load: g,c,d:burst
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#define DMA_START_GROUP( inst, group_descr ) \
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do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
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DMA_WR_CMD( inst, regk_dma_load_g ); \
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DMA_WR_CMD( inst, regk_dma_load_c ); \
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DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
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} while( 0 )
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// load: c,d:burst
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#define DMA_START_CONTEXT( inst, ctx_descr ) \
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do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
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DMA_WR_CMD( inst, regk_dma_load_c ); \
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DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
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} while( 0 )
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// if the DMA is at the end of the data list, the last data descr is reloaded
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#define DMA_CONTINUE_DATA( inst ) \
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do { reg_dma_rw_cmd c = {0}; \
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c.cont_data = regk_dma_yes;\
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REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
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#endif
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