2005-04-16 18:20:36 -04:00
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/* -------------------------------------------------------------------- */
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2006-09-27 04:17:27 -04:00
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/* voyagergx.h */
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2005-04-16 18:20:36 -04:00
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/* -------------------------------------------------------------------- */
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/* This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Copyright 2003 (c) Lineo uSolutions,Inc.
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*/
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/* -------------------------------------------------------------------- */
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#ifndef _VOYAGER_GX_REG_H
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#define _VOYAGER_GX_REG_H
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#define VOYAGER_BASE 0xb3e00000
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#define VOYAGER_USBH_BASE (0x40000 + VOYAGER_BASE)
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#define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE)
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#define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE)
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#define VOYAGER_IRQ_NUM 32
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#define VOYAGER_IRQ_BASE 50
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#define VOYAGER_USBH_IRQ VOYAGER_IRQ_BASE + 6
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#define VOYAGER_8051_IRQ VOYAGER_IRQ_BASE + 10
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#define VOYAGER_UART0_IRQ VOYAGER_IRQ_BASE + 12
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#define VOYAGER_UART1_IRQ VOYAGER_IRQ_BASE + 13
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#define VOYAGER_AC97_IRQ VOYAGER_IRQ_BASE + 17
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/* ----- MISC controle register ------------------------------ */
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#define MISC_CTRL (0x000004 + VOYAGER_BASE)
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#define MISC_CTRL_USBCLK_48 (3 << 28)
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#define MISC_CTRL_USBCLK_96 (2 << 28)
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#define MISC_CTRL_USBCLK_CRYSTAL (1 << 28)
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/* ----- GPIO[31:0] register --------------------------------- */
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#define GPIO_MUX_LOW (0x000008 + VOYAGER_BASE)
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#define GPIO_MUX_LOW_AC97 0x1F000000
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#define GPIO_MUX_LOW_8051 0x0000ffff
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#define GPIO_MUX_LOW_PWM (1 << 29)
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/* ----- GPIO[63:32] register --------------------------------- */
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#define GPIO_MUX_HIGH (0x00000C + VOYAGER_BASE)
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/* ----- DRAM controle register ------------------------------- */
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#define DRAM_CTRL (0x000010 + VOYAGER_BASE)
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#define DRAM_CTRL_EMBEDDED (1 << 31)
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#define DRAM_CTRL_CPU_BURST_1 (0 << 28)
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#define DRAM_CTRL_CPU_BURST_2 (1 << 28)
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#define DRAM_CTRL_CPU_BURST_4 (2 << 28)
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#define DRAM_CTRL_CPU_BURST_8 (3 << 28)
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#define DRAM_CTRL_CPU_CAS_LATENCY (1 << 27)
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#define DRAM_CTRL_CPU_SIZE_2 (0 << 24)
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#define DRAM_CTRL_CPU_SIZE_4 (1 << 24)
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#define DRAM_CTRL_CPU_SIZE_64 (4 << 24)
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#define DRAM_CTRL_CPU_SIZE_32 (5 << 24)
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#define DRAM_CTRL_CPU_SIZE_16 (6 << 24)
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#define DRAM_CTRL_CPU_SIZE_8 (7 << 24)
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#define DRAM_CTRL_CPU_COLUMN_SIZE_1024 (0 << 22)
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#define DRAM_CTRL_CPU_COLUMN_SIZE_512 (2 << 22)
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#define DRAM_CTRL_CPU_COLUMN_SIZE_256 (3 << 22)
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#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE (1 << 21)
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#define DRAM_CTRL_CPU_RESET (1 << 20)
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#define DRAM_CTRL_CPU_BANKS (1 << 19)
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#define DRAM_CTRL_CPU_WRITE_PRECHARGE (1 << 18)
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#define DRAM_CTRL_BLOCK_WRITE (1 << 17)
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#define DRAM_CTRL_REFRESH_COMMAND (1 << 16)
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#define DRAM_CTRL_SIZE_4 (0 << 13)
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#define DRAM_CTRL_SIZE_8 (1 << 13)
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#define DRAM_CTRL_SIZE_16 (2 << 13)
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#define DRAM_CTRL_SIZE_32 (3 << 13)
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#define DRAM_CTRL_SIZE_64 (4 << 13)
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#define DRAM_CTRL_SIZE_2 (5 << 13)
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#define DRAM_CTRL_COLUMN_SIZE_256 (0 << 11)
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#define DRAM_CTRL_COLUMN_SIZE_512 (2 << 11)
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#define DRAM_CTRL_COLUMN_SIZE_1024 (3 << 11)
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#define DRAM_CTRL_BLOCK_WRITE_TIME (1 << 10)
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#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE (1 << 9)
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#define DRAM_CTRL_ACTIVE_PRECHARGE (1 << 8)
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#define DRAM_CTRL_RESET (1 << 7)
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#define DRAM_CTRL_REMAIN_ACTIVE (1 << 6)
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#define DRAM_CTRL_BANKS (1 << 1)
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#define DRAM_CTRL_WRITE_PRECHARGE (1 << 0)
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/* ----- Arvitration control register -------------------------- */
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#define ARBITRATION_CTRL (0x000014 + VOYAGER_BASE)
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#define ARBITRATION_CTRL_CPUMEM (1 << 29)
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#define ARBITRATION_CTRL_INTMEM (1 << 28)
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#define ARBITRATION_CTRL_USB_OFF (0 << 24)
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#define ARBITRATION_CTRL_USB_PRIORITY_1 (1 << 24)
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#define ARBITRATION_CTRL_USB_PRIORITY_2 (2 << 24)
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#define ARBITRATION_CTRL_USB_PRIORITY_3 (3 << 24)
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#define ARBITRATION_CTRL_USB_PRIORITY_4 (4 << 24)
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#define ARBITRATION_CTRL_USB_PRIORITY_5 (5 << 24)
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#define ARBITRATION_CTRL_USB_PRIORITY_6 (6 << 24)
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#define ARBITRATION_CTRL_USB_PRIORITY_7 (7 << 24)
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#define ARBITRATION_CTRL_PANEL_OFF (0 << 20)
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#define ARBITRATION_CTRL_PANEL_PRIORITY_1 (1 << 20)
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#define ARBITRATION_CTRL_PANEL_PRIORITY_2 (2 << 20)
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#define ARBITRATION_CTRL_PANEL_PRIORITY_3 (3 << 20)
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#define ARBITRATION_CTRL_PANEL_PRIORITY_4 (4 << 20)
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#define ARBITRATION_CTRL_PANEL_PRIORITY_5 (5 << 20)
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#define ARBITRATION_CTRL_PANEL_PRIORITY_6 (6 << 20)
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#define ARBITRATION_CTRL_PANEL_PRIORITY_7 (7 << 20)
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#define ARBITRATION_CTRL_ZVPORT_OFF (0 << 16)
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#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_1 (1 << 16)
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#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_2 (2 << 16)
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#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_3 (3 << 16)
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#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_4 (4 << 16)
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#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_5 (5 << 16)
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#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_6 (6 << 16)
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#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_7 (7 << 16)
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#define ARBITRATION_CTRL_CMD_INTPR_OFF (0 << 12)
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#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 (1 << 12)
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#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_2 (2 << 12)
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#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_3 (3 << 12)
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#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_4 (4 << 12)
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#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_5 (5 << 12)
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#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_6 (6 << 12)
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#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_7 (7 << 12)
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#define ARBITRATION_CTRL_DMA_OFF (0 << 8)
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#define ARBITRATION_CTRL_DMA_PRIORITY_1 (1 << 8)
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#define ARBITRATION_CTRL_DMA_PRIORITY_2 (2 << 8)
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#define ARBITRATION_CTRL_DMA_PRIORITY_3 (3 << 8)
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#define ARBITRATION_CTRL_DMA_PRIORITY_4 (4 << 8)
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#define ARBITRATION_CTRL_DMA_PRIORITY_5 (5 << 8)
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#define ARBITRATION_CTRL_DMA_PRIORITY_6 (6 << 8)
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#define ARBITRATION_CTRL_DMA_PRIORITY_7 (7 << 8)
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#define ARBITRATION_CTRL_VIDEO_OFF (0 << 4)
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#define ARBITRATION_CTRL_VIDEO_PRIORITY_1 (1 << 4)
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#define ARBITRATION_CTRL_VIDEO_PRIORITY_2 (2 << 4)
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#define ARBITRATION_CTRL_VIDEO_PRIORITY_3 (3 << 4)
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#define ARBITRATION_CTRL_VIDEO_PRIORITY_4 (4 << 4)
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#define ARBITRATION_CTRL_VIDEO_PRIORITY_5 (5 << 4)
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#define ARBITRATION_CTRL_VIDEO_PRIORITY_6 (6 << 4)
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#define ARBITRATION_CTRL_VIDEO_PRIORITY_7 (7 << 4)
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#define ARBITRATION_CTRL_CRT_OFF (0 << 0)
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#define ARBITRATION_CTRL_CRT_PRIORITY_1 (1 << 0)
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#define ARBITRATION_CTRL_CRT_PRIORITY_2 (2 << 0)
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#define ARBITRATION_CTRL_CRT_PRIORITY_3 (3 << 0)
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#define ARBITRATION_CTRL_CRT_PRIORITY_4 (4 << 0)
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#define ARBITRATION_CTRL_CRT_PRIORITY_5 (5 << 0)
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#define ARBITRATION_CTRL_CRT_PRIORITY_6 (6 << 0)
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#define ARBITRATION_CTRL_CRT_PRIORITY_7 (7 << 0)
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/* ----- Command list status register -------------------------- */
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#define CMD_INTPR_STATUS (0x000024 + VOYAGER_BASE)
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/* ----- Interrupt status register ----------------------------- */
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#define INT_STATUS (0x00002c + VOYAGER_BASE)
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#define INT_STATUS_UH (1 << 6)
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#define INT_STATUS_MC (1 << 10)
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#define INT_STATUS_U0 (1 << 12)
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#define INT_STATUS_U1 (1 << 13)
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#define INT_STATUS_AC (1 << 17)
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/* ----- Interrupt mask register ------------------------------ */
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#define VOYAGER_INT_MASK (0x000030 + VOYAGER_BASE)
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#define VOYAGER_INT_MASK_AC (1 << 17)
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/* ----- Current Gate register ---------------------------------*/
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#define CURRENT_GATE (0x000038 + VOYAGER_BASE)
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/* ----- Power mode 0 gate register --------------------------- */
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#define POWER_MODE0_GATE (0x000040 + VOYAGER_BASE)
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#define POWER_MODE0_GATE_G (1 << 6)
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#define POWER_MODE0_GATE_U0 (1 << 7)
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#define POWER_MODE0_GATE_U1 (1 << 8)
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#define POWER_MODE0_GATE_UH (1 << 11)
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#define POWER_MODE0_GATE_AC (1 << 18)
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/* ----- Power mode 1 gate register --------------------------- */
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#define POWER_MODE1_GATE (0x000048 + VOYAGER_BASE)
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#define POWER_MODE1_GATE_G (1 << 6)
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#define POWER_MODE1_GATE_U0 (1 << 7)
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#define POWER_MODE1_GATE_U1 (1 << 8)
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#define POWER_MODE1_GATE_UH (1 << 11)
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#define POWER_MODE1_GATE_AC (1 << 18)
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/* ----- Power mode 0 clock register -------------------------- */
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#define POWER_MODE0_CLOCK (0x000044 + VOYAGER_BASE)
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/* ----- Power mode 1 clock register -------------------------- */
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#define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE)
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/* ----- Power mode controll register ------------------------- */
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#define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE)
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/* ----- Miscellaneous Timing register ------------------------ */
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#define SYSTEM_DRAM_CTRL (0x000068 + VOYAGER_BASE)
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/* ----- PWM register ------------------------------------------*/
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#define PWM_0 (0x010020 + VOYAGER_BASE)
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#define PWM_0_HC(x) (((x)&0x0fff)<<20)
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#define PWM_0_LC(x) (((x)&0x0fff)<<8 )
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#define PWM_0_CLK_DEV(x) (((x)&0x000f)<<4 )
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#define PWM_0_EN (1<<0)
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/* ----- I2C register ----------------------------------------- */
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#define I2C_BYTECOUNT (0x010040 + VOYAGER_BASE)
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#define I2C_CONTROL (0x010041 + VOYAGER_BASE)
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#define I2C_STATUS (0x010042 + VOYAGER_BASE)
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#define I2C_RESET (0x010042 + VOYAGER_BASE)
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#define I2C_SADDRESS (0x010043 + VOYAGER_BASE)
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#define I2C_DATA (0x010044 + VOYAGER_BASE)
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/* ----- Controle register bits ----------------------------------------- */
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#define I2C_CONTROL_E (1 << 0)
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#define I2C_CONTROL_MODE (1 << 1)
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#define I2C_CONTROL_STATUS (1 << 2)
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#define I2C_CONTROL_INT (1 << 4)
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#define I2C_CONTROL_INTACK (1 << 5)
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#define I2C_CONTROL_REPEAT (1 << 6)
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/* ----- Status register bits ----------------------------------------- */
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#define I2C_STATUS_BUSY (1 << 0)
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#define I2C_STATUS_ACK (1 << 1)
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#define I2C_STATUS_ERROR (1 << 2)
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#define I2C_STATUS_COMPLETE (1 << 3)
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/* ----- Reset register ---------------------------------------------- */
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#define I2C_RESET_ERROR (1 << 2)
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/* ----- transmission frequencies ------------------------------------- */
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#define I2C_SADDRESS_SELECT (1 << 0)
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/* ----- Display Controll register ----------------------------------------- */
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#define PANEL_DISPLAY_CTRL (0x080000 + VOYAGER_BASE)
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#define PANEL_DISPLAY_CTRL_BIAS (1<<26)
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#define PANEL_PAN_CTRL (0x080004 + VOYAGER_BASE)
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#define PANEL_COLOR_KEY (0x080008 + VOYAGER_BASE)
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#define PANEL_FB_ADDRESS (0x08000C + VOYAGER_BASE)
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#define PANEL_FB_WIDTH (0x080010 + VOYAGER_BASE)
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#define PANEL_WINDOW_WIDTH (0x080014 + VOYAGER_BASE)
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#define PANEL_WINDOW_HEIGHT (0x080018 + VOYAGER_BASE)
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#define PANEL_PLANE_TL (0x08001C + VOYAGER_BASE)
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#define PANEL_PLANE_BR (0x080020 + VOYAGER_BASE)
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#define PANEL_HORIZONTAL_TOTAL (0x080024 + VOYAGER_BASE)
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#define PANEL_HORIZONTAL_SYNC (0x080028 + VOYAGER_BASE)
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#define PANEL_VERTICAL_TOTAL (0x08002C + VOYAGER_BASE)
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#define PANEL_VERTICAL_SYNC (0x080030 + VOYAGER_BASE)
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#define PANEL_CURRENT_LINE (0x080034 + VOYAGER_BASE)
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#define VIDEO_DISPLAY_CTRL (0x080040 + VOYAGER_BASE)
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#define VIDEO_FB_0_ADDRESS (0x080044 + VOYAGER_BASE)
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#define VIDEO_FB_WIDTH (0x080048 + VOYAGER_BASE)
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#define VIDEO_FB_0_LAST_ADDRESS (0x08004C + VOYAGER_BASE)
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#define VIDEO_PLANE_TL (0x080050 + VOYAGER_BASE)
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#define VIDEO_PLANE_BR (0x080054 + VOYAGER_BASE)
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#define VIDEO_SCALE (0x080058 + VOYAGER_BASE)
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#define VIDEO_INITIAL_SCALE (0x08005C + VOYAGER_BASE)
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#define VIDEO_YUV_CONSTANTS (0x080060 + VOYAGER_BASE)
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#define VIDEO_FB_1_ADDRESS (0x080064 + VOYAGER_BASE)
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#define VIDEO_FB_1_LAST_ADDRESS (0x080068 + VOYAGER_BASE)
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#define VIDEO_ALPHA_DISPLAY_CTRL (0x080080 + VOYAGER_BASE)
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#define VIDEO_ALPHA_FB_ADDRESS (0x080084 + VOYAGER_BASE)
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#define VIDEO_ALPHA_FB_WIDTH (0x080088 + VOYAGER_BASE)
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#define VIDEO_ALPHA_FB_LAST_ADDRESS (0x08008C + VOYAGER_BASE)
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#define VIDEO_ALPHA_PLANE_TL (0x080090 + VOYAGER_BASE)
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#define VIDEO_ALPHA_PLANE_BR (0x080094 + VOYAGER_BASE)
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#define VIDEO_ALPHA_SCALE (0x080098 + VOYAGER_BASE)
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#define VIDEO_ALPHA_INITIAL_SCALE (0x08009C + VOYAGER_BASE)
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#define VIDEO_ALPHA_CHROMA_KEY (0x0800A0 + VOYAGER_BASE)
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#define PANEL_HWC_ADDRESS (0x0800F0 + VOYAGER_BASE)
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#define PANEL_HWC_LOCATION (0x0800F4 + VOYAGER_BASE)
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#define PANEL_HWC_COLOR_12 (0x0800F8 + VOYAGER_BASE)
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#define PANEL_HWC_COLOR_3 (0x0800FC + VOYAGER_BASE)
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#define ALPHA_DISPLAY_CTRL (0x080100 + VOYAGER_BASE)
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#define ALPHA_FB_ADDRESS (0x080104 + VOYAGER_BASE)
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#define ALPHA_FB_WIDTH (0x080108 + VOYAGER_BASE)
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#define ALPHA_PLANE_TL (0x08010C + VOYAGER_BASE)
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#define ALPHA_PLANE_BR (0x080110 + VOYAGER_BASE)
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#define ALPHA_CHROMA_KEY (0x080114 + VOYAGER_BASE)
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#define CRT_DISPLAY_CTRL (0x080200 + VOYAGER_BASE)
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#define CRT_FB_ADDRESS (0x080204 + VOYAGER_BASE)
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#define CRT_FB_WIDTH (0x080208 + VOYAGER_BASE)
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#define CRT_HORIZONTAL_TOTAL (0x08020C + VOYAGER_BASE)
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#define CRT_HORIZONTAL_SYNC (0x080210 + VOYAGER_BASE)
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#define CRT_VERTICAL_TOTAL (0x080214 + VOYAGER_BASE)
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#define CRT_VERTICAL_SYNC (0x080218 + VOYAGER_BASE)
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#define CRT_SIGNATURE_ANALYZER (0x08021C + VOYAGER_BASE)
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#define CRT_CURRENT_LINE (0x080220 + VOYAGER_BASE)
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#define CRT_MONITOR_DETECT (0x080224 + VOYAGER_BASE)
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#define CRT_HWC_ADDRESS (0x080230 + VOYAGER_BASE)
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#define CRT_HWC_LOCATION (0x080234 + VOYAGER_BASE)
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#define CRT_HWC_COLOR_12 (0x080238 + VOYAGER_BASE)
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#define CRT_HWC_COLOR_3 (0x08023C + VOYAGER_BASE)
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#define CRT_PALETTE_RAM (0x080400 + VOYAGER_BASE)
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#define PANEL_PALETTE_RAM (0x080800 + VOYAGER_BASE)
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#define VIDEO_PALETTE_RAM (0x080C00 + VOYAGER_BASE)
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/* ----- 8051 Controle register ----------------------------------------- */
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#define VOYAGER_8051_BASE (0x000c0000 + VOYAGER_BASE)
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#define VOYAGER_8051_RESET (0x000b0000 + VOYAGER_BASE)
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#define VOYAGER_8051_SELECT (0x000b0004 + VOYAGER_BASE)
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#define VOYAGER_8051_CPU_INT (0x000b000c + VOYAGER_BASE)
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/* ----- AC97 Controle register ----------------------------------------- */
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#define AC97_TX_SLOT0 (0x00000000 + VOYAGER_AC97_BASE)
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#define AC97_CONTROL_STATUS (0x00000080 + VOYAGER_AC97_BASE)
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#define AC97C_READ (1 << 19)
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#define AC97C_WD_BIT (1 << 2)
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#define AC97C_INDEX_MASK 0x7f
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2007-02-15 04:20:52 -05:00
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/* arch/sh/cchips/voyagergx/consistent.c */
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void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t);
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int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t);
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2005-04-16 18:20:36 -04:00
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#endif /* _VOYAGER_GX_REG_H */
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