552 lines
18 KiB
C
552 lines
18 KiB
C
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/* $Id: ffb_context.c,v 1.5 2001/08/09 17:47:51 davem Exp $
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* ffb_context.c: Creator/Creator3D DRI/DRM context switching.
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*
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* Copyright (C) 2000 David S. Miller (davem@redhat.com)
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*
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* Almost entirely stolen from tdfx_context.c, see there
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* for authors.
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*/
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#include <linux/sched.h>
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#include <asm/upa.h>
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#include "ffb.h"
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#include "drmP.h"
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#include "ffb_drv.h"
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static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only)
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{
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ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
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int i;
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for (i = 0; i < FFB_MAX_CTXS; i++) {
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if (fpriv->hw_state[i] == NULL)
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break;
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}
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if (i == FFB_MAX_CTXS)
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return -1;
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fpriv->hw_state[i] = kmalloc(sizeof(struct ffb_hw_context), GFP_KERNEL);
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if (fpriv->hw_state[i] == NULL)
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return -1;
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fpriv->hw_state[i]->is_2d_only = is_2d_only;
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/* Plus one because 0 is the special DRM_KERNEL_CONTEXT. */
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return i + 1;
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}
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static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx)
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{
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ffb_fbcPtr ffb = fpriv->regs;
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struct ffb_hw_context *ctx;
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int i;
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ctx = fpriv->hw_state[idx - 1];
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if (idx == 0 || ctx == NULL)
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return;
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if (ctx->is_2d_only) {
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/* 2D applications only care about certain pieces
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* of state.
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*/
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ctx->drawop = upa_readl(&ffb->drawop);
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ctx->ppc = upa_readl(&ffb->ppc);
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ctx->wid = upa_readl(&ffb->wid);
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ctx->fg = upa_readl(&ffb->fg);
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ctx->bg = upa_readl(&ffb->bg);
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ctx->xclip = upa_readl(&ffb->xclip);
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ctx->fbc = upa_readl(&ffb->fbc);
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ctx->rop = upa_readl(&ffb->rop);
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ctx->cmp = upa_readl(&ffb->cmp);
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ctx->matchab = upa_readl(&ffb->matchab);
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ctx->magnab = upa_readl(&ffb->magnab);
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ctx->pmask = upa_readl(&ffb->pmask);
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ctx->xpmask = upa_readl(&ffb->xpmask);
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ctx->lpat = upa_readl(&ffb->lpat);
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ctx->fontxy = upa_readl(&ffb->fontxy);
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ctx->fontw = upa_readl(&ffb->fontw);
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ctx->fontinc = upa_readl(&ffb->fontinc);
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/* stencil/stencilctl only exists on FFB2+ and later
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* due to the introduction of 3DRAM-III.
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*/
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if (fpriv->ffb_type == ffb2_vertical_plus ||
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fpriv->ffb_type == ffb2_horizontal_plus) {
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ctx->stencil = upa_readl(&ffb->stencil);
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ctx->stencilctl = upa_readl(&ffb->stencilctl);
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}
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for (i = 0; i < 32; i++)
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ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
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ctx->ucsr = upa_readl(&ffb->ucsr);
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return;
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}
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/* Fetch drawop. */
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ctx->drawop = upa_readl(&ffb->drawop);
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/* If we were saving the vertex registers, this is where
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* we would do it. We would save 32 32-bit words starting
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* at ffb->suvtx.
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*/
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/* Capture rendering attributes. */
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ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */
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ctx->wid = upa_readl(&ffb->wid); /* Current WID */
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ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */
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ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */
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ctx->consty = upa_readl(&ffb->consty); /* Constant Y */
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ctx->constz = upa_readl(&ffb->constz); /* Constant Z */
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ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */
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ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */
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ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */
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ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */
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ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */
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ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */
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ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */
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ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */
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ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */
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ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */
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ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */
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ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */
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ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */
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ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */
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ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */
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ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */
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ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */
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ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */
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ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */
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ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */
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ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */
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ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */
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ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */
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ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */
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/* Auxiliary Clips. */
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ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min);
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ctx->auxclip0max = upa_readl(&ffb->auxclip[0].max);
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ctx->auxclip1min = upa_readl(&ffb->auxclip[1].min);
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ctx->auxclip1max = upa_readl(&ffb->auxclip[1].max);
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ctx->auxclip2min = upa_readl(&ffb->auxclip[2].min);
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ctx->auxclip2max = upa_readl(&ffb->auxclip[2].max);
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ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min);
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ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max);
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ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */
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ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */
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ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */
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ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */
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/* These registers/features only exist on FFB2 and later chips. */
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if (fpriv->ffb_type >= ffb2_prototype) {
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ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */
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ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */
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ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */
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ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */
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ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */
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ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */
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ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */
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ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */
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ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */
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/* And stencil/stencilctl only exists on FFB2+ and later
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* due to the introduction of 3DRAM-III.
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*/
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if (fpriv->ffb_type == ffb2_vertical_plus ||
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fpriv->ffb_type == ffb2_horizontal_plus) {
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ctx->stencil = upa_readl(&ffb->stencil);
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ctx->stencilctl = upa_readl(&ffb->stencilctl);
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}
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}
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/* Save the 32x32 area pattern. */
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for (i = 0; i < 32; i++)
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ctx->area_pattern[i] = upa_readl(&ffb->pattern[i]);
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/* Finally, stash away the User Constol/Status Register. */
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ctx->ucsr = upa_readl(&ffb->ucsr);
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}
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static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx)
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{
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ffb_fbcPtr ffb = fpriv->regs;
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struct ffb_hw_context *ctx;
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int i;
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ctx = fpriv->hw_state[idx - 1];
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if (idx == 0 || ctx == NULL)
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return;
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if (ctx->is_2d_only) {
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/* 2D applications only care about certain pieces
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* of state.
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*/
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upa_writel(ctx->drawop, &ffb->drawop);
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/* If we were restoring the vertex registers, this is where
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* we would do it. We would restore 32 32-bit words starting
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* at ffb->suvtx.
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*/
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upa_writel(ctx->ppc, &ffb->ppc);
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upa_writel(ctx->wid, &ffb->wid);
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upa_writel(ctx->fg, &ffb->fg);
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upa_writel(ctx->bg, &ffb->bg);
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upa_writel(ctx->xclip, &ffb->xclip);
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upa_writel(ctx->fbc, &ffb->fbc);
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upa_writel(ctx->rop, &ffb->rop);
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upa_writel(ctx->cmp, &ffb->cmp);
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upa_writel(ctx->matchab, &ffb->matchab);
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upa_writel(ctx->magnab, &ffb->magnab);
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upa_writel(ctx->pmask, &ffb->pmask);
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upa_writel(ctx->xpmask, &ffb->xpmask);
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upa_writel(ctx->lpat, &ffb->lpat);
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upa_writel(ctx->fontxy, &ffb->fontxy);
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upa_writel(ctx->fontw, &ffb->fontw);
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upa_writel(ctx->fontinc, &ffb->fontinc);
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/* stencil/stencilctl only exists on FFB2+ and later
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* due to the introduction of 3DRAM-III.
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*/
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if (fpriv->ffb_type == ffb2_vertical_plus ||
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fpriv->ffb_type == ffb2_horizontal_plus) {
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upa_writel(ctx->stencil, &ffb->stencil);
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upa_writel(ctx->stencilctl, &ffb->stencilctl);
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upa_writel(0x80000000, &ffb->fbc);
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upa_writel((ctx->stencilctl | 0x80000),
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&ffb->rawstencilctl);
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upa_writel(ctx->fbc, &ffb->fbc);
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}
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for (i = 0; i < 32; i++)
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upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
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upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
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return;
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}
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/* Restore drawop. */
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upa_writel(ctx->drawop, &ffb->drawop);
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/* If we were restoring the vertex registers, this is where
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* we would do it. We would restore 32 32-bit words starting
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* at ffb->suvtx.
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*/
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/* Restore rendering attributes. */
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upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */
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upa_writel(ctx->wid, &ffb->wid); /* Current WID */
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upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */
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upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */
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upa_writel(ctx->consty, &ffb->consty); /* Constant Y */
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upa_writel(ctx->constz, &ffb->constz); /* Constant Z */
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upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */
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upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */
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upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */
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upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */
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upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */
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upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */
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upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */
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upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */
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upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */
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upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */
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upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */
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upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */
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upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */
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upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */
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upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */
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upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */
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upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */
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upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */
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upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */
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upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */
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upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */
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upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */
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upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */
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upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */
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/* Auxiliary Clips. */
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upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min);
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upa_writel(ctx->auxclip0max, &ffb->auxclip[0].max);
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upa_writel(ctx->auxclip1min, &ffb->auxclip[1].min);
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upa_writel(ctx->auxclip1max, &ffb->auxclip[1].max);
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upa_writel(ctx->auxclip2min, &ffb->auxclip[2].min);
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upa_writel(ctx->auxclip2max, &ffb->auxclip[2].max);
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upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min);
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upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max);
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upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */
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upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */
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upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */
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upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */
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/* These registers/features only exist on FFB2 and later chips. */
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|
|
if (fpriv->ffb_type >= ffb2_prototype) {
|
||
|
|
upa_writel(ctx->dcss1, &ffb->dcss1); /* Depth Cue Scale Slope 1 */
|
||
|
|
upa_writel(ctx->dcss2, &ffb->dcss2); /* Depth Cue Scale Slope 2 */
|
||
|
|
upa_writel(ctx->dcss3, &ffb->dcss2); /* Depth Cue Scale Slope 3 */
|
||
|
|
upa_writel(ctx->dcs2, &ffb->dcs2); /* Depth Cue Scale 2 */
|
||
|
|
upa_writel(ctx->dcs3, &ffb->dcs3); /* Depth Cue Scale 3 */
|
||
|
|
upa_writel(ctx->dcs4, &ffb->dcs4); /* Depth Cue Scale 4 */
|
||
|
|
upa_writel(ctx->dcd2, &ffb->dcd2); /* Depth Cue Depth 2 */
|
||
|
|
upa_writel(ctx->dcd3, &ffb->dcd3); /* Depth Cue Depth 3 */
|
||
|
|
upa_writel(ctx->dcd4, &ffb->dcd4); /* Depth Cue Depth 4 */
|
||
|
|
|
||
|
|
/* And stencil/stencilctl only exists on FFB2+ and later
|
||
|
|
* due to the introduction of 3DRAM-III.
|
||
|
|
*/
|
||
|
|
if (fpriv->ffb_type == ffb2_vertical_plus ||
|
||
|
|
fpriv->ffb_type == ffb2_horizontal_plus) {
|
||
|
|
/* Unfortunately, there is a hardware bug on
|
||
|
|
* the FFB2+ chips which prevents a normal write
|
||
|
|
* to the stencil control register from working
|
||
|
|
* as it should.
|
||
|
|
*
|
||
|
|
* The state controlled by the FFB stencilctl register
|
||
|
|
* really gets transferred to the per-buffer instances
|
||
|
|
* of the stencilctl register in the 3DRAM chips.
|
||
|
|
*
|
||
|
|
* The bug is that FFB does not update buffer C correctly,
|
||
|
|
* so we have to do it by hand for them.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* This will update buffers A and B. */
|
||
|
|
upa_writel(ctx->stencil, &ffb->stencil);
|
||
|
|
upa_writel(ctx->stencilctl, &ffb->stencilctl);
|
||
|
|
|
||
|
|
/* Force FFB to use buffer C 3dram regs. */
|
||
|
|
upa_writel(0x80000000, &ffb->fbc);
|
||
|
|
upa_writel((ctx->stencilctl | 0x80000),
|
||
|
|
&ffb->rawstencilctl);
|
||
|
|
|
||
|
|
/* Now restore the correct FBC controls. */
|
||
|
|
upa_writel(ctx->fbc, &ffb->fbc);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restore the 32x32 area pattern. */
|
||
|
|
for (i = 0; i < 32; i++)
|
||
|
|
upa_writel(ctx->area_pattern[i], &ffb->pattern[i]);
|
||
|
|
|
||
|
|
/* Finally, stash away the User Constol/Status Register.
|
||
|
|
* The only state we really preserve here is the picking
|
||
|
|
* control.
|
||
|
|
*/
|
||
|
|
upa_writel((ctx->ucsr & 0xf0000), &ffb->ucsr);
|
||
|
|
}
|
||
|
|
|
||
|
|
#define FFB_UCSR_FB_BUSY 0x01000000
|
||
|
|
#define FFB_UCSR_RP_BUSY 0x02000000
|
||
|
|
#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
|
||
|
|
|
||
|
|
static void FFBWait(ffb_fbcPtr ffb)
|
||
|
|
{
|
||
|
|
int limit = 100000;
|
||
|
|
|
||
|
|
do {
|
||
|
|
u32 regval = upa_readl(&ffb->ucsr);
|
||
|
|
|
||
|
|
if ((regval & FFB_UCSR_ALL_BUSY) == 0)
|
||
|
|
break;
|
||
|
|
} while (--limit);
|
||
|
|
}
|
||
|
|
|
||
|
|
int ffb_driver_context_switch(drm_device_t *dev, int old, int new)
|
||
|
|
{
|
||
|
|
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
|
||
|
|
|
||
|
|
#ifdef DRM_DMA_HISTOGRAM
|
||
|
|
dev->ctx_start = get_cycles();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
DRM_DEBUG("Context switch from %d to %d\n", old, new);
|
||
|
|
|
||
|
|
if (new == dev->last_context ||
|
||
|
|
dev->last_context == 0) {
|
||
|
|
dev->last_context = new;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
FFBWait(fpriv->regs);
|
||
|
|
ffb_save_context(fpriv, old);
|
||
|
|
ffb_restore_context(fpriv, old, new);
|
||
|
|
FFBWait(fpriv->regs);
|
||
|
|
|
||
|
|
dev->last_context = new;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int ffb_driver_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
|
||
|
|
unsigned long arg)
|
||
|
|
{
|
||
|
|
drm_ctx_res_t res;
|
||
|
|
drm_ctx_t ctx;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
|
||
|
|
if (copy_from_user(&res, (drm_ctx_res_t __user *)arg, sizeof(res)))
|
||
|
|
return -EFAULT;
|
||
|
|
if (res.count >= DRM_RESERVED_CONTEXTS) {
|
||
|
|
memset(&ctx, 0, sizeof(ctx));
|
||
|
|
for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
|
||
|
|
ctx.handle = i;
|
||
|
|
if (copy_to_user(&res.contexts[i],
|
||
|
|
&i,
|
||
|
|
sizeof(i)))
|
||
|
|
return -EFAULT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
res.count = DRM_RESERVED_CONTEXTS;
|
||
|
|
if (copy_to_user((drm_ctx_res_t __user *)arg, &res, sizeof(res)))
|
||
|
|
return -EFAULT;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
int ffb_driver_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
|
||
|
|
unsigned long arg)
|
||
|
|
{
|
||
|
|
drm_file_t *priv = filp->private_data;
|
||
|
|
drm_device_t *dev = priv->dev;
|
||
|
|
drm_ctx_t ctx;
|
||
|
|
int idx;
|
||
|
|
|
||
|
|
if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
idx = DRM(alloc_queue)(dev, (ctx.flags & _DRM_CONTEXT_2DONLY));
|
||
|
|
if (idx < 0)
|
||
|
|
return -ENFILE;
|
||
|
|
|
||
|
|
DRM_DEBUG("%d\n", ctx.handle);
|
||
|
|
ctx.handle = idx;
|
||
|
|
if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
|
||
|
|
unsigned long arg)
|
||
|
|
{
|
||
|
|
drm_file_t *priv = filp->private_data;
|
||
|
|
drm_device_t *dev = priv->dev;
|
||
|
|
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
|
||
|
|
struct ffb_hw_context *hwctx;
|
||
|
|
drm_ctx_t ctx;
|
||
|
|
int idx;
|
||
|
|
|
||
|
|
if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
idx = ctx.handle;
|
||
|
|
if (idx <= 0 || idx >= FFB_MAX_CTXS)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
hwctx = fpriv->hw_state[idx - 1];
|
||
|
|
if (hwctx == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if ((ctx.flags & _DRM_CONTEXT_2DONLY) == 0)
|
||
|
|
hwctx->is_2d_only = 0;
|
||
|
|
else
|
||
|
|
hwctx->is_2d_only = 1;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
|
||
|
|
unsigned long arg)
|
||
|
|
{
|
||
|
|
drm_file_t *priv = filp->private_data;
|
||
|
|
drm_device_t *dev = priv->dev;
|
||
|
|
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
|
||
|
|
struct ffb_hw_context *hwctx;
|
||
|
|
drm_ctx_t ctx;
|
||
|
|
int idx;
|
||
|
|
|
||
|
|
if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
idx = ctx.handle;
|
||
|
|
if (idx <= 0 || idx >= FFB_MAX_CTXS)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
hwctx = fpriv->hw_state[idx - 1];
|
||
|
|
if (hwctx == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (hwctx->is_2d_only != 0)
|
||
|
|
ctx.flags = _DRM_CONTEXT_2DONLY;
|
||
|
|
else
|
||
|
|
ctx.flags = 0;
|
||
|
|
|
||
|
|
if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int ffb_driver_switchctx(struct inode *inode, struct file *filp, unsigned int cmd,
|
||
|
|
unsigned long arg)
|
||
|
|
{
|
||
|
|
drm_file_t *priv = filp->private_data;
|
||
|
|
drm_device_t *dev = priv->dev;
|
||
|
|
drm_ctx_t ctx;
|
||
|
|
|
||
|
|
if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
DRM_DEBUG("%d\n", ctx.handle);
|
||
|
|
return ffb_driver_context_switch(dev, dev->last_context, ctx.handle);
|
||
|
|
}
|
||
|
|
|
||
|
|
int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
|
||
|
|
unsigned long arg)
|
||
|
|
{
|
||
|
|
drm_ctx_t ctx;
|
||
|
|
|
||
|
|
if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
DRM_DEBUG("%d\n", ctx.handle);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int ffb_driver_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
|
||
|
|
unsigned long arg)
|
||
|
|
{
|
||
|
|
drm_ctx_t ctx;
|
||
|
|
drm_file_t *priv = filp->private_data;
|
||
|
|
drm_device_t *dev = priv->dev;
|
||
|
|
ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
|
||
|
|
int idx;
|
||
|
|
|
||
|
|
if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx)))
|
||
|
|
return -EFAULT;
|
||
|
|
DRM_DEBUG("%d\n", ctx.handle);
|
||
|
|
|
||
|
|
idx = ctx.handle - 1;
|
||
|
|
if (idx < 0 || idx >= FFB_MAX_CTXS)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (fpriv->hw_state[idx] != NULL) {
|
||
|
|
kfree(fpriv->hw_state[idx]);
|
||
|
|
fpriv->hw_state[idx] = NULL;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ffb_set_context_ioctls(void)
|
||
|
|
{
|
||
|
|
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)].func = ffb_driver_addctx;
|
||
|
|
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)].func = ffb_driver_rmctx;
|
||
|
|
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)].func = ffb_driver_modctx;
|
||
|
|
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)].func = ffb_driver_getctx;
|
||
|
|
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func = ffb_driver_switchctx;
|
||
|
|
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)].func = ffb_driver_newctx;
|
||
|
|
DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)].func = ffb_driver_resctx;
|
||
|
|
|
||
|
|
}
|