2005-04-16 18:20:36 -04:00
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/* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
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* trampoline.S: Jump start slave processors on sparc64.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <asm/head.h>
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#include <asm/asi.h>
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#include <asm/lsu.h>
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#include <asm/dcr.h>
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#include <asm/dcu.h>
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#include <asm/pstate.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/spitfire.h>
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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#include <asm/mmu.h>
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.data
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.align 8
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call_method:
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.asciz "call-method"
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.align 8
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itlb_load:
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.asciz "SUNW,itlb-load"
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.align 8
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dtlb_load:
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.asciz "SUNW,dtlb-load"
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.text
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.align 8
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.globl sparc64_cpu_startup, sparc64_cpu_startup_end
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sparc64_cpu_startup:
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flushw
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BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_startup)
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BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_startup)
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ba,pt %xcc, spitfire_startup
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nop
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cheetah_plus_startup:
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/* Preserve OBP chosen DCU and DCR register settings. */
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ba,pt %xcc, cheetah_generic_startup
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nop
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cheetah_startup:
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mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
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wr %g1, %asr18
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sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
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sllx %g5, 32, %g5
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or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
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stxa %g5, [%g0] ASI_DCU_CONTROL_REG
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membar #Sync
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cheetah_generic_startup:
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mov TSB_EXTENSION_P, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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mov TSB_EXTENSION_S, %g3
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stxa %g0, [%g3] ASI_DMMU
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membar #Sync
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mov TSB_EXTENSION_N, %g3
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stxa %g0, [%g3] ASI_DMMU
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stxa %g0, [%g3] ASI_IMMU
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membar #Sync
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/* Disable STICK_INT interrupts. */
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sethi %hi(0x80000000), %g5
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sllx %g5, 32, %g5
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wr %g5, %asr25
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ba,pt %xcc, startup_continue
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nop
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spitfire_startup:
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mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
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stxa %g1, [%g0] ASI_LSU_CONTROL
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membar #Sync
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startup_continue:
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wrpr %g0, 15, %pil
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sethi %hi(0x80000000), %g2
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sllx %g2, 32, %g2
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wr %g2, 0, %tick_cmpr
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/* Call OBP by hand to lock KERNBASE into i/d tlbs.
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* We lock 2 consequetive entries if we are 'bigkernel'.
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*/
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mov %o0, %l0
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sethi %hi(prom_entry_lock), %g2
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1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 18:42:04 -04:00
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membar #StoreLoad | #StoreStore
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2005-04-16 18:20:36 -04:00
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brnz,pn %g1, 1b
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-27 18:42:04 -04:00
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nop
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2005-04-16 18:20:36 -04:00
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x10], %l2
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mov %sp, %l1
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add %l2, -(192 + 128), %sp
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flushw
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(itlb_load), %g2
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or %g2, %lo(itlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 23:11:33 -04:00
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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2005-04-16 18:20:36 -04:00
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 15, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 63, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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cmp %g2, 0
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be,pt %icc, do_dtlb
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nop
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(itlb_load), %g2
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or %g2, %lo(itlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 23:11:33 -04:00
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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2005-04-16 18:20:36 -04:00
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE + 0x400000), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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sethi %hi(0x400000), %g1
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add %g2, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 14, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 62, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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do_dtlb:
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(dtlb_load), %g2
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or %g2, %lo(dtlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
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[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 23:11:33 -04:00
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
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2005-04-16 18:20:36 -04:00
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 15, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 63, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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ldx [%g2 + 0x08], %o1
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call %o1
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add %sp, (2047 + 128), %o0
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sethi %hi(bigkernel), %g2
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lduw [%g2 + %lo(bigkernel)], %g2
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cmp %g2, 0
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be,pt %icc, do_unlock
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nop
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sethi %hi(call_method), %g2
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or %g2, %lo(call_method), %g2
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stx %g2, [%sp + 2047 + 128 + 0x00]
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mov 5, %g2
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stx %g2, [%sp + 2047 + 128 + 0x08]
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mov 1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x10]
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sethi %hi(dtlb_load), %g2
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or %g2, %lo(dtlb_load), %g2
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stx %g2, [%sp + 2047 + 128 + 0x18]
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 23:11:33 -04:00
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sethi %hi(prom_mmu_ihandle_cache), %g2
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lduw [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
|
2005-04-16 18:20:36 -04:00
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stx %g2, [%sp + 2047 + 128 + 0x20]
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sethi %hi(KERNBASE + 0x400000), %g2
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stx %g2, [%sp + 2047 + 128 + 0x28]
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sethi %hi(kern_locked_tte_data), %g2
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ldx [%g2 + %lo(kern_locked_tte_data)], %g2
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sethi %hi(0x400000), %g1
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add %g2, %g1, %g2
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stx %g2, [%sp + 2047 + 128 + 0x30]
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mov 14, %g2
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BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
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mov 62, %g2
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1:
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stx %g2, [%sp + 2047 + 128 + 0x38]
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sethi %hi(p1275buf), %g2
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or %g2, %lo(p1275buf), %g2
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|
ldx [%g2 + 0x08], %o1
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|
call %o1
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|
add %sp, (2047 + 128), %o0
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|
do_unlock:
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|
sethi %hi(prom_entry_lock), %g2
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|
stb %g0, [%g2 + %lo(prom_entry_lock)]
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|
membar #StoreStore | #StoreLoad
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|
mov %l1, %sp
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|
flushw
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mov %l0, %o0
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wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
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|
wr %g0, 0, %fprs
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|
/* XXX Buggy PROM... */
|
|
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srl %o0, 0, %o0
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|
ldx [%o0], %g6
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|
|
wr %g0, ASI_P, %asi
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|
mov PRIMARY_CONTEXT, %g7
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|
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|
|
stxa %g0, [%g7] ASI_DMMU
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|
|
membar #Sync
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|
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|
|
mov SECONDARY_CONTEXT, %g7
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|
|
stxa %g0, [%g7] ASI_DMMU
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|
|
|
membar #Sync
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|
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|
mov 1, %g5
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|
|
sllx %g5, THREAD_SHIFT, %g5
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|
|
sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
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|
|
add %g6, %g5, %sp
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|
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|
|
mov 0, %fp
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|
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|
|
|
wrpr %g0, 0, %wstate
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|
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|
|
wrpr %g0, 0, %tl
|
|
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|
|
|
|
|
|
|
/* Setup the trap globals, then we can resurface. */
|
|
|
|
|
rdpr %pstate, %o1
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|
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|
|
mov %g6, %o2
|
|
|
|
|
wrpr %o1, PSTATE_AG, %pstate
|
|
|
|
|
sethi %hi(sparc64_ttable_tl0), %g5
|
|
|
|
|
wrpr %g5, %tba
|
|
|
|
|
mov %o2, %g6
|
|
|
|
|
|
|
|
|
|
wrpr %o1, PSTATE_MG, %pstate
|
|
|
|
|
#define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
|
|
|
|
|
#define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
|
|
|
|
|
|
|
|
|
|
mov TSB_REG, %g1
|
|
|
|
|
stxa %g0, [%g1] ASI_DMMU
|
|
|
|
|
membar #Sync
|
|
|
|
|
mov TLB_SFSR, %g1
|
|
|
|
|
sethi %uhi(KERN_HIGHBITS), %g2
|
|
|
|
|
or %g2, %ulo(KERN_HIGHBITS), %g2
|
|
|
|
|
sllx %g2, 32, %g2
|
|
|
|
|
or %g2, KERN_LOWBITS, %g2
|
|
|
|
|
|
|
|
|
|
BRANCH_IF_ANY_CHEETAH(g3,g7,9f)
|
|
|
|
|
|
|
|
|
|
ba,pt %xcc, 1f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
9:
|
|
|
|
|
sethi %uhi(VPTE_BASE_CHEETAH), %g3
|
|
|
|
|
or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
|
|
|
|
|
ba,pt %xcc, 2f
|
|
|
|
|
sllx %g3, 32, %g3
|
|
|
|
|
1:
|
|
|
|
|
sethi %uhi(VPTE_BASE_SPITFIRE), %g3
|
|
|
|
|
or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
|
|
|
|
|
sllx %g3, 32, %g3
|
|
|
|
|
|
|
|
|
|
2:
|
|
|
|
|
clr %g7
|
|
|
|
|
#undef KERN_HIGHBITS
|
|
|
|
|
#undef KERN_LOWBITS
|
|
|
|
|
|
|
|
|
|
wrpr %o1, 0x0, %pstate
|
|
|
|
|
ldx [%g6 + TI_TASK], %g4
|
|
|
|
|
|
|
|
|
|
wrpr %g0, 0, %wstate
|
|
|
|
|
|
|
|
|
|
call init_irqwork_curcpu
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)
|
|
|
|
|
ba,pt %xcc, 2f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
1: /* Start using proper page size encodings in ctx register. */
|
|
|
|
|
sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3
|
|
|
|
|
mov PRIMARY_CONTEXT, %g1
|
|
|
|
|
sllx %g3, 32, %g3
|
|
|
|
|
sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
|
|
|
|
|
or %g3, %g2, %g3
|
|
|
|
|
stxa %g3, [%g1] ASI_DMMU
|
|
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
|
|
2:
|
|
|
|
|
rdpr %pstate, %o1
|
|
|
|
|
or %o1, PSTATE_IE, %o1
|
|
|
|
|
wrpr %o1, 0, %pstate
|
|
|
|
|
|
|
|
|
|
call prom_set_trap_table
|
|
|
|
|
sethi %hi(sparc64_ttable_tl0), %o0
|
|
|
|
|
|
|
|
|
|
call smp_callin
|
|
|
|
|
nop
|
|
|
|
|
call cpu_idle
|
|
|
|
|
mov 0, %o0
|
|
|
|
|
call cpu_panic
|
|
|
|
|
nop
|
|
|
|
|
1: b,a,pt %xcc, 1b
|
|
|
|
|
|
|
|
|
|
.align 8
|
|
|
|
|
sparc64_cpu_startup_end:
|
