2009-04-27 22:52:28 -04:00
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/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/usb.h>
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2009-04-27 22:52:34 -04:00
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#include <linux/pci.h>
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2009-04-27 22:52:28 -04:00
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#include "xhci.h"
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2009-04-27 22:52:34 -04:00
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/*
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* Allocates a generic ring segment from the ring pool, sets the dma address,
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* initializes the segment to zero, and sets the private next pointer to NULL.
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*
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* Section 4.11.1.1:
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* "All components of all Command and Transfer TRBs shall be initialized to '0'"
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*/
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static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
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{
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struct xhci_segment *seg;
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dma_addr_t dma;
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seg = kzalloc(sizeof *seg, flags);
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if (!seg)
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return 0;
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xhci_dbg(xhci, "Allocating priv segment structure at 0x%x\n",
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(unsigned int) seg);
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seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
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if (!seg->trbs) {
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kfree(seg);
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return 0;
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}
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xhci_dbg(xhci, "// Allocating segment at 0x%x (virtual) 0x%x (DMA)\n",
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(unsigned int) seg->trbs, (u32) dma);
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memset(seg->trbs, 0, SEGMENT_SIZE);
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seg->dma = dma;
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seg->next = NULL;
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return seg;
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}
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static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
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{
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if (!seg)
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return;
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if (seg->trbs) {
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xhci_dbg(xhci, "Freeing DMA segment at 0x%x"
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" (virtual) 0x%x (DMA)\n",
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(unsigned int) seg->trbs, (u32) seg->dma);
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dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
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seg->trbs = NULL;
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}
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xhci_dbg(xhci, "Freeing priv segment structure at 0x%x\n",
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(unsigned int) seg);
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kfree(seg);
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}
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/*
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* Make the prev segment point to the next segment.
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*
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* Change the last TRB in the prev segment to be a Link TRB which points to the
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* DMA address of the next segment. The caller needs to set any Link TRB
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* related flags, such as End TRB, Toggle Cycle, and no snoop.
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*/
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static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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struct xhci_segment *next, bool link_trbs)
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{
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u32 val;
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if (!prev || !next)
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return;
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prev->next = next;
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if (link_trbs) {
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prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr[0] = next->dma;
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/* Set the last TRB in the segment to have a TRB type ID of Link TRB */
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val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
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val &= ~TRB_TYPE_BITMASK;
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val |= TRB_TYPE(TRB_LINK);
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prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
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}
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xhci_dbg(xhci, "Linking segment 0x%x to segment 0x%x (DMA)\n",
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prev->dma, next->dma);
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}
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/* XXX: Do we need the hcd structure in all these functions? */
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static void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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struct xhci_segment *seg;
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struct xhci_segment *first_seg;
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if (!ring || !ring->first_seg)
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return;
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first_seg = ring->first_seg;
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seg = first_seg->next;
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xhci_dbg(xhci, "Freeing ring at 0x%x\n", (unsigned int) ring);
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while (seg != first_seg) {
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struct xhci_segment *next = seg->next;
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xhci_segment_free(xhci, seg);
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seg = next;
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}
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xhci_segment_free(xhci, first_seg);
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ring->first_seg = NULL;
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kfree(ring);
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}
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/**
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* Create a new ring with zero or more segments.
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*
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* Link each segment together into a ring.
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* Set the end flag and the cycle toggle bit on the last segment.
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* See section 4.9.1 and figures 15 and 16.
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*/
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static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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unsigned int num_segs, bool link_trbs, gfp_t flags)
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{
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struct xhci_ring *ring;
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struct xhci_segment *prev;
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ring = kzalloc(sizeof *(ring), flags);
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xhci_dbg(xhci, "Allocating ring at 0x%x\n", (unsigned int) ring);
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if (!ring)
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return 0;
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if (num_segs == 0)
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return ring;
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ring->first_seg = xhci_segment_alloc(xhci, flags);
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if (!ring->first_seg)
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goto fail;
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num_segs--;
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prev = ring->first_seg;
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while (num_segs > 0) {
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struct xhci_segment *next;
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next = xhci_segment_alloc(xhci, flags);
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if (!next)
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goto fail;
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xhci_link_segments(xhci, prev, next, link_trbs);
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prev = next;
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num_segs--;
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}
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xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
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if (link_trbs) {
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/* See section 4.9.2.1 and 6.4.4.1 */
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prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
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xhci_dbg(xhci, "Wrote link toggle flag to"
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" segment 0x%x (virtual), 0x%x (DMA)\n",
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(unsigned int) prev, (u32) prev->dma);
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}
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/* The ring is empty, so the enqueue pointer == dequeue pointer */
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ring->enqueue = ring->first_seg->trbs;
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2009-04-27 22:53:56 -04:00
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ring->enq_seg = ring->first_seg;
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2009-04-27 22:52:34 -04:00
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ring->dequeue = ring->enqueue;
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2009-04-27 22:53:56 -04:00
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ring->deq_seg = ring->first_seg;
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2009-04-27 22:52:34 -04:00
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/* The ring is initialized to 0. The producer must write 1 to the cycle
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* bit to handover ownership of the TRB, so PCS = 1. The consumer must
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* compare CCS to the cycle bit to check ownership, so CCS = 1.
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*/
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ring->cycle_state = 1;
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return ring;
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fail:
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xhci_ring_free(xhci, ring);
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return 0;
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}
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2009-04-27 22:52:28 -04:00
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void xhci_mem_cleanup(struct xhci_hcd *xhci)
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{
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2009-04-27 22:52:34 -04:00
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struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
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int size;
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/* XXX: Free all the segments in the various rings */
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/* Free the Event Ring Segment Table and the actual Event Ring */
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xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
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xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
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xhci_writel(xhci, 0, &xhci->ir_set->erst_base[0]);
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xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[1]);
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xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[0]);
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size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
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if (xhci->erst.entries)
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pci_free_consistent(pdev, size,
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xhci->erst.entries, xhci->erst.erst_dma_addr);
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xhci->erst.entries = NULL;
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xhci_dbg(xhci, "Freed ERST\n");
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if (xhci->event_ring)
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xhci_ring_free(xhci, xhci->event_ring);
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xhci->event_ring = NULL;
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xhci_dbg(xhci, "Freed event ring\n");
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xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[1]);
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xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[0]);
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if (xhci->cmd_ring)
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xhci_ring_free(xhci, xhci->cmd_ring);
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xhci->cmd_ring = NULL;
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xhci_dbg(xhci, "Freed command ring\n");
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if (xhci->segment_pool)
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dma_pool_destroy(xhci->segment_pool);
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xhci->segment_pool = NULL;
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xhci_dbg(xhci, "Freed segment pool\n");
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2009-04-27 22:53:42 -04:00
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xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[1]);
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xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[0]);
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if (xhci->dcbaa)
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pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
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xhci->dcbaa, xhci->dcbaa->dma);
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xhci->dcbaa = NULL;
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2009-04-27 22:52:28 -04:00
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xhci->page_size = 0;
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xhci->page_shift = 0;
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}
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int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
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{
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2009-04-27 22:52:34 -04:00
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dma_addr_t dma;
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struct device *dev = xhci_to_hcd(xhci)->self.controller;
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2009-04-27 22:52:28 -04:00
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unsigned int val, val2;
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2009-04-27 22:52:34 -04:00
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struct xhci_segment *seg;
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2009-04-27 22:52:28 -04:00
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u32 page_size;
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int i;
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page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
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xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
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for (i = 0; i < 16; i++) {
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if ((0x1 & page_size) != 0)
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break;
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page_size = page_size >> 1;
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}
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if (i < 16)
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xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
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else
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xhci_warn(xhci, "WARN: no supported page size\n");
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/* Use 4K pages, since that's common and the minimum the HC supports */
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xhci->page_shift = 12;
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xhci->page_size = 1 << xhci->page_shift;
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xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
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/*
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* Program the Number of Device Slots Enabled field in the CONFIG
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* register with the max value of slots the HC can handle.
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*/
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val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
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xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
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(unsigned int) val);
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val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
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val |= (val2 & ~HCS_SLOTS_MASK);
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xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
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(unsigned int) val);
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xhci_writel(xhci, val, &xhci->op_regs->config_reg);
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2009-04-27 22:53:42 -04:00
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/*
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* Section 5.4.8 - doorbell array must be
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* "physically contiguous and 64-byte (cache line) aligned".
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*/
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xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
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sizeof(*xhci->dcbaa), &dma);
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if (!xhci->dcbaa)
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goto fail;
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memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
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xhci->dcbaa->dma = dma;
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xhci_dbg(xhci, "// Setting device context base array address to 0x%x\n",
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xhci->dcbaa->dma);
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xhci_writel(xhci, (u32) 0, &xhci->op_regs->dcbaa_ptr[1]);
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xhci_writel(xhci, dma, &xhci->op_regs->dcbaa_ptr[0]);
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2009-04-27 22:52:34 -04:00
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/*
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* Initialize the ring segment pool. The ring must be a contiguous
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* structure comprised of TRBs. The TRBs must be 16 byte aligned,
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* however, the command ring segment needs 64-byte aligned segments,
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* so we pick the greater alignment need.
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*/
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xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
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SEGMENT_SIZE, 64, xhci->page_size);
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if (!xhci->segment_pool)
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goto fail;
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/* Set up the command ring to have one segments for now. */
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xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
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if (!xhci->cmd_ring)
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goto fail;
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xhci_dbg(xhci, "Allocated command ring at 0x%x\n", (unsigned int) xhci->cmd_ring);
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xhci_dbg(xhci, "First segment DMA is 0x%x\n", (unsigned int) xhci->cmd_ring->first_seg->dma);
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/* Set the address in the Command Ring Control register */
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val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]);
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val = (val & ~CMD_RING_ADDR_MASK) |
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(xhci->cmd_ring->first_seg->dma & CMD_RING_ADDR_MASK) |
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xhci->cmd_ring->cycle_state;
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xhci_dbg(xhci, "// Setting command ring address high bits to 0x0\n");
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xhci_writel(xhci, (u32) 0, &xhci->op_regs->cmd_ring[1]);
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xhci_dbg(xhci, "// Setting command ring address low bits to 0x%x\n", val);
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xhci_writel(xhci, val, &xhci->op_regs->cmd_ring[0]);
|
|
|
|
xhci_dbg_cmd_ptrs(xhci);
|
|
|
|
|
|
|
|
val = xhci_readl(xhci, &xhci->cap_regs->db_off);
|
|
|
|
val &= DBOFF_MASK;
|
|
|
|
xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
|
|
|
|
" from cap regs base addr\n", val);
|
|
|
|
xhci->dba = (void *) xhci->cap_regs + val;
|
|
|
|
xhci_dbg_regs(xhci);
|
|
|
|
xhci_print_run_regs(xhci);
|
|
|
|
/* Set ir_set to interrupt register set 0 */
|
|
|
|
xhci->ir_set = (void *) xhci->run_regs->ir_set;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Event ring setup: Allocate a normal ring, but also setup
|
|
|
|
* the event ring segment table (ERST). Section 4.9.3.
|
|
|
|
*/
|
|
|
|
xhci_dbg(xhci, "// Allocating event ring\n");
|
|
|
|
xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
|
|
|
|
if (!xhci->event_ring)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
|
|
|
|
sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
|
|
|
|
if (!xhci->erst.entries)
|
|
|
|
goto fail;
|
|
|
|
xhci_dbg(xhci, "// Allocated event ring segment table at 0x%x\n", dma);
|
|
|
|
|
|
|
|
memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
|
|
|
|
xhci->erst.num_entries = ERST_NUM_SEGS;
|
|
|
|
xhci->erst.erst_dma_addr = dma;
|
|
|
|
xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = 0x%x, dma addr = 0x%x\n",
|
|
|
|
xhci->erst.num_entries,
|
|
|
|
(unsigned int) xhci->erst.entries,
|
|
|
|
xhci->erst.erst_dma_addr);
|
|
|
|
|
|
|
|
/* set ring base address and size for each segment table entry */
|
|
|
|
for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
|
|
|
|
struct xhci_erst_entry *entry = &xhci->erst.entries[val];
|
|
|
|
entry->seg_addr[1] = 0;
|
|
|
|
entry->seg_addr[0] = seg->dma;
|
|
|
|
entry->seg_size = TRBS_PER_SEGMENT;
|
|
|
|
entry->rsvd = 0;
|
|
|
|
seg = seg->next;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set ERST count with the number of entries in the segment table */
|
|
|
|
val = xhci_readl(xhci, &xhci->ir_set->erst_size);
|
|
|
|
val &= ERST_SIZE_MASK;
|
|
|
|
val |= ERST_NUM_SEGS;
|
|
|
|
xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
|
|
|
|
val);
|
|
|
|
xhci_writel(xhci, val, &xhci->ir_set->erst_size);
|
|
|
|
|
|
|
|
xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
|
|
|
|
/* set the segment table base address */
|
|
|
|
xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%x\n",
|
|
|
|
xhci->erst.erst_dma_addr);
|
|
|
|
xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
|
|
|
|
val = xhci_readl(xhci, &xhci->ir_set->erst_base[0]);
|
|
|
|
val &= ERST_PTR_MASK;
|
|
|
|
val |= (xhci->erst.erst_dma_addr & ~ERST_PTR_MASK);
|
|
|
|
xhci_writel(xhci, val, &xhci->ir_set->erst_base[0]);
|
|
|
|
|
|
|
|
/* Set the event ring dequeue address */
|
2009-04-27 22:53:56 -04:00
|
|
|
set_hc_event_deq(xhci);
|
2009-04-27 22:52:34 -04:00
|
|
|
xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
|
|
|
|
xhci_print_ir_set(xhci, xhci->ir_set, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX: Might need to set the Interrupter Moderation Register to
|
|
|
|
* something other than the default (~1ms minimum between interrupts).
|
|
|
|
* See section 5.5.1.2.
|
|
|
|
*/
|
2009-04-27 22:52:28 -04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
|
|
xhci_warn(xhci, "Couldn't initialize memory\n");
|
|
|
|
xhci_mem_cleanup(xhci);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|