2005-07-25 18:45:45 -04:00
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/*
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* linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c
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*
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* Toshiba RBTX4938 specific interrupt handlers
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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/*
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IRQ Device
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16 TX4938-CP0/00 Software 0
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17 TX4938-CP0/01 Software 1
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18 TX4938-CP0/02 Cascade TX4938-CP0
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19 TX4938-CP0/03 Multiplexed -- do not use
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20 TX4938-CP0/04 Multiplexed -- do not use
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21 TX4938-CP0/05 Multiplexed -- do not use
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22 TX4938-CP0/06 Multiplexed -- do not use
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23 TX4938-CP0/07 CPU TIMER
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24 TX4938-PIC/00
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25 TX4938-PIC/01
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26 TX4938-PIC/02 Cascade RBTX4938-IOC
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27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
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28 TX4938-PIC/04
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29 TX4938-PIC/05 TX4938 ETH1
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30 TX4938-PIC/06 TX4938 ETH0
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31 TX4938-PIC/07
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32 TX4938-PIC/08 TX4938 SIO 0
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33 TX4938-PIC/09 TX4938 SIO 1
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34 TX4938-PIC/10 TX4938 DMA0
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35 TX4938-PIC/11 TX4938 DMA1
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36 TX4938-PIC/12 TX4938 DMA2
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37 TX4938-PIC/13 TX4938 DMA3
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38 TX4938-PIC/14
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39 TX4938-PIC/15
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40 TX4938-PIC/16 TX4938 PCIC
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41 TX4938-PIC/17 TX4938 TMR0
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42 TX4938-PIC/18 TX4938 TMR1
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43 TX4938-PIC/19 TX4938 TMR2
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44 TX4938-PIC/20
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45 TX4938-PIC/21
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46 TX4938-PIC/22 TX4938 PCIERR
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47 TX4938-PIC/23
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48 TX4938-PIC/24
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49 TX4938-PIC/25
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50 TX4938-PIC/26
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51 TX4938-PIC/27
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52 TX4938-PIC/28
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53 TX4938-PIC/29
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54 TX4938-PIC/30
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55 TX4938-PIC/31 TX4938 SPI
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56 RBTX4938-IOC/00 PCI-D
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57 RBTX4938-IOC/01 PCI-C
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58 RBTX4938-IOC/02 PCI-B
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59 RBTX4938-IOC/03 PCI-A
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60 RBTX4938-IOC/04 RTC
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61 RBTX4938-IOC/05 ATA
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62 RBTX4938-IOC/06 MODEM
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63 RBTX4938-IOC/07 SWINT
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/timex.h>
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#include <asm/bootinfo.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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2006-08-20 09:55:52 -04:00
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#include <asm/wbflush.h>
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2005-07-25 18:45:45 -04:00
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#include <linux/bootmem.h>
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#include <asm/tx4938/rbtx4938.h>
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static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
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static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
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static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
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static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
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static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
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static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
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DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
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#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
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2006-07-02 09:41:42 -04:00
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static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
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2005-07-25 18:45:45 -04:00
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.typename = TOSHIBA_RBTX4938_IOC_NAME,
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.startup = toshiba_rbtx4938_irq_ioc_startup,
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.shutdown = toshiba_rbtx4938_irq_ioc_shutdown,
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.enable = toshiba_rbtx4938_irq_ioc_enable,
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.disable = toshiba_rbtx4938_irq_ioc_disable,
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.ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
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.end = toshiba_rbtx4938_irq_ioc_end,
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.set_affinity = NULL
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};
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#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
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#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a
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int
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toshiba_rbtx4938_irq_nested(int sw_irq)
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{
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u8 level3;
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level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;
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if (level3) {
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/* must use fls so onboard ATA has priority */
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sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
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}
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wbflush();
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return sw_irq;
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}
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static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
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.handler = no_action,
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.flags = 0,
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.mask = CPU_MASK_NONE,
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.name = TOSHIBA_RBTX4938_IOC_NAME,
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};
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/**********************************************************************************/
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/* Functions for ioc */
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/**********************************************************************************/
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static void __init
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toshiba_rbtx4938_irq_ioc_init(void)
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{
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int i;
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for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
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i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 3;
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 05:24:36 -04:00
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irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type;
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2005-07-25 18:45:45 -04:00
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}
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setup_irq(RBTX4938_IRQ_IOCINT,
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&toshiba_rbtx4938_irq_ioc_action);
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}
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static unsigned int
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toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
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{
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toshiba_rbtx4938_irq_ioc_enable(irq);
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return 0;
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}
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static void
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toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
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{
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toshiba_rbtx4938_irq_ioc_disable(irq);
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}
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static void
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toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
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{
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unsigned long flags;
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volatile unsigned char v;
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spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
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v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
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TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
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mmiowb();
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TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
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}
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static void
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toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
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{
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unsigned long flags;
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volatile unsigned char v;
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spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
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v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
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TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
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mmiowb();
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TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
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spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
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}
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static void
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toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
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{
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toshiba_rbtx4938_irq_ioc_disable(irq);
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}
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static void
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toshiba_rbtx4938_irq_ioc_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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toshiba_rbtx4938_irq_ioc_enable(irq);
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}
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}
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extern void __init txx9_spi_irqinit(int irc_irq);
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void __init arch_init_irq(void)
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{
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extern void tx4938_irq_init(void);
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/* Now, interrupt control disabled, */
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/* all IRC interrupts are masked, */
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/* all IRC interrupt mode are Low Active. */
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/* mask all IOC interrupts */
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*rbtx4938_imask_ptr = 0;
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/* clear SoftInt interrupts */
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*rbtx4938_softint_ptr = 0;
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tx4938_irq_init();
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toshiba_rbtx4938_irq_ioc_init();
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/* Onboard 10M Ether: High Active */
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TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040);
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if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) {
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txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI);
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}
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wbflush();
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}
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