248 lines
8.3 KiB
C
248 lines
8.3 KiB
C
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/*
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* arch/ppc/platforms/adir_pci.c
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*
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* PCI support for SBS Adirondack
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*
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* By Michael Sokolov <msokolov@ivan.Harhan.ORG>
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* based on the K2 version by Matt Porter <mporter@mvista.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <syslib/cpc710.h>
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#include "adir.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif /* DEBUG */
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static inline int __init
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adir_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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#define PCIIRQ(a,b,c,d) {ADIR_IRQ_##a,ADIR_IRQ_##b,ADIR_IRQ_##c,ADIR_IRQ_##d},
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struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
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/*
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* The three PCI devices on the motherboard have dedicated lines to the
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* CPLD interrupt controller, bypassing the standard PCI INTA-D and the
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* PC interrupt controller. All other PCI devices (slots) have usual
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* staggered INTA-D lines, resulting in 8 lines total (PCI0 INTA-D and
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* PCI1 INTA-D). All 8 go to the CPLD interrupt controller. PCI0 INTA-D
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* also go to the south bridge, so we have the option of taking them
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* via the CPLD interrupt controller or via the south bridge 8259
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* 8258 thingy. PCI1 INTA-D can only be taken via the CPLD interrupt
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* controller. We take all PCI interrupts via the CPLD interrupt
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* controller as recommended by SBS.
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*
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* We also have some monkey business with the PCI devices within the
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* VT82C686B south bridge itself. This chip actually has 7 functions on
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* its IDSEL. Function 0 is the actual south bridge, function 1 is IDE,
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* and function 4 is some special stuff. The other 4 functions are just
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* regular PCI devices bundled in the chip. 2 and 3 are USB UHCIs and 5
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* and 6 are audio (not supported on the Adirondack).
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*
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* This is where the monkey business begins. PCI devices are supposed
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* to signal normal PCI interrupts. But the 4 functions in question are
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* located in the south bridge chip, which is designed with the
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* assumption that it will be fielding PCI INTA-D interrupts rather
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* than generating them. Here's what it does. Each of the functions in
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* question routes its interrupt to one of the IRQs on the 8259 thingy.
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* Which one? It looks at the Interrupt Line register in the PCI config
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* space, even though the PCI spec says it's for BIOS/OS interaction
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* only.
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*
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* How do we deal with this? We take these interrupts via 8259 IRQs as
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* we have to. We return the desired IRQ numbers from this routine when
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* called for the functions in question. The PCI scan code will then
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* stick our return value into the Interrupt Line register in the PCI
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* config space, and the interrupt will actually go there. We identify
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* these functions within the south bridge IDSEL by their interrupt pin
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* numbers, as the VT82C686B has 04 in the Interrupt Pin register for
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* USB and 03 for audio.
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*/
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if (!hose->index) {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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/* south bridge */ PCIIRQ(IDE0, NONE, VIA_AUDIO, VIA_USB)
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/* Ethernet 0 */ PCIIRQ(MBETH0, MBETH0, MBETH0, MBETH0)
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/* PCI0 slot 1 */ PCIIRQ(PCI0_INTB, PCI0_INTC, PCI0_INTD, PCI0_INTA)
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/* PCI0 slot 2 */ PCIIRQ(PCI0_INTC, PCI0_INTD, PCI0_INTA, PCI0_INTB)
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/* PCI0 slot 3 */ PCIIRQ(PCI0_INTD, PCI0_INTA, PCI0_INTB, PCI0_INTC)
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};
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const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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} else {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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/* Ethernet 1 */ PCIIRQ(MBETH1, MBETH1, MBETH1, MBETH1)
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/* SCSI */ PCIIRQ(MBSCSI, MBSCSI, MBSCSI, MBSCSI)
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/* PCI1 slot 1 */ PCIIRQ(PCI1_INTB, PCI1_INTC, PCI1_INTD, PCI1_INTA)
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/* PCI1 slot 2 */ PCIIRQ(PCI1_INTC, PCI1_INTD, PCI1_INTA, PCI1_INTB)
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/* PCI1 slot 3 */ PCIIRQ(PCI1_INTD, PCI1_INTA, PCI1_INTB, PCI1_INTC)
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};
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const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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#undef PCIIRQ
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}
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static void
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adir_pcibios_fixup_resources(struct pci_dev *dev)
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{
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int i;
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if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
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(dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64))
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{
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DBG("Fixup CPC710 resources\n");
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for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
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{
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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}
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}
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}
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/*
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* CPC710 DD3 has an errata causing it to hang the system if a type 0 config
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* cycle is attempted on its PCI32 interface with a device number > 21.
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* CPC710's PCI bridges map device numbers 1 through 21 to AD11 through AD31.
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* Per the PCI spec it MUST accept all other device numbers and do nothing, and
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* software MUST scan all device numbers without assuming how IDSELs are
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* mapped. However, as the CPC710 DD3's errata causes such correct scanning
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* procedure to hang the system, we have no choice but to introduce this hack
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* of knowingly avoiding device numbers > 21 on PCI0,
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*/
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static int
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adir_exclude_device(u_char bus, u_char devfn)
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{
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if ((bus == 0) && (PCI_SLOT(devfn) > 21))
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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void adir_find_bridges(void)
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{
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struct pci_controller *hose_a, *hose_b;
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/* Setup PCI32 hose */
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hose_a = pcibios_alloc_controller();
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if (!hose_a)
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return;
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hose_a->first_busno = 0;
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hose_a->last_busno = 0xff;
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hose_a->pci_mem_offset = ADIR_PCI32_MEM_BASE;
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hose_a->io_space.start = 0;
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hose_a->io_space.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
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hose_a->mem_space.start = 0;
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hose_a->mem_space.end = ADIR_PCI32_MEM_SIZE - 1;
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hose_a->io_resource.start = 0;
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hose_a->io_resource.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
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hose_a->io_resource.flags = IORESOURCE_IO;
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hose_a->mem_resources[0].start = ADIR_PCI32_MEM_BASE;
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hose_a->mem_resources[0].end = ADIR_PCI32_MEM_BASE +
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ADIR_PCI32_MEM_SIZE - 1;
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hose_a->mem_resources[0].flags = IORESOURCE_MEM;
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hose_a->io_base_phys = ADIR_PCI32_IO_BASE;
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hose_a->io_base_virt = (void *) ADIR_PCI32_VIRT_IO_BASE;
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ppc_md.pci_exclude_device = adir_exclude_device;
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setup_indirect_pci(hose_a, ADIR_PCI32_CONFIG_ADDR,
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ADIR_PCI32_CONFIG_DATA);
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/* Initialize PCI32 bus registers */
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early_write_config_byte(hose_a,
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hose_a->first_busno,
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PCI_DEVFN(0, 0),
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CPC710_BUS_NUMBER,
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hose_a->first_busno);
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early_write_config_byte(hose_a,
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hose_a->first_busno,
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PCI_DEVFN(0, 0),
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CPC710_SUB_BUS_NUMBER,
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hose_a->last_busno);
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hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
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/* Write out correct max subordinate bus number for hose A */
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early_write_config_byte(hose_a,
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hose_a->first_busno,
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PCI_DEVFN(0, 0),
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CPC710_SUB_BUS_NUMBER,
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hose_a->last_busno);
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/* Setup PCI64 hose */
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hose_b = pcibios_alloc_controller();
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if (!hose_b)
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return;
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hose_b->first_busno = hose_a->last_busno + 1;
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hose_b->last_busno = 0xff;
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hose_b->pci_mem_offset = ADIR_PCI64_MEM_BASE;
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hose_b->io_space.start = 0;
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hose_b->io_space.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
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hose_b->mem_space.start = 0;
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hose_b->mem_space.end = ADIR_PCI64_MEM_SIZE - 1;
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hose_b->io_resource.start = 0;
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hose_b->io_resource.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
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hose_b->io_resource.flags = IORESOURCE_IO;
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hose_b->mem_resources[0].start = ADIR_PCI64_MEM_BASE;
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hose_b->mem_resources[0].end = ADIR_PCI64_MEM_BASE +
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ADIR_PCI64_MEM_SIZE - 1;
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hose_b->mem_resources[0].flags = IORESOURCE_MEM;
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hose_b->io_base_phys = ADIR_PCI64_IO_BASE;
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hose_b->io_base_virt = (void *) ADIR_PCI64_VIRT_IO_BASE;
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setup_indirect_pci(hose_b, ADIR_PCI64_CONFIG_ADDR,
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ADIR_PCI64_CONFIG_DATA);
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/* Initialize PCI64 bus registers */
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early_write_config_byte(hose_b,
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0,
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PCI_DEVFN(0, 0),
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CPC710_SUB_BUS_NUMBER,
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0xff);
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early_write_config_byte(hose_b,
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0,
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PCI_DEVFN(0, 0),
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CPC710_BUS_NUMBER,
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hose_b->first_busno);
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hose_b->last_busno = pciauto_bus_scan(hose_b,
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hose_b->first_busno);
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/* Write out correct max subordinate bus number for hose B */
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early_write_config_byte(hose_b,
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hose_b->first_busno,
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PCI_DEVFN(0, 0),
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CPC710_SUB_BUS_NUMBER,
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hose_b->last_busno);
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ppc_md.pcibios_fixup = NULL;
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ppc_md.pcibios_fixup_resources = adir_pcibios_fixup_resources;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = adir_map_irq;
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}
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