2005-04-16 18:20:36 -04:00
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/*
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* Copyright (C) 2000, 2001 Wolfgang Denk, wd@denx.de
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* Modified for direct IDE interface
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* by Thomas Lange, thomas@corelatus.com
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* Modified for direct IDE interface on 8xx without using the PCMCIA
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* controller
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* by Steven.Scholz@imc-berlin.de
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* Moved out of arch/ppc/kernel/m8xx_setup.c, other minor cleanups
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* by Mathew Locke <mattl@mvista.com>
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/tty.h>
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#include <linux/major.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/ide.h>
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#include <linux/bootmem.h>
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#include <asm/mpc8xx.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/ide.h>
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#include <asm/8xx_immap.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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static int identify (volatile u8 *p);
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static void print_fixed (volatile u8 *p);
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static void print_funcid (int func);
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static int check_ide_device (unsigned long base);
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static void ide_interrupt_ack (void *dev);
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2007-10-11 17:54:00 -04:00
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static void m8xx_ide_set_pio_mode(ide_drive_t *drive, const u8 pio);
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2005-04-16 18:20:36 -04:00
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typedef struct ide_ioport_desc {
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unsigned long base_off; /* Offset to PCMCIA memory */
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unsigned long reg_off[IDE_NR_PORTS]; /* controller register offsets */
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int irq; /* IRQ */
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} ide_ioport_desc_t;
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ide_ioport_desc_t ioport_dsc[MAX_HWIFS] = {
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#ifdef IDE0_BASE_OFFSET
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{ IDE0_BASE_OFFSET,
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{
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IDE0_DATA_REG_OFFSET,
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IDE0_ERROR_REG_OFFSET,
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IDE0_NSECTOR_REG_OFFSET,
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IDE0_SECTOR_REG_OFFSET,
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IDE0_LCYL_REG_OFFSET,
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IDE0_HCYL_REG_OFFSET,
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IDE0_SELECT_REG_OFFSET,
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IDE0_STATUS_REG_OFFSET,
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IDE0_CONTROL_REG_OFFSET,
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IDE0_IRQ_REG_OFFSET,
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},
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IDE0_INTERRUPT,
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},
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#ifdef IDE1_BASE_OFFSET
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{ IDE1_BASE_OFFSET,
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{
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IDE1_DATA_REG_OFFSET,
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IDE1_ERROR_REG_OFFSET,
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IDE1_NSECTOR_REG_OFFSET,
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IDE1_SECTOR_REG_OFFSET,
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IDE1_LCYL_REG_OFFSET,
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IDE1_HCYL_REG_OFFSET,
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IDE1_SELECT_REG_OFFSET,
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IDE1_STATUS_REG_OFFSET,
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IDE1_CONTROL_REG_OFFSET,
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IDE1_IRQ_REG_OFFSET,
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},
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IDE1_INTERRUPT,
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},
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#endif /* IDE1_BASE_OFFSET */
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#endif /* IDE0_BASE_OFFSET */
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};
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ide_pio_timings_t ide_pio_clocks[6];
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int hold_time[6] = {30, 20, 15, 10, 10, 10 }; /* PIO Mode 5 with IORDY (nonstandard) */
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/*
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* Warning: only 1 (ONE) PCMCIA slot supported here,
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* which must be correctly initialized by the firmware (PPCBoot).
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*/
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static int _slot_ = -1; /* will be read from PCMCIA registers */
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/* Make clock cycles and always round up */
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#define PCMCIA_MK_CLKS( t, T ) (( (t) * ((T)/1000000) + 999U ) / 1000U )
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#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
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#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
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/*
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* The TQM850L hardware has two pins swapped! Grrrrgh!
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*/
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#ifdef CONFIG_TQM850L
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#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
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#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
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#else
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#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
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#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
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#endif
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#if defined(CONFIG_BLK_DEV_MPC8xx_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
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#define PCMCIA_SCHLVL IDE0_INTERRUPT /* Status Change Interrupt Level */
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static int pcmcia_schlvl = PCMCIA_SCHLVL;
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#endif
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/*
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* See include/linux/ide.h for definition of hw_regs_t (p, base)
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*/
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/*
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2008-04-17 18:46:29 -04:00
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* m8xx_ide_init_ports() for a direct IDE interface _using_
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* MPC8xx's internal PCMCIA interface
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2005-04-16 18:20:36 -04:00
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*/
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#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
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2008-04-26 11:36:38 -04:00
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static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
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2005-04-16 18:20:36 -04:00
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{
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unsigned long *p = hw->io_ports;
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int i;
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typedef struct {
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ulong br;
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ulong or;
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} pcmcia_win_t;
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volatile pcmcia_win_t *win;
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volatile pcmconf8xx_t *pcmp;
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uint *pgcrx;
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u32 pcmcia_phy_base;
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u32 pcmcia_phy_end;
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static unsigned long pcmcia_base = 0;
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unsigned long base;
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*p = 0;
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pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
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if (!pcmcia_base) {
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/*
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* Read out PCMCIA registers. Since the reset values
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* are undefined, we sure hope that they have been
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* set up by firmware
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*/
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/* Scan all registers for valid settings */
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pcmcia_phy_base = 0xFFFFFFFF;
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pcmcia_phy_end = 0;
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/* br0 is start of brX and orX regs */
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win = (pcmcia_win_t *) \
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(&(((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0));
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for (i = 0; i < 8; i++) {
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if (win->or & 1) { /* This bank is marked as valid */
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if (win->br < pcmcia_phy_base) {
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pcmcia_phy_base = win->br;
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}
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if ((win->br + PCMCIA_MEM_SIZE) > pcmcia_phy_end) {
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pcmcia_phy_end = win->br + PCMCIA_MEM_SIZE;
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}
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/* Check which slot that has been defined */
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_slot_ = (win->or >> 2) & 1;
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} /* Valid bank */
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win++;
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} /* for */
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printk ("PCMCIA slot %c: phys mem %08x...%08x (size %08x)\n",
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'A' + _slot_,
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pcmcia_phy_base, pcmcia_phy_end,
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pcmcia_phy_end - pcmcia_phy_base);
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pcmcia_base=(unsigned long)ioremap(pcmcia_phy_base,
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pcmcia_phy_end-pcmcia_phy_base);
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#ifdef DEBUG
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printk ("PCMCIA virt base: %08lx\n", pcmcia_base);
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#endif
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/* Compute clock cycles for PIO timings */
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for (i=0; i<6; ++i) {
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bd_t *binfo = (bd_t *)__res;
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hold_time[i] =
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PCMCIA_MK_CLKS (hold_time[i],
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binfo->bi_busfreq);
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ide_pio_clocks[i].setup_time =
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PCMCIA_MK_CLKS (ide_pio_timings[i].setup_time,
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binfo->bi_busfreq);
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ide_pio_clocks[i].active_time =
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PCMCIA_MK_CLKS (ide_pio_timings[i].active_time,
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binfo->bi_busfreq);
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ide_pio_clocks[i].cycle_time =
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PCMCIA_MK_CLKS (ide_pio_timings[i].cycle_time,
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binfo->bi_busfreq);
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#if 0
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printk ("PIO mode %d timings: %d/%d/%d => %d/%d/%d\n",
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i,
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ide_pio_clocks[i].setup_time,
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ide_pio_clocks[i].active_time,
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ide_pio_clocks[i].hold_time,
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ide_pio_clocks[i].cycle_time,
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ide_pio_timings[i].setup_time,
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ide_pio_timings[i].active_time,
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ide_pio_timings[i].hold_time,
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ide_pio_timings[i].cycle_time);
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#endif
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}
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}
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if (_slot_ == -1) {
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printk ("PCMCIA slot has not been defined! Using A as default\n");
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_slot_ = 0;
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}
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#ifdef CONFIG_IDE_8xx_PCCARD
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#ifdef DEBUG
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printk ("PIPR = 0x%08X slot %c ==> mask = 0x%X\n",
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pcmp->pcmc_pipr,
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'A' + _slot_,
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M8XX_PCMCIA_CD1(_slot_) | M8XX_PCMCIA_CD2(_slot_) );
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#endif /* DEBUG */
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if (pcmp->pcmc_pipr & (M8XX_PCMCIA_CD1(_slot_)|M8XX_PCMCIA_CD2(_slot_))) {
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printk ("No card in slot %c: PIPR=%08x\n",
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'A' + _slot_, (u32) pcmp->pcmc_pipr);
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2008-04-26 11:36:38 -04:00
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return -ENODEV; /* No card in slot */
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2005-04-16 18:20:36 -04:00
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}
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check_ide_device (pcmcia_base);
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#endif /* CONFIG_IDE_8xx_PCCARD */
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base = pcmcia_base + ioport_dsc[data_port].base_off;
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#ifdef DEBUG
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printk ("base: %08x + %08x = %08x\n",
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pcmcia_base, ioport_dsc[data_port].base_off, base);
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#endif
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for (i = 0; i < IDE_NR_PORTS; ++i) {
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#ifdef DEBUG
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printk ("port[%d]: %08x + %08x = %08x\n",
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i,
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base,
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ioport_dsc[data_port].reg_off[i],
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i, base + ioport_dsc[data_port].reg_off[i]);
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#endif
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*p++ = base + ioport_dsc[data_port].reg_off[i];
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}
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2008-04-17 18:46:29 -04:00
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hw->irq = ioport_dsc[data_port].irq;
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hw->ack_intr = (ide_ack_intr_t *)ide_interrupt_ack;
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2005-04-16 18:20:36 -04:00
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#ifdef CONFIG_IDE_8xx_PCCARD
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2008-04-17 18:46:29 -04:00
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{
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2005-04-16 18:20:36 -04:00
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unsigned int reg;
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if (_slot_)
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pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcrb;
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else
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pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcra;
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reg = *pgcrx;
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reg |= mk_int_int_mask (pcmcia_schlvl) << 24;
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reg |= mk_int_int_mask (pcmcia_schlvl) << 16;
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*pgcrx = reg;
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}
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2008-04-17 18:46:29 -04:00
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#endif /* CONFIG_IDE_8xx_PCCARD */
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2005-04-16 18:20:36 -04:00
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/* Enable Harddisk Interrupt,
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* and make it edge sensitive
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*/
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/* (11-18) Set edge detect for irq, no wakeup from low power mode */
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((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
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(0x80000000 >> ioport_dsc[data_port].irq);
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#ifdef CONFIG_IDE_8xx_PCCARD
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/* Make sure we don't get garbage irq */
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((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pscr = 0xFFFF;
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/* Enable falling edge irq */
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pcmp->pcmc_per = 0x100000 >> (16 * _slot_);
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#endif /* CONFIG_IDE_8xx_PCCARD */
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2008-04-26 11:36:38 -04:00
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return 0;
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2008-04-17 18:46:29 -04:00
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}
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2005-04-16 18:20:36 -04:00
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#endif /* CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT */
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/*
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2008-04-17 18:46:29 -04:00
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* m8xx_ide_init_ports() for a direct IDE interface _not_ using
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2005-04-16 18:20:36 -04:00
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* MPC8xx's internal PCMCIA interface
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*/
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#if defined(CONFIG_IDE_EXT_DIRECT)
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2008-04-26 11:36:38 -04:00
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static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
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2005-04-16 18:20:36 -04:00
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{
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unsigned long *p = hw->io_ports;
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int i;
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u32 ide_phy_base;
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u32 ide_phy_end;
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static unsigned long ide_base = 0;
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unsigned long base;
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*p = 0;
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if (!ide_base) {
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/* TODO:
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* - add code to read ORx, BRx
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*/
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ide_phy_base = CFG_ATA_BASE_ADDR;
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ide_phy_end = CFG_ATA_BASE_ADDR + 0x200;
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printk ("IDE phys mem : %08x...%08x (size %08x)\n",
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ide_phy_base, ide_phy_end,
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ide_phy_end - ide_phy_base);
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ide_base=(unsigned long)ioremap(ide_phy_base,
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ide_phy_end-ide_phy_base);
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#ifdef DEBUG
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printk ("IDE virt base: %08lx\n", ide_base);
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#endif
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}
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|
|
|
base = ide_base + ioport_dsc[data_port].base_off;
|
|
|
|
#ifdef DEBUG
|
|
|
|
printk ("base: %08x + %08x = %08x\n",
|
|
|
|
ide_base, ioport_dsc[data_port].base_off, base);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
for (i = 0; i < IDE_NR_PORTS; ++i) {
|
|
|
|
#ifdef DEBUG
|
|
|
|
printk ("port[%d]: %08x + %08x = %08x\n",
|
|
|
|
i,
|
|
|
|
base,
|
|
|
|
ioport_dsc[data_port].reg_off[i],
|
|
|
|
i, base + ioport_dsc[data_port].reg_off[i]);
|
|
|
|
#endif
|
|
|
|
*p++ = base + ioport_dsc[data_port].reg_off[i];
|
|
|
|
}
|
|
|
|
|
2008-04-17 18:46:29 -04:00
|
|
|
/* direct connected IDE drive, i.e. external IRQ */
|
|
|
|
hw->irq = ioport_dsc[data_port].irq;
|
|
|
|
hw->ack_intr = (ide_ack_intr_t *)ide_interrupt_ack;
|
2005-04-16 18:20:36 -04:00
|
|
|
|
|
|
|
/* Enable Harddisk Interrupt,
|
|
|
|
* and make it edge sensitive
|
|
|
|
*/
|
|
|
|
/* (11-18) Set edge detect for irq, no wakeup from low power mode */
|
|
|
|
((immap_t *) IMAP_ADDR)->im_siu_conf.sc_siel |=
|
|
|
|
(0x80000000 >> ioport_dsc[data_port].irq);
|
2008-04-26 11:36:38 -04:00
|
|
|
|
|
|
|
return 0;
|
2008-04-17 18:46:29 -04:00
|
|
|
}
|
2005-04-16 18:20:36 -04:00
|
|
|
#endif /* CONFIG_IDE_8xx_DIRECT */
|
|
|
|
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
|
|
|
|
/* PCMCIA Timing */
|
|
|
|
#ifndef PCMCIA_SHT
|
|
|
|
#define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
|
|
|
|
#define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
|
|
|
|
#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Calculate PIO timings */
|
2007-10-11 17:54:00 -04:00
|
|
|
static void m8xx_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
|
2005-04-16 18:20:36 -04:00
|
|
|
{
|
|
|
|
#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
|
|
|
|
volatile pcmconf8xx_t *pcmp;
|
|
|
|
ulong timing, mask, reg;
|
|
|
|
|
|
|
|
pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
|
|
|
|
|
|
|
|
mask = ~(PCMCIA_SHT(0xFF) | PCMCIA_SST(0xFF) | PCMCIA_SL(0xFF));
|
|
|
|
|
|
|
|
timing = PCMCIA_SHT(hold_time[pio] )
|
|
|
|
| PCMCIA_SST(ide_pio_clocks[pio].setup_time )
|
|
|
|
| PCMCIA_SL (ide_pio_clocks[pio].active_time)
|
|
|
|
;
|
|
|
|
|
|
|
|
#if 1
|
|
|
|
printk ("Setting timing bits 0x%08lx in PCMCIA controller\n", timing);
|
|
|
|
#endif
|
|
|
|
if ((reg = pcmp->pcmc_por0 & mask) != 0)
|
|
|
|
pcmp->pcmc_por0 = reg | timing;
|
|
|
|
|
|
|
|
if ((reg = pcmp->pcmc_por1 & mask) != 0)
|
|
|
|
pcmp->pcmc_por1 = reg | timing;
|
|
|
|
|
|
|
|
if ((reg = pcmp->pcmc_por2 & mask) != 0)
|
|
|
|
pcmp->pcmc_por2 = reg | timing;
|
|
|
|
|
|
|
|
if ((reg = pcmp->pcmc_por3 & mask) != 0)
|
|
|
|
pcmp->pcmc_por3 = reg | timing;
|
|
|
|
|
|
|
|
if ((reg = pcmp->pcmc_por4 & mask) != 0)
|
|
|
|
pcmp->pcmc_por4 = reg | timing;
|
|
|
|
|
|
|
|
if ((reg = pcmp->pcmc_por5 & mask) != 0)
|
|
|
|
pcmp->pcmc_por5 = reg | timing;
|
|
|
|
|
|
|
|
if ((reg = pcmp->pcmc_por6 & mask) != 0)
|
|
|
|
pcmp->pcmc_por6 = reg | timing;
|
|
|
|
|
|
|
|
if ((reg = pcmp->pcmc_por7 & mask) != 0)
|
|
|
|
pcmp->pcmc_por7 = reg | timing;
|
|
|
|
|
|
|
|
#elif defined(CONFIG_IDE_EXT_DIRECT)
|
|
|
|
|
|
|
|
printk("%s[%d] %s: not implemented yet!\n",
|
|
|
|
__FILE__,__LINE__,__FUNCTION__);
|
|
|
|
#endif /* defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_PCMCIA */
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
ide_interrupt_ack (void *dev)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_IDE_8xx_PCCARD
|
|
|
|
u_int pscr, pipr;
|
|
|
|
|
|
|
|
#if (PCMCIA_SOCKETS_NO == 2)
|
|
|
|
u_int _slot_;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* get interrupt sources */
|
|
|
|
|
|
|
|
pscr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr;
|
|
|
|
pipr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* report only if both card detect signals are the same
|
|
|
|
* not too nice done,
|
|
|
|
* we depend on that CD2 is the bit to the left of CD1...
|
|
|
|
*/
|
|
|
|
|
|
|
|
if(_slot_==-1){
|
|
|
|
printk("PCMCIA slot has not been defined! Using A as default\n");
|
|
|
|
_slot_=0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(((pipr & M8XX_PCMCIA_CD2(_slot_)) >> 1) ^
|
|
|
|
(pipr & M8XX_PCMCIA_CD1(_slot_)) ) {
|
|
|
|
printk ("card detect interrupt\n");
|
|
|
|
}
|
|
|
|
/* clear the interrupt sources */
|
|
|
|
((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = pscr;
|
|
|
|
|
|
|
|
#else /* ! CONFIG_IDE_8xx_PCCARD */
|
|
|
|
/*
|
|
|
|
* Only CONFIG_IDE_8xx_PCCARD is using the interrupt of the
|
|
|
|
* MPC8xx's PCMCIA controller, so there is nothing to be done here
|
|
|
|
* for CONFIG_IDE_8xx_DIRECT and CONFIG_IDE_EXT_DIRECT.
|
|
|
|
* The interrupt is handled somewhere else. -- Steven
|
|
|
|
*/
|
|
|
|
#endif /* CONFIG_IDE_8xx_PCCARD */
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CIS Tupel codes
|
|
|
|
*/
|
|
|
|
#define CISTPL_NULL 0x00
|
|
|
|
#define CISTPL_DEVICE 0x01
|
|
|
|
#define CISTPL_LONGLINK_CB 0x02
|
|
|
|
#define CISTPL_INDIRECT 0x03
|
|
|
|
#define CISTPL_CONFIG_CB 0x04
|
|
|
|
#define CISTPL_CFTABLE_ENTRY_CB 0x05
|
|
|
|
#define CISTPL_LONGLINK_MFC 0x06
|
|
|
|
#define CISTPL_BAR 0x07
|
|
|
|
#define CISTPL_PWR_MGMNT 0x08
|
|
|
|
#define CISTPL_EXTDEVICE 0x09
|
|
|
|
#define CISTPL_CHECKSUM 0x10
|
|
|
|
#define CISTPL_LONGLINK_A 0x11
|
|
|
|
#define CISTPL_LONGLINK_C 0x12
|
|
|
|
#define CISTPL_LINKTARGET 0x13
|
|
|
|
#define CISTPL_NO_LINK 0x14
|
|
|
|
#define CISTPL_VERS_1 0x15
|
|
|
|
#define CISTPL_ALTSTR 0x16
|
|
|
|
#define CISTPL_DEVICE_A 0x17
|
|
|
|
#define CISTPL_JEDEC_C 0x18
|
|
|
|
#define CISTPL_JEDEC_A 0x19
|
|
|
|
#define CISTPL_CONFIG 0x1a
|
|
|
|
#define CISTPL_CFTABLE_ENTRY 0x1b
|
|
|
|
#define CISTPL_DEVICE_OC 0x1c
|
|
|
|
#define CISTPL_DEVICE_OA 0x1d
|
|
|
|
#define CISTPL_DEVICE_GEO 0x1e
|
|
|
|
#define CISTPL_DEVICE_GEO_A 0x1f
|
|
|
|
#define CISTPL_MANFID 0x20
|
|
|
|
#define CISTPL_FUNCID 0x21
|
|
|
|
#define CISTPL_FUNCE 0x22
|
|
|
|
#define CISTPL_SWIL 0x23
|
|
|
|
#define CISTPL_END 0xff
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CIS Function ID codes
|
|
|
|
*/
|
|
|
|
#define CISTPL_FUNCID_MULTI 0x00
|
|
|
|
#define CISTPL_FUNCID_MEMORY 0x01
|
|
|
|
#define CISTPL_FUNCID_SERIAL 0x02
|
|
|
|
#define CISTPL_FUNCID_PARALLEL 0x03
|
|
|
|
#define CISTPL_FUNCID_FIXED 0x04
|
|
|
|
#define CISTPL_FUNCID_VIDEO 0x05
|
|
|
|
#define CISTPL_FUNCID_NETWORK 0x06
|
|
|
|
#define CISTPL_FUNCID_AIMS 0x07
|
|
|
|
#define CISTPL_FUNCID_SCSI 0x08
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fixed Disk FUNCE codes
|
|
|
|
*/
|
|
|
|
#define CISTPL_IDE_INTERFACE 0x01
|
|
|
|
|
|
|
|
#define CISTPL_FUNCE_IDE_IFACE 0x01
|
|
|
|
#define CISTPL_FUNCE_IDE_MASTER 0x02
|
|
|
|
#define CISTPL_FUNCE_IDE_SLAVE 0x03
|
|
|
|
|
|
|
|
/* First feature byte */
|
|
|
|
#define CISTPL_IDE_SILICON 0x04
|
|
|
|
#define CISTPL_IDE_UNIQUE 0x08
|
|
|
|
#define CISTPL_IDE_DUAL 0x10
|
|
|
|
|
|
|
|
/* Second feature byte */
|
|
|
|
#define CISTPL_IDE_HAS_SLEEP 0x01
|
|
|
|
#define CISTPL_IDE_HAS_STANDBY 0x02
|
|
|
|
#define CISTPL_IDE_HAS_IDLE 0x04
|
|
|
|
#define CISTPL_IDE_LOW_POWER 0x08
|
|
|
|
#define CISTPL_IDE_REG_INHIBIT 0x10
|
|
|
|
#define CISTPL_IDE_HAS_INDEX 0x20
|
|
|
|
#define CISTPL_IDE_IOIS16 0x40
|
|
|
|
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
|
|
|
|
#define MAX_TUPEL_SZ 512
|
|
|
|
#define MAX_FEATURES 4
|
|
|
|
|
|
|
|
static int check_ide_device (unsigned long base)
|
|
|
|
{
|
|
|
|
volatile u8 *ident = NULL;
|
|
|
|
volatile u8 *feature_p[MAX_FEATURES];
|
|
|
|
volatile u8 *p, *start;
|
|
|
|
int n_features = 0;
|
|
|
|
u8 func_id = ~0;
|
|
|
|
u8 code, len;
|
|
|
|
unsigned short config_base = 0;
|
|
|
|
int found = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
printk ("PCMCIA MEM: %08lX\n", base);
|
|
|
|
#endif
|
|
|
|
start = p = (volatile u8 *) base;
|
|
|
|
|
|
|
|
while ((p - start) < MAX_TUPEL_SZ) {
|
|
|
|
|
|
|
|
code = *p; p += 2;
|
|
|
|
|
|
|
|
if (code == 0xFF) { /* End of chain */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
len = *p; p += 2;
|
|
|
|
#ifdef DEBUG_PCMCIA
|
|
|
|
{ volatile u8 *q = p;
|
|
|
|
printk ("\nTuple code %02x length %d\n\tData:",
|
|
|
|
code, len);
|
|
|
|
|
|
|
|
for (i = 0; i < len; ++i) {
|
|
|
|
printk (" %02x", *q);
|
|
|
|
q+= 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* DEBUG_PCMCIA */
|
|
|
|
switch (code) {
|
|
|
|
case CISTPL_VERS_1:
|
|
|
|
ident = p + 4;
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID:
|
|
|
|
func_id = *p;
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCE:
|
|
|
|
if (n_features < MAX_FEATURES)
|
|
|
|
feature_p[n_features++] = p;
|
|
|
|
break;
|
|
|
|
case CISTPL_CONFIG:
|
|
|
|
config_base = (*(p+6) << 8) + (*(p+4));
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
p += 2 * len;
|
|
|
|
}
|
|
|
|
|
|
|
|
found = identify (ident);
|
|
|
|
|
|
|
|
if (func_id != ((u8)~0)) {
|
|
|
|
print_funcid (func_id);
|
|
|
|
|
|
|
|
if (func_id == CISTPL_FUNCID_FIXED)
|
|
|
|
found = 1;
|
|
|
|
else
|
|
|
|
return (1); /* no disk drive */
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i=0; i<n_features; ++i) {
|
|
|
|
print_fixed (feature_p[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!found) {
|
|
|
|
printk ("unknown card type\n");
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set level mode irq and I/O mapped device in config reg*/
|
|
|
|
*((u8 *)(base + config_base)) = 0x41;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static void print_funcid (int func)
|
|
|
|
{
|
|
|
|
switch (func) {
|
|
|
|
case CISTPL_FUNCID_MULTI:
|
|
|
|
printk (" Multi-Function");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_MEMORY:
|
|
|
|
printk (" Memory");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_SERIAL:
|
|
|
|
printk (" Serial Port");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_PARALLEL:
|
|
|
|
printk (" Parallel Port");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_FIXED:
|
|
|
|
printk (" Fixed Disk");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_VIDEO:
|
|
|
|
printk (" Video Adapter");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_NETWORK:
|
|
|
|
printk (" Network Adapter");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_AIMS:
|
|
|
|
printk (" AIMS Card");
|
|
|
|
break;
|
|
|
|
case CISTPL_FUNCID_SCSI:
|
|
|
|
printk (" SCSI Adapter");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk (" Unknown");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
printk (" Card\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
static void print_fixed (volatile u8 *p)
|
|
|
|
{
|
|
|
|
if (p == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
switch (*p) {
|
|
|
|
case CISTPL_FUNCE_IDE_IFACE:
|
|
|
|
{ u8 iface = *(p+2);
|
|
|
|
|
|
|
|
printk ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
|
|
|
|
printk (" interface ");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CISTPL_FUNCE_IDE_MASTER:
|
|
|
|
case CISTPL_FUNCE_IDE_SLAVE:
|
|
|
|
{ u8 f1 = *(p+2);
|
|
|
|
u8 f2 = *(p+4);
|
|
|
|
|
|
|
|
printk ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
|
|
|
|
|
|
|
|
if (f1 & CISTPL_IDE_UNIQUE)
|
|
|
|
printk (" [unique]");
|
|
|
|
|
|
|
|
printk ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
|
|
|
|
|
|
|
|
if (f2 & CISTPL_IDE_HAS_SLEEP)
|
|
|
|
printk (" [sleep]");
|
|
|
|
|
|
|
|
if (f2 & CISTPL_IDE_HAS_STANDBY)
|
|
|
|
printk (" [standby]");
|
|
|
|
|
|
|
|
if (f2 & CISTPL_IDE_HAS_IDLE)
|
|
|
|
printk (" [idle]");
|
|
|
|
|
|
|
|
if (f2 & CISTPL_IDE_LOW_POWER)
|
|
|
|
printk (" [low power]");
|
|
|
|
|
|
|
|
if (f2 & CISTPL_IDE_REG_INHIBIT)
|
|
|
|
printk (" [reg inhibit]");
|
|
|
|
|
|
|
|
if (f2 & CISTPL_IDE_HAS_INDEX)
|
|
|
|
printk (" [index]");
|
|
|
|
|
|
|
|
if (f2 & CISTPL_IDE_IOIS16)
|
|
|
|
printk (" [IOis16]");
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
printk ("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
|
|
|
|
#define MAX_IDENT_CHARS 64
|
|
|
|
#define MAX_IDENT_FIELDS 4
|
|
|
|
|
|
|
|
static u8 *known_cards[] = {
|
|
|
|
"ARGOSY PnPIDE D5",
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static int identify (volatile u8 *p)
|
|
|
|
{
|
|
|
|
u8 id_str[MAX_IDENT_CHARS];
|
|
|
|
u8 data;
|
|
|
|
u8 *t;
|
|
|
|
u8 **card;
|
|
|
|
int i, done;
|
|
|
|
|
|
|
|
if (p == NULL)
|
|
|
|
return (0); /* Don't know */
|
|
|
|
|
|
|
|
t = id_str;
|
|
|
|
done =0;
|
|
|
|
|
|
|
|
for (i=0; i<=4 && !done; ++i, p+=2) {
|
|
|
|
while ((data = *p) != '\0') {
|
|
|
|
if (data == 0xFF) {
|
|
|
|
done = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
*t++ = data;
|
|
|
|
if (t == &id_str[MAX_IDENT_CHARS-1]) {
|
|
|
|
done = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
p += 2;
|
|
|
|
}
|
|
|
|
if (!done)
|
|
|
|
*t++ = ' ';
|
|
|
|
}
|
|
|
|
*t = '\0';
|
|
|
|
while (--t > id_str) {
|
|
|
|
if (*t == ' ')
|
|
|
|
*t = '\0';
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
printk ("Card ID: %s\n", id_str);
|
|
|
|
|
|
|
|
for (card=known_cards; *card; ++card) {
|
|
|
|
if (strcmp(*card, id_str) == 0) { /* found! */
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0); /* don't know */
|
|
|
|
}
|
|
|
|
|
2008-01-26 14:13:07 -05:00
|
|
|
static int __init mpc8xx_ide_probe(void)
|
2008-01-26 14:13:06 -05:00
|
|
|
{
|
2008-04-17 18:46:29 -04:00
|
|
|
hw_regs_t hw;
|
2008-01-26 14:13:06 -05:00
|
|
|
u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
|
|
|
|
|
|
|
|
#ifdef IDE0_BASE_OFFSET
|
2008-04-17 18:46:29 -04:00
|
|
|
memset(&hw, 0, sizeof(hw));
|
2008-04-26 11:36:38 -04:00
|
|
|
if (!m8xx_ide_init_ports(&hw, 0)) {
|
|
|
|
ide_hwif_t *hwif = &ide_hwifs[0];
|
|
|
|
|
|
|
|
ide_init_port_hw(hwif, &hw);
|
|
|
|
hwif->pio_mask = ATA_PIO4;
|
|
|
|
hwif->set_pio_mode = m8xx_ide_set_pio_mode;
|
|
|
|
|
|
|
|
idx[0] = 0;
|
|
|
|
}
|
2008-01-26 14:13:06 -05:00
|
|
|
#ifdef IDE1_BASE_OFFSET
|
2008-04-17 18:46:29 -04:00
|
|
|
memset(&hw, 0, sizeof(hw));
|
2008-04-26 11:36:38 -04:00
|
|
|
if (!m8xx_ide_init_ports(&hw, 1)) {
|
|
|
|
ide_hwif_t *mate = &ide_hwifs[1];
|
|
|
|
|
|
|
|
ide_init_port_hw(mate, &hw);
|
|
|
|
mate->pio_mask = ATA_PIO4;
|
|
|
|
mate->set_pio_mode = m8xx_ide_set_pio_mode;
|
|
|
|
|
|
|
|
idx[1] = 1;
|
|
|
|
}
|
2008-01-26 14:13:06 -05:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2008-02-02 13:56:31 -05:00
|
|
|
ide_device_add(idx, NULL);
|
2008-01-26 14:13:07 -05:00
|
|
|
|
|
|
|
return 0;
|
2008-01-26 14:13:06 -05:00
|
|
|
}
|
2008-01-26 14:13:07 -05:00
|
|
|
|
|
|
|
module_init(mpc8xx_ide_probe);
|
2008-04-02 15:22:03 -04:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|