2019-04-02 17:23:55 -04:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DSI_PHY_H_
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#define _DSI_PHY_H_
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#include "dsi_defs.h"
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#include "dsi_clk.h"
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#include "dsi_pwr.h"
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#include "dsi_phy_hw.h"
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struct dsi_ver_spec_info {
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enum dsi_phy_version version;
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u32 lane_cfg_count;
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u32 strength_cfg_count;
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u32 regulator_cfg_count;
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u32 timing_cfg_count;
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};
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/**
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* struct dsi_phy_power_info - digital and analog power supplies for DSI PHY
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* @digital: Digital power supply for DSI PHY.
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* @phy_pwr: Analog power supplies for DSI PHY to work.
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*/
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struct dsi_phy_power_info {
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struct dsi_regulator_info digital;
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struct dsi_regulator_info phy_pwr;
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};
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/**
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* enum phy_engine_state - define engine status for dsi phy.
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* @DSI_PHY_ENGINE_OFF: Engine is turned off.
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* @DSI_PHY_ENGINE_ON: Engine is turned on.
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* @DSI_PHY_ENGINE_MAX: Maximum value.
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*/
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enum phy_engine_state {
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DSI_PHY_ENGINE_OFF = 0,
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DSI_PHY_ENGINE_ON,
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DSI_PHY_ENGINE_MAX,
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};
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/**
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* enum phy_ulps_return_type - define set_ulps return type for dsi phy.
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* @DSI_PHY_ULPS_HANDLED: ulps is handled in phy.
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* @DSI_PHY_ULPS_NOT_HANDLED: ulps is not handled in phy.
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* @DSI_PHY_ULPS_ERROR: ulps request failed in phy.
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*/
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enum phy_ulps_return_type {
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DSI_PHY_ULPS_HANDLED = 0,
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DSI_PHY_ULPS_NOT_HANDLED,
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DSI_PHY_ULPS_ERROR,
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};
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/**
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* struct msm_dsi_phy - DSI PHY object
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* @pdev: Pointer to platform device.
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* @index: Instance id.
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* @name: Name of the PHY instance.
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* @refcount: Reference count.
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* @phy_lock: Mutex for hardware and object access.
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* @ver_info: Version specific phy parameters.
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* @hw: DSI PHY hardware object.
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* @pwr_info: Power information.
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* @cfg: DSI phy configuration.
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* @clk_cb: structure containing call backs for clock control
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* @power_state: True if PHY is powered on.
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* @dsi_phy_state: PHY state information.
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* @mode: Current mode.
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* @data_lanes: Number of data lanes used.
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* @dst_format: Destination format.
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* @allow_phy_power_off: True if PHY is allowed to power off when idle
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* @regulator_min_datarate_bps: Minimum per lane data rate to turn on regulator
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* @regulator_required: True if phy regulator is required
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*/
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struct msm_dsi_phy {
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struct platform_device *pdev;
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int index;
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const char *name;
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u32 refcount;
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struct mutex phy_lock;
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const struct dsi_ver_spec_info *ver_info;
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struct dsi_phy_hw hw;
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struct dsi_phy_power_info pwr_info;
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struct dsi_phy_cfg cfg;
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struct clk_ctrl_cb clk_cb;
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enum phy_engine_state dsi_phy_state;
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bool power_state;
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struct dsi_mode_info mode;
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enum dsi_data_lanes data_lanes;
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enum dsi_pixel_format dst_format;
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bool allow_phy_power_off;
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u32 regulator_min_datarate_bps;
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bool regulator_required;
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};
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/**
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* dsi_phy_get() - get a dsi phy handle from device node
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* @of_node: device node for dsi phy controller
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*
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* Gets the DSI PHY handle for the corresponding of_node. The ref count is
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* incremented to one all subsequents get will fail until the original client
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* calls a put.
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*
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* Return: DSI PHY handle or an error code.
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*/
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struct msm_dsi_phy *dsi_phy_get(struct device_node *of_node);
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/**
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* dsi_phy_put() - release dsi phy handle
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* @dsi_phy: DSI PHY handle.
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*
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* Release the DSI PHY hardware. Driver will clean up all resources and puts
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* back the DSI PHY into reset state.
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*/
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void dsi_phy_put(struct msm_dsi_phy *dsi_phy);
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/**
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* dsi_phy_drv_init() - initialize dsi phy driver
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* @dsi_phy: DSI PHY handle.
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*
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* Initializes DSI PHY driver. Should be called after dsi_phy_get().
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*
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* Return: error code.
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*/
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int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy);
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/**
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* dsi_phy_drv_deinit() - de-initialize dsi phy driver
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* @dsi_phy: DSI PHY handle.
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*
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* Release all resources acquired by dsi_phy_drv_init().
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*
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* Return: error code.
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*/
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int dsi_phy_drv_deinit(struct msm_dsi_phy *dsi_phy);
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/**
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* dsi_phy_validate_mode() - validate a display mode
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* @dsi_phy: DSI PHY handle.
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* @mode: Mode information.
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*
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* Validation will fail if the mode cannot be supported by the PHY driver or
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* hardware.
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*
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* Return: error code.
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*/
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int dsi_phy_validate_mode(struct msm_dsi_phy *dsi_phy,
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struct dsi_mode_info *mode);
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/**
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* dsi_phy_set_power_state() - enable/disable dsi phy power supplies
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* @dsi_phy: DSI PHY handle.
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* @enable: Boolean flag to enable/disable.
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*
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* Return: error code.
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*/
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int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable);
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/**
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* dsi_phy_enable() - enable DSI PHY hardware
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* @dsi_phy: DSI PHY handle.
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* @config: DSI host configuration.
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* @pll_source: Source PLL for PHY clock.
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* @skip_validation: Validation will not be performed on parameters.
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* @is_cont_splash_enabled: check whether continuous splash enabled.
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*
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* Validates and enables DSI PHY.
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*
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* Return: error code.
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*/
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int dsi_phy_enable(struct msm_dsi_phy *dsi_phy,
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struct dsi_host_config *config,
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enum dsi_phy_pll_source pll_source,
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bool skip_validation,
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bool is_cont_splash_enabled);
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/**
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* dsi_phy_disable() - disable DSI PHY hardware.
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* @phy: DSI PHY handle.
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*
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* Return: error code.
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*/
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int dsi_phy_disable(struct msm_dsi_phy *phy);
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/**
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* dsi_phy_set_ulps() - set ulps state for DSI pHY
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* @phy: DSI PHY handle
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* @config: DSi host configuration information.
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* @enable: Enable/Disable
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* @clamp_enabled: mmss_clamp enabled/disabled
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*
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* Return: error code.
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*/
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int dsi_phy_set_ulps(struct msm_dsi_phy *phy, struct dsi_host_config *config,
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bool enable, bool clamp_enabled);
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/**
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* dsi_phy_clk_cb_register() - Register PHY clock control callback
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* @phy: DSI PHY handle
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* @clk_cb: Structure containing call back for clock control
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*
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* Return: error code.
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*/
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int dsi_phy_clk_cb_register(struct msm_dsi_phy *phy,
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struct clk_ctrl_cb *clk_cb);
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/**
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* dsi_phy_idle_ctrl() - enable/disable DSI PHY during idle screen
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* @phy: DSI PHY handle
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* @enable: boolean to specify PHY enable/disable.
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*
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* Return: error code.
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*/
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int dsi_phy_idle_ctrl(struct msm_dsi_phy *phy, bool enable);
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/**
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* dsi_phy_set_clamp_state() - configure clamps for DSI lanes
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* @phy: DSI PHY handle.
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* @enable: boolean to specify clamp enable/disable.
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*
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* Return: error code.
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*/
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int dsi_phy_set_clamp_state(struct msm_dsi_phy *phy, bool enable);
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/**
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* dsi_phy_set_clk_freq() - set DSI PHY clock frequency setting
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* @phy: DSI PHY handle
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* @clk_freq: link clock frequency
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*
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* Return: error code.
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*/
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int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
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struct link_clk_freq *clk_freq);
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/**
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* dsi_phy_set_timing_params() - timing parameters for the panel
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* @phy: DSI PHY handle
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* @timing: array holding timing params.
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* @size: size of the array.
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*
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* When PHY timing calculator is not implemented, this array will be used to
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* pass PHY timing information.
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*
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* Return: error code.
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*/
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int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
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u32 *timing, u32 size);
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/**
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* dsi_phy_lane_reset() - Reset DSI PHY lanes in case of error
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* @phy: DSI PHY handle
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*
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* Return: error code.
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*/
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int dsi_phy_lane_reset(struct msm_dsi_phy *phy);
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/**
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* dsi_phy_toggle_resync_fifo() - toggle resync retime FIFO
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* @phy: DSI PHY handle
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*
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* Toggle the resync retime FIFO to synchronize the data paths.
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* This should be done everytime there is a change in the link clock
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* rate
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*/
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void dsi_phy_toggle_resync_fifo(struct msm_dsi_phy *phy);
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/**
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* dsi_phy_reset_clk_en_sel() - reset clk_en_select on cmn_clk_cfg1 register
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* @phy: DSI PHY handle
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*
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* After toggling resync fifo regiater, clk_en_sel bit on cmn_clk_cfg1
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* register has to be reset
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*/
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void dsi_phy_reset_clk_en_sel(struct msm_dsi_phy *phy);
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/**
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* dsi_phy_drv_register() - register platform driver for dsi phy
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*/
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void dsi_phy_drv_register(void);
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/**
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* dsi_phy_drv_unregister() - unregister platform driver
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*/
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void dsi_phy_drv_unregister(void);
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2018-10-25 06:19:16 -04:00
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/**
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* dsi_phy_update_phy_timings() - Update dsi phy timings
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* @phy: DSI PHY handle
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* @config: DSI Host config parameters
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*
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* Return: error code.
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*/
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int dsi_phy_update_phy_timings(struct msm_dsi_phy *phy,
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struct dsi_host_config *config);
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/**
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* dsi_phy_config_dynamic_refresh() - Configure dynamic refresh registers
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* @phy: DSI PHY handle
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* @delay: pipe delays for dynamic refresh
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* @is_master: Boolean to indicate if for master or slave
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*/
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void dsi_phy_config_dynamic_refresh(struct msm_dsi_phy *phy,
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struct dsi_dyn_clk_delay *delay,
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bool is_master);
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/**
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* dsi_phy_dynamic_refresh_trigger() - trigger dynamic refresh
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* @phy: DSI PHY handle
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* @is_master: Boolean to indicate if for master or slave.
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*/
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void dsi_phy_dynamic_refresh_trigger(struct msm_dsi_phy *phy, bool is_master);
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/**
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* dsi_phy_dynamic_refresh_clear() - clear dynamic refresh config
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* @phy: DSI PHY handle
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*/
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void dsi_phy_dynamic_refresh_clear(struct msm_dsi_phy *phy);
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/**
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* dsi_phy_dyn_refresh_cache_phy_timings - cache the phy timings calculated
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* as part of dynamic refresh.
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* @phy: DSI PHY Handle.
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* @dst: Pointer to cache location.
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* @size: Number of phy lane settings.
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*/
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int dsi_phy_dyn_refresh_cache_phy_timings(struct msm_dsi_phy *phy,
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2019-05-23 12:48:41 -04:00
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u32 *dst, u32 size);
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/**
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* dsi_phy_set_continuous_clk() - API to set/unset force clock lane HS request.
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* @phy: DSI PHY Handle.
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* @enable: variable to control continuous clock.
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*/
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void dsi_phy_set_continuous_clk(struct msm_dsi_phy *phy, bool enable);
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2019-04-02 17:23:55 -04:00
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#endif /* _DSI_PHY_H_ */
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