2007-05-08 21:00:38 -04:00
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/*
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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2007-05-15 15:36:30 -04:00
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#include <linux/dma-mapping.h>
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2007-05-08 21:00:38 -04:00
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#include <linux/mlx4/cmd.h>
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#include "mlx4.h"
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#include "fw.h"
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enum {
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MLX4_NUM_ASYNC_EQE = 0x100,
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MLX4_NUM_SPARE_EQE = 0x80,
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MLX4_EQ_ENTRY_SIZE = 0x20
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};
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/*
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* Must be packed because start is 64 bits but only aligned to 32 bits.
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*/
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struct mlx4_eq_context {
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__be32 flags;
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u16 reserved1[3];
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__be16 page_offset;
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u8 log_eq_size;
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u8 reserved2[4];
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u8 eq_period;
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u8 reserved3;
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u8 eq_max_count;
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u8 reserved4[3];
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u8 intr;
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u8 log_page_size;
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u8 reserved5[2];
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u8 mtt_base_addr_h;
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__be32 mtt_base_addr_l;
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u32 reserved6[2];
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__be32 consumer_index;
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__be32 producer_index;
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u32 reserved7[4];
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};
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#define MLX4_EQ_STATUS_OK ( 0 << 28)
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#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
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#define MLX4_EQ_OWNER_SW ( 0 << 24)
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#define MLX4_EQ_OWNER_HW ( 1 << 24)
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#define MLX4_EQ_FLAG_EC ( 1 << 18)
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#define MLX4_EQ_FLAG_OI ( 1 << 17)
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#define MLX4_EQ_STATE_ARMED ( 9 << 8)
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#define MLX4_EQ_STATE_FIRED (10 << 8)
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#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
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#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
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(1ull << MLX4_EVENT_TYPE_COMM_EST) | \
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(1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
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(1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
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(1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
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(1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
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(1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
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(1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
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(1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
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(1ull << MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR) | \
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(1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
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(1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
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(1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
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(1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
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(1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
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(1ull << MLX4_EVENT_TYPE_CMD))
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#define MLX4_CATAS_EVENT_MASK (1ull << MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR)
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struct mlx4_eqe {
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u8 reserved1;
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u8 type;
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u8 reserved2;
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u8 subtype;
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union {
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u32 raw[6];
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struct {
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__be32 cqn;
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} __attribute__((packed)) comp;
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struct {
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u16 reserved1;
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__be16 token;
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u32 reserved2;
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u8 reserved3[3];
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u8 status;
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__be64 out_param;
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} __attribute__((packed)) cmd;
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struct {
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__be32 qpn;
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} __attribute__((packed)) qp;
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struct {
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__be32 srqn;
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} __attribute__((packed)) srq;
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struct {
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__be32 cqn;
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u32 reserved1;
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u8 reserved2[3];
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u8 syndrome;
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} __attribute__((packed)) cq_err;
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struct {
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u32 reserved1[2];
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__be32 port;
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} __attribute__((packed)) port_change;
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} event;
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u8 reserved3[3];
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u8 owner;
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} __attribute__((packed));
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static void eq_set_ci(struct mlx4_eq *eq, int req_not)
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{
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__raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
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req_not << 31),
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eq->doorbell);
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/* We still want ordering, just not swabbing, so add a barrier */
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mb();
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}
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static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
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{
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unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
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return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
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}
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static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
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{
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struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
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return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
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}
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static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
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{
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struct mlx4_eqe *eqe;
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int cqn;
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int eqes_found = 0;
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int set_ci = 0;
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while ((eqe = next_eqe_sw(eq))) {
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/*
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* Make sure we read EQ entry contents after we've
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* checked the ownership bit.
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*/
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rmb();
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switch (eqe->type) {
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case MLX4_EVENT_TYPE_COMP:
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cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
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mlx4_cq_completion(dev, cqn);
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break;
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case MLX4_EVENT_TYPE_PATH_MIG:
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case MLX4_EVENT_TYPE_COMM_EST:
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case MLX4_EVENT_TYPE_SQ_DRAINED:
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case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
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case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
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case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
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case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
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case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
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mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
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eqe->type);
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break;
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case MLX4_EVENT_TYPE_SRQ_LIMIT:
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case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
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mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
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eqe->type);
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break;
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case MLX4_EVENT_TYPE_CMD:
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mlx4_cmd_event(dev,
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be16_to_cpu(eqe->event.cmd.token),
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eqe->event.cmd.status,
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be64_to_cpu(eqe->event.cmd.out_param));
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break;
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case MLX4_EVENT_TYPE_PORT_CHANGE:
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mlx4_dispatch_event(dev, eqe->type, eqe->subtype,
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be32_to_cpu(eqe->event.port_change.port) >> 28);
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break;
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case MLX4_EVENT_TYPE_CQ_ERROR:
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mlx4_warn(dev, "CQ %s on CQN %06x\n",
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eqe->event.cq_err.syndrome == 1 ?
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"overrun" : "access violation",
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be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
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mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
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eqe->type);
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break;
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case MLX4_EVENT_TYPE_EQ_OVERFLOW:
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mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
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break;
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case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
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case MLX4_EVENT_TYPE_ECC_DETECT:
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default:
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mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
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eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
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break;
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};
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++eq->cons_index;
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eqes_found = 1;
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++set_ci;
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/*
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* The HCA will think the queue has overflowed if we
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* don't tell it we've been processing events. We
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* create our EQs with MLX4_NUM_SPARE_EQE extra
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* entries, so we must update our consumer index at
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* least that often.
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*/
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if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
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/*
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* Conditional on hca_type is OK here because
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* this is a rare case, not the fast path.
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*/
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eq_set_ci(eq, 0);
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set_ci = 0;
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}
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}
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eq_set_ci(eq, 1);
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return eqes_found;
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}
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static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
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{
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struct mlx4_dev *dev = dev_ptr;
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struct mlx4_priv *priv = mlx4_priv(dev);
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int work = 0;
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int i;
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writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
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for (i = 0; i < MLX4_EQ_CATAS; ++i)
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work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
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return IRQ_RETVAL(work);
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}
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static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
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{
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struct mlx4_eq *eq = eq_ptr;
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struct mlx4_dev *dev = eq->dev;
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mlx4_eq_int(dev, eq);
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/* MSI-X vectors always belong to us */
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return IRQ_HANDLED;
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}
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static irqreturn_t mlx4_catas_interrupt(int irq, void *dev_ptr)
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{
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mlx4_handle_catas_err(dev_ptr);
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/* MSI-X vectors always belong to us */
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return IRQ_HANDLED;
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}
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static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
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int eq_num)
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{
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return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
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0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
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}
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static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int eq_num)
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{
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return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
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MLX4_CMD_TIME_CLASS_A);
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}
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static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int eq_num)
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{
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return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
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MLX4_CMD_TIME_CLASS_A);
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}
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static void __devinit __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev,
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struct mlx4_eq *eq)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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int index;
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index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
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if (!priv->eq_table.uar_map[index]) {
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priv->eq_table.uar_map[index] =
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ioremap(pci_resource_start(dev->pdev, 2) +
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((eq->eqn / 4) << PAGE_SHIFT),
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PAGE_SIZE);
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if (!priv->eq_table.uar_map[index]) {
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mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
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eq->eqn);
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return NULL;
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}
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}
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return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
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}
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static int __devinit mlx4_create_eq(struct mlx4_dev *dev, int nent,
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u8 intr, struct mlx4_eq *eq)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_eq_context *eq_context;
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int npages;
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u64 *dma_list = NULL;
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dma_addr_t t;
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u64 mtt_addr;
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int err = -ENOMEM;
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int i;
|
|
|
|
|
|
|
|
eq->dev = dev;
|
|
|
|
eq->nent = roundup_pow_of_two(max(nent, 2));
|
|
|
|
npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
|
|
|
|
|
|
|
|
eq->page_list = kmalloc(npages * sizeof *eq->page_list,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!eq->page_list)
|
|
|
|
goto err_out;
|
|
|
|
|
|
|
|
for (i = 0; i < npages; ++i)
|
|
|
|
eq->page_list[i].buf = NULL;
|
|
|
|
|
|
|
|
dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
|
|
|
|
if (!dma_list)
|
|
|
|
goto err_out_free;
|
|
|
|
|
|
|
|
mailbox = mlx4_alloc_cmd_mailbox(dev);
|
|
|
|
if (IS_ERR(mailbox))
|
|
|
|
goto err_out_free;
|
|
|
|
eq_context = mailbox->buf;
|
|
|
|
|
|
|
|
for (i = 0; i < npages; ++i) {
|
|
|
|
eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
|
|
|
|
PAGE_SIZE, &t, GFP_KERNEL);
|
|
|
|
if (!eq->page_list[i].buf)
|
|
|
|
goto err_out_free_pages;
|
|
|
|
|
|
|
|
dma_list[i] = t;
|
|
|
|
eq->page_list[i].map = t;
|
|
|
|
|
|
|
|
memset(eq->page_list[i].buf, 0, PAGE_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
|
|
|
|
if (eq->eqn == -1)
|
|
|
|
goto err_out_free_pages;
|
|
|
|
|
|
|
|
eq->doorbell = mlx4_get_eq_uar(dev, eq);
|
|
|
|
if (!eq->doorbell) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto err_out_free_eq;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
|
|
|
|
if (err)
|
|
|
|
goto err_out_free_eq;
|
|
|
|
|
|
|
|
err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
|
|
|
|
if (err)
|
|
|
|
goto err_out_free_mtt;
|
|
|
|
|
|
|
|
memset(eq_context, 0, sizeof *eq_context);
|
|
|
|
eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
|
|
|
|
MLX4_EQ_STATE_ARMED);
|
|
|
|
eq_context->log_eq_size = ilog2(eq->nent);
|
|
|
|
eq_context->intr = intr;
|
|
|
|
eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
|
|
|
|
|
|
|
|
mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
|
|
|
|
eq_context->mtt_base_addr_h = mtt_addr >> 32;
|
|
|
|
eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
|
|
|
|
|
|
|
|
err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
|
|
|
|
if (err) {
|
|
|
|
mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
|
|
|
|
goto err_out_free_mtt;
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(dma_list);
|
|
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
|
|
|
|
|
|
eq->cons_index = 0;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err_out_free_mtt:
|
|
|
|
mlx4_mtt_cleanup(dev, &eq->mtt);
|
|
|
|
|
|
|
|
err_out_free_eq:
|
|
|
|
mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
|
|
|
|
|
|
|
|
err_out_free_pages:
|
|
|
|
for (i = 0; i < npages; ++i)
|
|
|
|
if (eq->page_list[i].buf)
|
|
|
|
dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
|
|
|
|
eq->page_list[i].buf,
|
|
|
|
eq->page_list[i].map);
|
|
|
|
|
|
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
|
|
|
|
|
|
err_out_free:
|
|
|
|
kfree(eq->page_list);
|
|
|
|
kfree(dma_list);
|
|
|
|
|
|
|
|
err_out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mlx4_free_eq(struct mlx4_dev *dev,
|
|
|
|
struct mlx4_eq *eq)
|
|
|
|
{
|
|
|
|
struct mlx4_priv *priv = mlx4_priv(dev);
|
|
|
|
struct mlx4_cmd_mailbox *mailbox;
|
|
|
|
int err;
|
|
|
|
int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
mailbox = mlx4_alloc_cmd_mailbox(dev);
|
|
|
|
if (IS_ERR(mailbox))
|
|
|
|
return;
|
|
|
|
|
|
|
|
err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
|
|
|
|
if (err)
|
|
|
|
mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
|
|
|
|
|
|
|
|
if (0) {
|
|
|
|
mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
|
|
|
|
for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
|
|
|
|
if (i % 4 == 0)
|
|
|
|
printk("[%02x] ", i * 4);
|
|
|
|
printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
|
|
|
|
if ((i + 1) % 4 == 0)
|
|
|
|
printk("\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mlx4_mtt_cleanup(dev, &eq->mtt);
|
|
|
|
for (i = 0; i < npages; ++i)
|
|
|
|
pci_free_consistent(dev->pdev, PAGE_SIZE,
|
|
|
|
eq->page_list[i].buf,
|
|
|
|
eq->page_list[i].map);
|
|
|
|
|
|
|
|
kfree(eq->page_list);
|
|
|
|
mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
|
|
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mlx4_free_irqs(struct mlx4_dev *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (eq_table->have_irq)
|
|
|
|
free_irq(dev->pdev->irq, dev);
|
2007-06-02 10:16:02 -04:00
|
|
|
for (i = 0; i < MLX4_EQ_CATAS; ++i)
|
2007-05-08 21:00:38 -04:00
|
|
|
if (eq_table->eq[i].have_irq)
|
|
|
|
free_irq(eq_table->eq[i].irq, eq_table->eq + i);
|
2007-06-02 10:16:02 -04:00
|
|
|
if (eq_table->eq[MLX4_EQ_CATAS].have_irq)
|
|
|
|
free_irq(eq_table->eq[MLX4_EQ_CATAS].irq, dev);
|
2007-05-08 21:00:38 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
static int __devinit mlx4_map_clr_int(struct mlx4_dev *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_priv *priv = mlx4_priv(dev);
|
|
|
|
|
|
|
|
priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
|
|
|
|
priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
|
|
|
|
if (!priv->clr_base) {
|
|
|
|
mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_priv *priv = mlx4_priv(dev);
|
|
|
|
|
|
|
|
iounmap(priv->clr_base);
|
|
|
|
}
|
|
|
|
|
|
|
|
int __devinit mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt)
|
|
|
|
{
|
|
|
|
struct mlx4_priv *priv = mlx4_priv(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We assume that mapping one page is enough for the whole EQ
|
|
|
|
* context table. This is fine with all current HCAs, because
|
|
|
|
* we only use 32 EQs and each EQ uses 64 bytes of context
|
|
|
|
* memory, or 1 KB total.
|
|
|
|
*/
|
|
|
|
priv->eq_table.icm_virt = icm_virt;
|
|
|
|
priv->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
|
|
|
|
if (!priv->eq_table.icm_page)
|
|
|
|
return -ENOMEM;
|
|
|
|
priv->eq_table.icm_dma = pci_map_page(dev->pdev, priv->eq_table.icm_page, 0,
|
|
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
|
|
if (pci_dma_mapping_error(priv->eq_table.icm_dma)) {
|
|
|
|
__free_page(priv->eq_table.icm_page);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = mlx4_MAP_ICM_page(dev, priv->eq_table.icm_dma, icm_virt);
|
|
|
|
if (ret) {
|
|
|
|
pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
|
|
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
|
|
__free_page(priv->eq_table.icm_page);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void mlx4_unmap_eq_icm(struct mlx4_dev *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_priv *priv = mlx4_priv(dev);
|
|
|
|
|
|
|
|
mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, 1);
|
|
|
|
pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
|
|
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
|
|
__free_page(priv->eq_table.icm_page);
|
|
|
|
}
|
|
|
|
|
|
|
|
int __devinit mlx4_init_eq_table(struct mlx4_dev *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_priv *priv = mlx4_priv(dev);
|
|
|
|
int err;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
|
|
|
|
dev->caps.num_eqs - 1, dev->caps.reserved_eqs);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(priv->eq_table.uar_map); ++i)
|
|
|
|
priv->eq_table.uar_map[i] = NULL;
|
|
|
|
|
|
|
|
err = mlx4_map_clr_int(dev);
|
|
|
|
if (err)
|
|
|
|
goto err_out_free;
|
|
|
|
|
|
|
|
priv->eq_table.clr_mask =
|
|
|
|
swab32(1 << (priv->eq_table.inta_pin & 31));
|
|
|
|
priv->eq_table.clr_int = priv->clr_base +
|
|
|
|
(priv->eq_table.inta_pin < 32 ? 4 : 0);
|
|
|
|
|
|
|
|
err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
|
|
|
|
(dev->flags & MLX4_FLAG_MSI_X) ? MLX4_EQ_COMP : 0,
|
|
|
|
&priv->eq_table.eq[MLX4_EQ_COMP]);
|
|
|
|
if (err)
|
|
|
|
goto err_out_unmap;
|
|
|
|
|
|
|
|
err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
|
|
|
|
(dev->flags & MLX4_FLAG_MSI_X) ? MLX4_EQ_ASYNC : 0,
|
|
|
|
&priv->eq_table.eq[MLX4_EQ_ASYNC]);
|
|
|
|
if (err)
|
|
|
|
goto err_out_comp;
|
|
|
|
|
|
|
|
if (dev->flags & MLX4_FLAG_MSI_X) {
|
|
|
|
static const char *eq_name[] = {
|
|
|
|
[MLX4_EQ_COMP] = DRV_NAME " (comp)",
|
|
|
|
[MLX4_EQ_ASYNC] = DRV_NAME " (async)",
|
|
|
|
[MLX4_EQ_CATAS] = DRV_NAME " (catas)"
|
|
|
|
};
|
|
|
|
|
|
|
|
err = mlx4_create_eq(dev, 1, MLX4_EQ_CATAS,
|
|
|
|
&priv->eq_table.eq[MLX4_EQ_CATAS]);
|
|
|
|
if (err)
|
|
|
|
goto err_out_async;
|
|
|
|
|
|
|
|
for (i = 0; i < MLX4_EQ_CATAS; ++i) {
|
|
|
|
err = request_irq(priv->eq_table.eq[i].irq,
|
|
|
|
mlx4_msi_x_interrupt,
|
|
|
|
0, eq_name[i], priv->eq_table.eq + i);
|
|
|
|
if (err)
|
|
|
|
goto err_out_catas;
|
|
|
|
|
|
|
|
priv->eq_table.eq[i].have_irq = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = request_irq(priv->eq_table.eq[MLX4_EQ_CATAS].irq,
|
|
|
|
mlx4_catas_interrupt, 0,
|
|
|
|
eq_name[MLX4_EQ_CATAS], dev);
|
|
|
|
if (err)
|
|
|
|
goto err_out_catas;
|
|
|
|
|
|
|
|
priv->eq_table.eq[MLX4_EQ_CATAS].have_irq = 1;
|
|
|
|
} else {
|
|
|
|
err = request_irq(dev->pdev->irq, mlx4_interrupt,
|
2007-05-11 01:53:01 -04:00
|
|
|
IRQF_SHARED, DRV_NAME, dev);
|
2007-05-08 21:00:38 -04:00
|
|
|
if (err)
|
|
|
|
goto err_out_async;
|
|
|
|
|
|
|
|
priv->eq_table.have_irq = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
|
|
|
|
priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
|
|
|
|
if (err)
|
|
|
|
mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
|
|
|
|
priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err);
|
|
|
|
|
|
|
|
for (i = 0; i < MLX4_EQ_CATAS; ++i)
|
|
|
|
eq_set_ci(&priv->eq_table.eq[i], 1);
|
|
|
|
|
|
|
|
if (dev->flags & MLX4_FLAG_MSI_X) {
|
|
|
|
err = mlx4_MAP_EQ(dev, MLX4_CATAS_EVENT_MASK, 0,
|
|
|
|
priv->eq_table.eq[MLX4_EQ_CATAS].eqn);
|
|
|
|
if (err)
|
|
|
|
mlx4_warn(dev, "MAP_EQ for catas EQ %d failed (%d)\n",
|
|
|
|
priv->eq_table.eq[MLX4_EQ_CATAS].eqn, err);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out_catas:
|
|
|
|
mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_CATAS]);
|
|
|
|
|
|
|
|
err_out_async:
|
|
|
|
mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_ASYNC]);
|
|
|
|
|
|
|
|
err_out_comp:
|
|
|
|
mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_COMP]);
|
|
|
|
|
|
|
|
err_out_unmap:
|
|
|
|
mlx4_unmap_clr_int(dev);
|
|
|
|
mlx4_free_irqs(dev);
|
|
|
|
|
|
|
|
err_out_free:
|
|
|
|
mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_priv *priv = mlx4_priv(dev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (dev->flags & MLX4_FLAG_MSI_X)
|
|
|
|
mlx4_MAP_EQ(dev, MLX4_CATAS_EVENT_MASK, 1,
|
|
|
|
priv->eq_table.eq[MLX4_EQ_CATAS].eqn);
|
|
|
|
|
|
|
|
mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
|
|
|
|
priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
|
|
|
|
|
|
|
|
mlx4_free_irqs(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < MLX4_EQ_CATAS; ++i)
|
|
|
|
mlx4_free_eq(dev, &priv->eq_table.eq[i]);
|
|
|
|
if (dev->flags & MLX4_FLAG_MSI_X)
|
|
|
|
mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_CATAS]);
|
|
|
|
|
|
|
|
mlx4_unmap_clr_int(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(priv->eq_table.uar_map); ++i)
|
|
|
|
if (priv->eq_table.uar_map[i])
|
|
|
|
iounmap(priv->eq_table.uar_map[i]);
|
|
|
|
|
|
|
|
mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
|
|
|
|
}
|