2005-04-16 18:20:36 -04:00
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/* $Id: pci_common.c,v 1.29 2002/02/01 00:56:03 davem Exp $
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* pci_common.c: PCI controller common support.
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*
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*/
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <asm/pbm.h>
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2006-06-22 19:18:54 -04:00
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#include <asm/prom.h>
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2006-06-29 18:07:37 -04:00
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#include <asm/of_device.h>
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2006-06-22 19:18:54 -04:00
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#include "pci_impl.h"
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2005-04-16 18:20:36 -04:00
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/* Fix self device of BUS and hook it into BUS->self.
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* The pci_scan_bus does not do this for the host bridge.
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*/
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void __init pci_fixup_host_bridge_self(struct pci_bus *pbus)
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{
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struct pci_dev *pdev;
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list_for_each_entry(pdev, &pbus->devices, bus_list) {
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if (pdev->class >> 8 == PCI_CLASS_BRIDGE_HOST) {
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pbus->self = pdev;
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return;
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}
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}
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prom_printf("PCI: Critical error, cannot find host bridge PDEV.\n");
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prom_halt();
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}
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2006-06-22 19:18:54 -04:00
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/* Find the OBP PROM device tree node for a PCI device. */
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static struct device_node * __init
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find_device_prom_node(struct pci_pbm_info *pbm, struct pci_dev *pdev,
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struct device_node *bus_node,
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struct linux_prom_pci_registers **pregs,
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int *nregs)
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2005-04-16 18:20:36 -04:00
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{
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2006-06-22 19:18:54 -04:00
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struct device_node *dp;
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2005-04-16 18:20:36 -04:00
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2006-02-14 19:44:39 -05:00
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*nregs = 0;
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2005-04-16 18:20:36 -04:00
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/*
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* Return the PBM's PROM node in case we are it's PCI device,
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* as the PBM's reg property is different to standard PCI reg
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* properties. We would delete this device entry otherwise,
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* which confuses XFree86's device probing...
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*/
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if ((pdev->bus->number == pbm->pci_bus->number) && (pdev->devfn == 0) &&
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(pdev->vendor == PCI_VENDOR_ID_SUN) &&
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(pdev->device == PCI_DEVICE_ID_SUN_PBM ||
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pdev->device == PCI_DEVICE_ID_SUN_SCHIZO ||
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pdev->device == PCI_DEVICE_ID_SUN_TOMATILLO ||
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pdev->device == PCI_DEVICE_ID_SUN_SABRE ||
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2006-02-14 19:44:39 -05:00
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pdev->device == PCI_DEVICE_ID_SUN_HUMMINGBIRD))
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2006-06-22 19:18:54 -04:00
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return bus_node;
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dp = bus_node->child;
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while (dp) {
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struct linux_prom_pci_registers *regs;
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struct property *prop;
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int len;
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prop = of_find_property(dp, "reg", &len);
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if (!prop)
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2005-04-16 18:20:36 -04:00
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goto do_next_sibling;
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2006-06-22 19:18:54 -04:00
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regs = prop->value;
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if (((regs[0].phys_hi >> 8) & 0xff) == pdev->devfn) {
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*pregs = regs;
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*nregs = len / sizeof(struct linux_prom_pci_registers);
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return dp;
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2005-04-16 18:20:36 -04:00
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}
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do_next_sibling:
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2006-06-22 19:18:54 -04:00
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dp = dp->sibling;
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2005-04-16 18:20:36 -04:00
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}
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2006-06-22 19:18:54 -04:00
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return NULL;
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2005-04-16 18:20:36 -04:00
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}
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/* Older versions of OBP on PCI systems encode 64-bit MEM
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* space assignments incorrectly, this fixes them up. We also
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* take the opportunity here to hide other kinds of bogus
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* assignments.
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*/
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static void __init fixup_obp_assignments(struct pci_dev *pdev,
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struct pcidev_cookie *pcp)
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{
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int i;
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if (pdev->vendor == PCI_VENDOR_ID_AL &&
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(pdev->device == PCI_DEVICE_ID_AL_M7101 ||
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pdev->device == PCI_DEVICE_ID_AL_M1533)) {
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int i;
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/* Zap all of the normal resources, they are
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* meaningless and generate bogus resource collision
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* messages. This is OpenBoot's ill-fated attempt to
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* represent the implicit resources that these devices
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* have.
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*/
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pcp->num_prom_assignments = 0;
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for (i = 0; i < 6; i++) {
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pdev->resource[i].start =
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pdev->resource[i].end =
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pdev->resource[i].flags = 0;
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}
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pdev->resource[PCI_ROM_RESOURCE].start =
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pdev->resource[PCI_ROM_RESOURCE].end =
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pdev->resource[PCI_ROM_RESOURCE].flags = 0;
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return;
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}
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for (i = 0; i < pcp->num_prom_assignments; i++) {
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struct linux_prom_pci_registers *ap;
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int space;
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ap = &pcp->prom_assignments[i];
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space = ap->phys_hi >> 24;
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if ((space & 0x3) == 2 &&
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(space & 0x4) != 0) {
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ap->phys_hi &= ~(0x7 << 24);
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ap->phys_hi |= 0x3 << 24;
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}
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}
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}
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/* Fill in the PCI device cookie sysdata for the given
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* PCI device. This cookie is the means by which one
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* can get to OBP and PCI controller specific information
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* for a PCI device.
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*/
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static void __init pdev_cookie_fillin(struct pci_pbm_info *pbm,
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struct pci_dev *pdev,
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2006-06-22 19:18:54 -04:00
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struct device_node *bus_node)
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2005-04-16 18:20:36 -04:00
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{
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2006-06-22 19:18:54 -04:00
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struct linux_prom_pci_registers *pregs = NULL;
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2005-04-16 18:20:36 -04:00
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struct pcidev_cookie *pcp;
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2006-06-22 19:18:54 -04:00
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struct device_node *dp;
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struct property *prop;
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int nregs, len;
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2005-04-16 18:20:36 -04:00
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2006-06-22 19:18:54 -04:00
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dp = find_device_prom_node(pbm, pdev, bus_node,
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&pregs, &nregs);
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if (!dp) {
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2005-04-16 18:20:36 -04:00
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/* If it is not in the OBP device tree then
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* there must be a damn good reason for it.
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*
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* So what we do is delete the device from the
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* PCI device tree completely. This scenario
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* is seen, for example, on CP1500 for the
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* second EBUS/HappyMeal pair if the external
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* connector for it is not present.
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*/
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pci_remove_bus_device(pdev);
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return;
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}
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2006-06-22 19:18:54 -04:00
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pcp = kzalloc(sizeof(*pcp), GFP_ATOMIC);
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2005-04-16 18:20:36 -04:00
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if (pcp == NULL) {
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prom_printf("PCI_COOKIE: Fatal malloc error, aborting...\n");
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prom_halt();
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}
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pcp->pbm = pbm;
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2006-06-22 19:18:54 -04:00
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pcp->prom_node = dp;
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2006-06-29 18:07:37 -04:00
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pcp->op = of_find_device_by_node(dp);
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2006-06-22 19:18:54 -04:00
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memcpy(pcp->prom_regs, pregs,
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nregs * sizeof(struct linux_prom_pci_registers));
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2005-04-16 18:20:36 -04:00
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pcp->num_prom_regs = nregs;
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2006-06-22 19:18:54 -04:00
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/* We can't have the pcidev_cookie assignments be just
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* direct pointers into the property value, since they
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* are potentially modified by the probing process.
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*/
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prop = of_find_property(dp, "assigned-addresses", &len);
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if (!prop) {
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2005-04-16 18:20:36 -04:00
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pcp->num_prom_assignments = 0;
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2006-06-22 19:18:54 -04:00
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} else {
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memcpy(pcp->prom_assignments, prop->value, len);
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2005-04-16 18:20:36 -04:00
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pcp->num_prom_assignments =
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2006-06-22 19:18:54 -04:00
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(len / sizeof(pcp->prom_assignments[0]));
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}
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2005-04-16 18:20:36 -04:00
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2006-06-22 19:18:54 -04:00
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if (strcmp(dp->name, "ebus") == 0) {
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struct linux_prom_ebus_ranges *erng;
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2005-04-16 18:20:36 -04:00
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int iter;
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/* EBUS is special... */
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2006-06-22 19:18:54 -04:00
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prop = of_find_property(dp, "ranges", &len);
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if (!prop) {
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2005-04-16 18:20:36 -04:00
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prom_printf("EBUS: Fatal error, no range property\n");
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prom_halt();
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}
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2006-06-22 19:18:54 -04:00
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erng = prop->value;
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len = (len / sizeof(erng[0]));
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for (iter = 0; iter < len; iter++) {
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2005-04-16 18:20:36 -04:00
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struct linux_prom_ebus_ranges *ep = &erng[iter];
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struct linux_prom_pci_registers *ap;
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ap = &pcp->prom_assignments[iter];
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ap->phys_hi = ep->parent_phys_hi;
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ap->phys_mid = ep->parent_phys_mid;
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ap->phys_lo = ep->parent_phys_lo;
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ap->size_hi = 0;
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ap->size_lo = ep->size;
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}
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2006-06-22 19:18:54 -04:00
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pcp->num_prom_assignments = len;
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2005-04-16 18:20:36 -04:00
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}
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fixup_obp_assignments(pdev, pcp);
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pdev->sysdata = pcp;
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}
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void __init pci_fill_in_pbm_cookies(struct pci_bus *pbus,
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struct pci_pbm_info *pbm,
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2006-06-22 19:18:54 -04:00
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struct device_node *dp)
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2005-04-16 18:20:36 -04:00
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{
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struct pci_dev *pdev, *pdev_next;
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struct pci_bus *this_pbus, *pbus_next;
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/* This must be _safe because the cookie fillin
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routine can delete devices from the tree. */
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list_for_each_entry_safe(pdev, pdev_next, &pbus->devices, bus_list)
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2006-06-22 19:18:54 -04:00
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pdev_cookie_fillin(pbm, pdev, dp);
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2005-04-16 18:20:36 -04:00
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list_for_each_entry_safe(this_pbus, pbus_next, &pbus->children, node) {
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struct pcidev_cookie *pcp = this_pbus->self->sysdata;
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pci_fill_in_pbm_cookies(this_pbus, pbm, pcp->prom_node);
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}
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}
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static void __init bad_assignment(struct pci_dev *pdev,
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struct linux_prom_pci_registers *ap,
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struct resource *res,
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int do_prom_halt)
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{
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prom_printf("PCI: Bogus PROM assignment. BUS[%02x] DEVFN[%x]\n",
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pdev->bus->number, pdev->devfn);
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if (ap)
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prom_printf("PCI: phys[%08x:%08x:%08x] size[%08x:%08x]\n",
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ap->phys_hi, ap->phys_mid, ap->phys_lo,
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ap->size_hi, ap->size_lo);
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if (res)
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prom_printf("PCI: RES[%016lx-->%016lx:(%lx)]\n",
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res->start, res->end, res->flags);
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if (do_prom_halt)
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prom_halt();
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}
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static struct resource *
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__init get_root_resource(struct linux_prom_pci_registers *ap,
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struct pci_pbm_info *pbm)
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{
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int space = (ap->phys_hi >> 24) & 3;
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switch (space) {
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case 0:
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/* Configuration space, silently ignore it. */
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return NULL;
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case 1:
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/* 16-bit IO space */
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return &pbm->io_space;
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case 2:
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/* 32-bit MEM space */
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return &pbm->mem_space;
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case 3:
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/* 64-bit MEM space, these are allocated out of
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* the 32-bit mem_space range for the PBM, ie.
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* we just zero out the upper 32-bits.
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*/
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return &pbm->mem_space;
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default:
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2006-06-22 19:18:54 -04:00
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printk("PCI: What is resource space %x?\n", space);
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2005-04-16 18:20:36 -04:00
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return NULL;
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};
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}
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static struct resource *
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__init get_device_resource(struct linux_prom_pci_registers *ap,
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struct pci_dev *pdev)
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{
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struct resource *res;
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int breg = (ap->phys_hi & 0xff);
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switch (breg) {
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case PCI_ROM_ADDRESS:
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/* Unfortunately I have seen several cases where
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* buggy FCODE uses a space value of '1' (I/O space)
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* in the register property for the ROM address
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* so disable this sanity check for now.
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*/
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#if 0
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{
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int space = (ap->phys_hi >> 24) & 3;
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/* It had better be MEM space. */
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if (space != 2)
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bad_assignment(pdev, ap, NULL, 0);
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}
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#endif
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res = &pdev->resource[PCI_ROM_RESOURCE];
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break;
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_1:
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case PCI_BASE_ADDRESS_2:
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case PCI_BASE_ADDRESS_3:
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case PCI_BASE_ADDRESS_4:
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case PCI_BASE_ADDRESS_5:
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res = &pdev->resource[(breg - PCI_BASE_ADDRESS_0) / 4];
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break;
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default:
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bad_assignment(pdev, ap, NULL, 0);
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res = NULL;
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break;
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};
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return res;
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}
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static void __init pdev_record_assignments(struct pci_pbm_info *pbm,
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struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pcidev_cookie *pcp = pdev->sysdata;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < pcp->num_prom_assignments; i++) {
|
|
|
|
struct linux_prom_pci_registers *ap;
|
|
|
|
struct resource *root, *res;
|
|
|
|
|
|
|
|
/* The format of this property is specified in
|
|
|
|
* the PCI Bus Binding to IEEE1275-1994.
|
|
|
|
*/
|
|
|
|
ap = &pcp->prom_assignments[i];
|
|
|
|
root = get_root_resource(ap, pbm);
|
|
|
|
res = get_device_resource(ap, pdev);
|
|
|
|
if (root == NULL || res == NULL ||
|
|
|
|
res->flags == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Ok we know which resource this PROM assignment is
|
|
|
|
* for, sanity check it.
|
|
|
|
*/
|
|
|
|
if ((res->start & 0xffffffffUL) != ap->phys_lo)
|
|
|
|
bad_assignment(pdev, ap, res, 1);
|
|
|
|
|
|
|
|
/* If it is a 64-bit MEM space assignment, verify that
|
|
|
|
* the resource is too and that the upper 32-bits match.
|
|
|
|
*/
|
|
|
|
if (((ap->phys_hi >> 24) & 3) == 3) {
|
|
|
|
if (((res->flags & IORESOURCE_MEM) == 0) ||
|
|
|
|
((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
|
|
|
|
!= PCI_BASE_ADDRESS_MEM_TYPE_64))
|
|
|
|
bad_assignment(pdev, ap, res, 1);
|
|
|
|
if ((res->start >> 32) != ap->phys_mid)
|
|
|
|
bad_assignment(pdev, ap, res, 1);
|
|
|
|
|
|
|
|
/* PBM cannot generate cpu initiated PIOs
|
|
|
|
* to the full 64-bit space. Therefore the
|
|
|
|
* upper 32-bits better be zero. If it is
|
|
|
|
* not, just skip it and we will assign it
|
|
|
|
* properly ourselves.
|
|
|
|
*/
|
|
|
|
if ((res->start >> 32) != 0UL) {
|
|
|
|
printk(KERN_ERR "PCI: OBP assigns out of range MEM address "
|
|
|
|
"%016lx for region %ld on device %s\n",
|
|
|
|
res->start, (res - &pdev->resource[0]), pci_name(pdev));
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Adjust the resource into the physical address space
|
|
|
|
* of this PBM.
|
|
|
|
*/
|
|
|
|
pbm->parent->resource_adjust(pdev, res, root);
|
|
|
|
|
|
|
|
if (request_resource(root, res) < 0) {
|
2006-10-17 22:04:44 -04:00
|
|
|
int rnum;
|
|
|
|
|
2005-04-16 18:20:36 -04:00
|
|
|
/* OK, there is some conflict. But this is fine
|
|
|
|
* since we'll reassign it in the fixup pass.
|
|
|
|
*
|
2006-10-17 22:04:44 -04:00
|
|
|
* Do not print the warning for ROM resources
|
|
|
|
* as such a conflict is quite common and
|
|
|
|
* harmless as the ROM bar is disabled.
|
2005-04-16 18:20:36 -04:00
|
|
|
*/
|
2006-10-17 22:04:44 -04:00
|
|
|
rnum = (res - &pdev->resource[0]);
|
|
|
|
if (rnum != PCI_ROM_RESOURCE)
|
|
|
|
printk(KERN_ERR "PCI: Resource collision, "
|
|
|
|
"region %d "
|
2005-04-16 18:20:36 -04:00
|
|
|
"[%016lx:%016lx] of device %s\n",
|
2006-10-17 22:04:44 -04:00
|
|
|
rnum,
|
2005-04-16 18:20:36 -04:00
|
|
|
res->start, res->end,
|
|
|
|
pci_name(pdev));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init pci_record_assignments(struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &pbus->devices, bus_list)
|
|
|
|
pdev_record_assignments(pbm, dev);
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
pci_record_assignments(pbm, bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return non-zero if PDEV has implicit I/O resources even
|
|
|
|
* though it may not have an I/O base address register
|
|
|
|
* active.
|
|
|
|
*/
|
|
|
|
static int __init has_implicit_io(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
int class = pdev->class >> 8;
|
|
|
|
|
|
|
|
if (class == PCI_CLASS_NOT_DEFINED ||
|
|
|
|
class == PCI_CLASS_NOT_DEFINED_VGA ||
|
|
|
|
class == PCI_CLASS_STORAGE_IDE ||
|
|
|
|
(pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init pdev_assign_unassigned(struct pci_pbm_info *pbm,
|
|
|
|
struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
u16 cmd;
|
|
|
|
int i, io_seen, mem_seen;
|
|
|
|
|
|
|
|
io_seen = mem_seen = 0;
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
|
|
struct resource *root, *res;
|
|
|
|
unsigned long size, min, max, align;
|
|
|
|
|
|
|
|
res = &pdev->resource[i];
|
|
|
|
|
|
|
|
if (res->flags & IORESOURCE_IO)
|
|
|
|
io_seen++;
|
|
|
|
else if (res->flags & IORESOURCE_MEM)
|
|
|
|
mem_seen++;
|
|
|
|
|
|
|
|
/* If it is already assigned or the resource does
|
|
|
|
* not exist, there is nothing to do.
|
|
|
|
*/
|
|
|
|
if (res->parent != NULL || res->flags == 0UL)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Determine the root we allocate from. */
|
|
|
|
if (res->flags & IORESOURCE_IO) {
|
|
|
|
root = &pbm->io_space;
|
|
|
|
min = root->start + 0x400UL;
|
|
|
|
max = root->end;
|
|
|
|
} else {
|
|
|
|
root = &pbm->mem_space;
|
|
|
|
min = root->start;
|
|
|
|
max = min + 0x80000000UL;
|
|
|
|
}
|
|
|
|
|
|
|
|
size = res->end - res->start;
|
|
|
|
align = size + 1;
|
|
|
|
if (allocate_resource(root, res, size + 1, min, max, align, NULL, NULL) < 0) {
|
|
|
|
/* uh oh */
|
|
|
|
prom_printf("PCI: Failed to allocate resource %d for %s\n",
|
|
|
|
i, pci_name(pdev));
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Update PCI config space. */
|
|
|
|
pbm->parent->base_address_update(pdev, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Special case, disable the ROM. Several devices
|
|
|
|
* act funny (ie. do not respond to memory space writes)
|
|
|
|
* when it is left enabled. A good example are Qlogic,ISP
|
|
|
|
* adapters.
|
|
|
|
*/
|
|
|
|
pci_read_config_dword(pdev, PCI_ROM_ADDRESS, ®);
|
|
|
|
reg &= ~PCI_ROM_ADDRESS_ENABLE;
|
|
|
|
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, reg);
|
|
|
|
|
|
|
|
/* If we saw I/O or MEM resources, enable appropriate
|
|
|
|
* bits in PCI command register.
|
|
|
|
*/
|
|
|
|
if (io_seen || mem_seen) {
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
|
|
if (io_seen || has_implicit_io(pdev))
|
|
|
|
cmd |= PCI_COMMAND_IO;
|
|
|
|
if (mem_seen)
|
|
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If this is a PCI bridge or an IDE controller,
|
|
|
|
* enable bus mastering. In the former case also
|
|
|
|
* set the cache line size correctly.
|
|
|
|
*/
|
|
|
|
if (((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) ||
|
|
|
|
(((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) &&
|
|
|
|
((pdev->class & 0x80) != 0))) {
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
|
|
cmd |= PCI_COMMAND_MASTER;
|
|
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
|
|
|
|
|
|
if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
|
|
|
|
pci_write_config_byte(pdev,
|
|
|
|
PCI_CACHE_LINE_SIZE,
|
|
|
|
(64 / sizeof(u32)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init pci_assign_unassigned(struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &pbus->devices, bus_list)
|
|
|
|
pdev_assign_unassigned(pbm, dev);
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
pci_assign_unassigned(pbm, bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init pdev_fixup_irq(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pcidev_cookie *pcp = pdev->sysdata;
|
2006-06-29 18:07:37 -04:00
|
|
|
struct of_device *op = pcp->op;
|
2005-04-16 18:20:36 -04:00
|
|
|
|
2006-06-29 18:07:37 -04:00
|
|
|
if (op->irqs[0] == 0xffffffff) {
|
|
|
|
pdev->irq = PCI_IRQ_NONE;
|
2005-04-16 18:20:36 -04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2006-06-29 18:07:37 -04:00
|
|
|
pdev->irq = op->irqs[0];
|
2005-04-16 18:20:36 -04:00
|
|
|
|
|
|
|
pci_write_config_byte(pdev, PCI_INTERRUPT_LINE,
|
|
|
|
pdev->irq & PCI_IRQ_INO);
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init pci_fixup_irq(struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &pbus->devices, bus_list)
|
|
|
|
pdev_fixup_irq(dev);
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
pci_fixup_irq(pbm, bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdev_setup_busmastering(struct pci_dev *pdev, int is_66mhz)
|
|
|
|
{
|
|
|
|
u16 cmd;
|
|
|
|
u8 hdr_type, min_gnt, ltimer;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
|
|
cmd |= PCI_COMMAND_MASTER;
|
|
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
|
|
|
|
|
|
/* Read it back, if the mastering bit did not
|
|
|
|
* get set, the device does not support bus
|
|
|
|
* mastering so we have nothing to do here.
|
|
|
|
*/
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
|
|
if ((cmd & PCI_COMMAND_MASTER) == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Set correct cache line size, 64-byte on all
|
|
|
|
* Sparc64 PCI systems. Note that the value is
|
|
|
|
* measured in 32-bit words.
|
|
|
|
*/
|
|
|
|
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
|
|
|
|
64 / sizeof(u32));
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr_type);
|
|
|
|
hdr_type &= ~0x80;
|
|
|
|
if (hdr_type != PCI_HEADER_TYPE_NORMAL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* If the latency timer is already programmed with a non-zero
|
|
|
|
* value, assume whoever set it (OBP or whoever) knows what
|
|
|
|
* they are doing.
|
|
|
|
*/
|
|
|
|
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, <imer);
|
|
|
|
if (ltimer != 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* XXX Since I'm tipping off the min grant value to
|
|
|
|
* XXX choose a suitable latency timer value, I also
|
|
|
|
* XXX considered making use of the max latency value
|
|
|
|
* XXX as well. Unfortunately I've seen too many bogusly
|
|
|
|
* XXX low settings for it to the point where it lacks
|
|
|
|
* XXX any usefulness. In one case, an ethernet card
|
|
|
|
* XXX claimed a min grant of 10 and a max latency of 5.
|
|
|
|
* XXX Now, if I had two such cards on the same bus I
|
|
|
|
* XXX could not set the desired burst period (calculated
|
|
|
|
* XXX from min grant) without violating the max latency
|
|
|
|
* XXX bound. Duh...
|
|
|
|
* XXX
|
|
|
|
* XXX I blame dumb PC bios implementors for stuff like
|
|
|
|
* XXX this, most of them don't even try to do something
|
|
|
|
* XXX sensible with latency timer values and just set some
|
|
|
|
* XXX default value (usually 32) into every device.
|
|
|
|
*/
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, PCI_MIN_GNT, &min_gnt);
|
|
|
|
|
|
|
|
if (min_gnt == 0) {
|
|
|
|
/* If no min_gnt setting then use a default
|
|
|
|
* value.
|
|
|
|
*/
|
|
|
|
if (is_66mhz)
|
|
|
|
ltimer = 16;
|
|
|
|
else
|
|
|
|
ltimer = 32;
|
|
|
|
} else {
|
|
|
|
int shift_factor;
|
|
|
|
|
|
|
|
if (is_66mhz)
|
|
|
|
shift_factor = 2;
|
|
|
|
else
|
|
|
|
shift_factor = 3;
|
|
|
|
|
|
|
|
/* Use a default value when the min_gnt value
|
|
|
|
* is erroneously high.
|
|
|
|
*/
|
|
|
|
if (((unsigned int) min_gnt << shift_factor) > 512 ||
|
|
|
|
((min_gnt << shift_factor) & 0xff) == 0) {
|
|
|
|
ltimer = 8 << shift_factor;
|
|
|
|
} else {
|
|
|
|
ltimer = min_gnt << shift_factor;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ltimer);
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_determine_66mhz_disposition(struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
int all_are_66mhz;
|
|
|
|
u16 status;
|
|
|
|
|
|
|
|
if (pbm->is_66mhz_capable == 0) {
|
|
|
|
all_are_66mhz = 0;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
all_are_66mhz = 1;
|
|
|
|
list_for_each_entry(pdev, &pbus->devices, bus_list) {
|
|
|
|
pci_read_config_word(pdev, PCI_STATUS, &status);
|
|
|
|
if (!(status & PCI_STATUS_66MHZ)) {
|
|
|
|
all_are_66mhz = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
pbm->all_devs_66mhz = all_are_66mhz;
|
|
|
|
|
|
|
|
printk("PCI%d(PBM%c): Bus running at %dMHz\n",
|
|
|
|
pbm->parent->index,
|
|
|
|
(pbm == &pbm->parent->pbm_A) ? 'A' : 'B',
|
|
|
|
(all_are_66mhz ? 66 : 33));
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_setup_busmastering(struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
int is_66mhz;
|
|
|
|
|
|
|
|
is_66mhz = pbm->is_66mhz_capable && pbm->all_devs_66mhz;
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &pbus->devices, bus_list)
|
|
|
|
pdev_setup_busmastering(dev, is_66mhz);
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
pci_setup_busmastering(pbm, bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_register_legacy_regions(struct resource *io_res,
|
|
|
|
struct resource *mem_res)
|
|
|
|
{
|
|
|
|
struct resource *p;
|
|
|
|
|
|
|
|
/* VGA Video RAM. */
|
2006-03-06 16:48:40 -05:00
|
|
|
p = kzalloc(sizeof(*p), GFP_KERNEL);
|
2005-04-16 18:20:36 -04:00
|
|
|
if (!p)
|
|
|
|
return;
|
|
|
|
|
|
|
|
p->name = "Video RAM area";
|
|
|
|
p->start = mem_res->start + 0xa0000UL;
|
|
|
|
p->end = p->start + 0x1ffffUL;
|
|
|
|
p->flags = IORESOURCE_BUSY;
|
|
|
|
request_resource(mem_res, p);
|
|
|
|
|
2006-03-06 16:48:40 -05:00
|
|
|
p = kzalloc(sizeof(*p), GFP_KERNEL);
|
2005-04-16 18:20:36 -04:00
|
|
|
if (!p)
|
|
|
|
return;
|
|
|
|
|
|
|
|
p->name = "System ROM";
|
|
|
|
p->start = mem_res->start + 0xf0000UL;
|
|
|
|
p->end = p->start + 0xffffUL;
|
|
|
|
p->flags = IORESOURCE_BUSY;
|
|
|
|
request_resource(mem_res, p);
|
|
|
|
|
2006-03-06 16:48:40 -05:00
|
|
|
p = kzalloc(sizeof(*p), GFP_KERNEL);
|
2005-04-16 18:20:36 -04:00
|
|
|
if (!p)
|
|
|
|
return;
|
|
|
|
|
|
|
|
p->name = "Video ROM";
|
|
|
|
p->start = mem_res->start + 0xc0000UL;
|
|
|
|
p->end = p->start + 0x7fffUL;
|
|
|
|
p->flags = IORESOURCE_BUSY;
|
|
|
|
request_resource(mem_res, p);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Generic helper routines for PCI error reporting. */
|
|
|
|
void pci_scan_for_target_abort(struct pci_controller_info *p,
|
|
|
|
struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
list_for_each_entry(pdev, &pbus->devices, bus_list) {
|
|
|
|
u16 status, error_bits;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, PCI_STATUS, &status);
|
|
|
|
error_bits =
|
|
|
|
(status & (PCI_STATUS_SIG_TARGET_ABORT |
|
|
|
|
PCI_STATUS_REC_TARGET_ABORT));
|
|
|
|
if (error_bits) {
|
|
|
|
pci_write_config_word(pdev, PCI_STATUS, error_bits);
|
|
|
|
printk("PCI%d(PBM%c): Device [%s] saw Target Abort [%016x]\n",
|
|
|
|
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
|
|
|
|
pci_name(pdev), status);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
pci_scan_for_target_abort(p, pbm, bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_scan_for_master_abort(struct pci_controller_info *p,
|
|
|
|
struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
list_for_each_entry(pdev, &pbus->devices, bus_list) {
|
|
|
|
u16 status, error_bits;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, PCI_STATUS, &status);
|
|
|
|
error_bits =
|
|
|
|
(status & (PCI_STATUS_REC_MASTER_ABORT));
|
|
|
|
if (error_bits) {
|
|
|
|
pci_write_config_word(pdev, PCI_STATUS, error_bits);
|
|
|
|
printk("PCI%d(PBM%c): Device [%s] received Master Abort [%016x]\n",
|
|
|
|
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
|
|
|
|
pci_name(pdev), status);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
pci_scan_for_master_abort(p, pbm, bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_scan_for_parity_error(struct pci_controller_info *p,
|
|
|
|
struct pci_pbm_info *pbm,
|
|
|
|
struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
list_for_each_entry(pdev, &pbus->devices, bus_list) {
|
|
|
|
u16 status, error_bits;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, PCI_STATUS, &status);
|
|
|
|
error_bits =
|
|
|
|
(status & (PCI_STATUS_PARITY |
|
|
|
|
PCI_STATUS_DETECTED_PARITY));
|
|
|
|
if (error_bits) {
|
|
|
|
pci_write_config_word(pdev, PCI_STATUS, error_bits);
|
|
|
|
printk("PCI%d(PBM%c): Device [%s] saw Parity Error [%016x]\n",
|
|
|
|
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
|
|
|
|
pci_name(pdev), status);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(bus, &pbus->children, node)
|
|
|
|
pci_scan_for_parity_error(p, pbm, bus);
|
|
|
|
}
|